25d7ba19c9
Remove comment about workaround of not working 'reset halt' - not needed as 'reset halt' is working as expected @ EDBG with srst_only. Add srst_pulls_trst to reset_config as it no more triggers an error. Change-Id: I47cf445690c46ccfb866900cddbfcaefc8649f82 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3722 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
82 lines
2.3 KiB
INI
82 lines
2.3 KiB
INI
#
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# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
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#
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#
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# samdXX devices only support SWD transports.
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91samd
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 2kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x800
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
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# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
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#
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# dsu_reset_deassert configures whether we want to run or halt out of reset,
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# then instruct the DSU to let us out of reset.
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$_TARGETNAME configure -event reset-deassert-post {
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at91samd dsu_reset_deassert
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}
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# SRST (wired to RESET_N) resets debug circuitry
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reset_config srst_gates_jtag srst_pulls_trst
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# Do not use a reset button with other SWD adapter than Atmel's EDBG.
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# DSU usually locks MCU in reset state until you issue a reset command
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# in OpenOCD.
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# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
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# Other members of family usually use SYSCLK = 4 MHz after reset.
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# Datasheet does not specify SYSCLK to SWD clock ratio.
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# Usually used SYSCLK/6 is slow, testing shows that debugging can
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# work @ SYSCLK/2 but your mileage may vary.
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# This limit is most probably imposed by incorrectly handled SWD WAIT
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# on some SWD adapters.
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adapter_khz 400
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# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
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# without problem at maximal clock speed. Atmel recommends
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# adapter speed less than 10 * CPU clock.
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# adapter_khz 5000
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
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