570 lines
14 KiB
C
570 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2017 by Grzegorz Kostka, kostka.grzegorz@gmail.com *
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* *
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* Based on bcm2835gpio.c *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <jtag/interface.h>
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#include <transport/transport.h>
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#include "bitbang.h"
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#include <sys/mman.h>
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#define IMX_GPIO_BASE 0x0209c000
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#define IMX_GPIO_SIZE 0x00004000
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#define IMX_GPIO_REGS_COUNT 8
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static uint32_t imx_gpio_peri_base = IMX_GPIO_BASE;
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struct imx_gpio_regs {
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uint32_t dr;
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uint32_t gdir;
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uint32_t psr;
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uint32_t icr1;
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uint32_t icr2;
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uint32_t imr;
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uint32_t isr;
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uint32_t edge_sel;
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} __attribute__((aligned(IMX_GPIO_SIZE)));
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static int dev_mem_fd;
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static volatile struct imx_gpio_regs *pio_base;
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/* GPIO setup functions */
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static inline bool gpio_mode_get(int g)
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{
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return pio_base[g / 32].gdir >> (g & 0x1F) & 1;
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}
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static inline void gpio_mode_input_set(int g)
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{
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pio_base[g / 32].gdir &= ~(1u << (g & 0x1F));
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}
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static inline void gpio_mode_output_set(int g)
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{
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pio_base[g / 32].gdir |= (1u << (g & 0x1F));
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}
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static inline void gpio_mode_set(int g, int m)
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{
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(m) ? gpio_mode_output_set(g) : gpio_mode_input_set(g);
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}
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static inline void gpio_set(int g)
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{
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pio_base[g / 32].dr |= (1u << (g & 0x1F));
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}
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static inline void gpio_clear(int g)
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{
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pio_base[g / 32].dr &= ~(1u << (g & 0x1F));
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}
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static inline bool gpio_level(int g)
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{
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return pio_base[g / 32].dr >> (g & 0x1F) & 1;
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}
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static bb_value_t imx_gpio_read(void);
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static int imx_gpio_write(int tck, int tms, int tdi);
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static int imx_gpio_swdio_read(void);
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static void imx_gpio_swdio_drive(bool is_output);
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static int imx_gpio_swd_write(int swclk, int swdio);
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static int imx_gpio_init(void);
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static int imx_gpio_quit(void);
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static struct bitbang_interface imx_gpio_bitbang = {
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.read = imx_gpio_read,
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.write = imx_gpio_write,
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.swdio_read = imx_gpio_swdio_read,
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.swdio_drive = imx_gpio_swdio_drive,
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.swd_write = imx_gpio_swd_write,
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.blink = NULL
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};
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/* GPIO numbers for each signal. Negative values are invalid */
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static int tck_gpio = -1;
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static int tck_gpio_mode;
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static int tms_gpio = -1;
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static int tms_gpio_mode;
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static int tdi_gpio = -1;
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static int tdi_gpio_mode;
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static int tdo_gpio = -1;
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static int tdo_gpio_mode;
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static int trst_gpio = -1;
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static int trst_gpio_mode;
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static int srst_gpio = -1;
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static int srst_gpio_mode;
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static int swclk_gpio = -1;
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static int swclk_gpio_mode;
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static int swdio_gpio = -1;
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static int swdio_gpio_mode;
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/* Transition delay coefficients. Tuned for IMX6UL 528MHz. Adjusted
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* experimentally for:10kHz, 100Khz, 500KHz. Speeds above 800Khz are impossible
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* to reach via memory mapped method (at least for IMX6UL@528MHz).
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* Measured mmap raw GPIO toggling speed on IMX6UL@528MHz: 1.3MHz.
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*/
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static int speed_coeff = 50000;
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static int speed_offset = 100;
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static unsigned int jtag_delay;
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static bb_value_t imx_gpio_read(void)
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{
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return gpio_level(tdo_gpio) ? BB_HIGH : BB_LOW;
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}
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static int imx_gpio_write(int tck, int tms, int tdi)
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{
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tms ? gpio_set(tms_gpio) : gpio_clear(tms_gpio);
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tdi ? gpio_set(tdi_gpio) : gpio_clear(tdi_gpio);
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tck ? gpio_set(tck_gpio) : gpio_clear(tck_gpio);
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for (unsigned int i = 0; i < jtag_delay; i++)
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asm volatile ("");
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return ERROR_OK;
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}
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static int imx_gpio_swd_write(int swclk, int swdio)
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{
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swdio ? gpio_set(swdio_gpio) : gpio_clear(swdio_gpio);
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swclk ? gpio_set(swclk_gpio) : gpio_clear(swclk_gpio);
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for (unsigned int i = 0; i < jtag_delay; i++)
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asm volatile ("");
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return ERROR_OK;
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}
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/* (1) assert or (0) deassert reset lines */
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static int imx_gpio_reset(int trst, int srst)
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{
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if (trst_gpio != -1)
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trst ? gpio_clear(trst_gpio) : gpio_set(trst_gpio);
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if (srst_gpio != -1)
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srst ? gpio_clear(srst_gpio) : gpio_set(srst_gpio);
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return ERROR_OK;
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}
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static void imx_gpio_swdio_drive(bool is_output)
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{
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if (is_output)
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gpio_mode_output_set(swdio_gpio);
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else
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gpio_mode_input_set(swdio_gpio);
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}
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static int imx_gpio_swdio_read(void)
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{
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return gpio_level(swdio_gpio);
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}
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static int imx_gpio_khz(int khz, int *jtag_speed)
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{
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if (!khz) {
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LOG_DEBUG("RCLK not supported");
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return ERROR_FAIL;
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}
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*jtag_speed = speed_coeff/khz - speed_offset;
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if (*jtag_speed < 0)
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*jtag_speed = 0;
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return ERROR_OK;
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}
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static int imx_gpio_speed_div(int speed, int *khz)
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{
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*khz = speed_coeff/(speed + speed_offset);
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return ERROR_OK;
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}
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static int imx_gpio_speed(int speed)
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{
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jtag_delay = speed;
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return ERROR_OK;
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}
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static int is_gpio_valid(int gpio)
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{
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return gpio >= 0 && gpio < 32 * IMX_GPIO_REGS_COUNT;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionums)
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{
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if (CMD_ARGC == 4) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
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} else if (CMD_ARGC != 0) {
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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command_print(CMD,
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"imx_gpio GPIO config: tck = %d, tms = %d, tdi = %d, tdo = %d",
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tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionum_tck)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
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command_print(CMD, "imx_gpio GPIO config: tck = %d", tck_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionum_tms)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio);
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command_print(CMD, "imx_gpio GPIO config: tms = %d", tms_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionum_tdo)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio);
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command_print(CMD, "imx_gpio GPIO config: tdo = %d", tdo_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionum_tdi)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio);
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command_print(CMD, "imx_gpio GPIO config: tdi = %d", tdi_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionum_srst)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio);
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command_print(CMD, "imx_gpio GPIO config: srst = %d", srst_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_jtag_gpionum_trst)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio);
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command_print(CMD, "imx_gpio GPIO config: trst = %d", trst_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_swd_gpionums)
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{
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if (CMD_ARGC == 2) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio);
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} else if (CMD_ARGC != 0) {
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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command_print(CMD,
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"imx_gpio GPIO nums: swclk = %d, swdio = %d",
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swclk_gpio, swdio_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_swd_gpionum_swclk)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
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command_print(CMD, "imx_gpio num: swclk = %d", swclk_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_swd_gpionum_swdio)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio);
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command_print(CMD, "imx_gpio num: swdio = %d", swdio_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_speed_coeffs)
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{
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if (CMD_ARGC == 2) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], speed_coeff);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], speed_offset);
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}
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command_print(CMD, "imx_gpio: speed_coeffs = %d, speed_offset = %d",
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speed_coeff, speed_offset);
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return ERROR_OK;
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}
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COMMAND_HANDLER(imx_gpio_handle_peripheral_base)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], imx_gpio_peri_base);
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command_print(CMD, "imx_gpio: peripheral_base = 0x%08x",
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imx_gpio_peri_base);
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return ERROR_OK;
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}
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static const struct command_registration imx_gpio_command_handlers[] = {
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{
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.name = "imx_gpio_jtag_nums",
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.handler = &imx_gpio_handle_jtag_gpionums,
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.mode = COMMAND_CONFIG,
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.help = "gpio numbers for tck, tms, tdi, tdo. (in that order)",
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.usage = "[tck tms tdi tdo]",
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},
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{
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.name = "imx_gpio_tck_num",
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.handler = &imx_gpio_handle_jtag_gpionum_tck,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tck.",
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.usage = "[tck]",
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},
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{
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.name = "imx_gpio_tms_num",
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.handler = &imx_gpio_handle_jtag_gpionum_tms,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tms.",
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.usage = "[tms]",
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},
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{
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.name = "imx_gpio_tdo_num",
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.handler = &imx_gpio_handle_jtag_gpionum_tdo,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tdo.",
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.usage = "[tdo]",
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},
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{
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.name = "imx_gpio_tdi_num",
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.handler = &imx_gpio_handle_jtag_gpionum_tdi,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tdi.",
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.usage = "[tdi]",
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},
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{
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.name = "imx_gpio_swd_nums",
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.handler = &imx_gpio_handle_swd_gpionums,
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.mode = COMMAND_CONFIG,
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.help = "gpio numbers for swclk, swdio. (in that order)",
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.usage = "[swclk swdio]",
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},
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{
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.name = "imx_gpio_swclk_num",
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.handler = &imx_gpio_handle_swd_gpionum_swclk,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for swclk.",
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.usage = "[swclk]",
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},
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{
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.name = "imx_gpio_swdio_num",
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.handler = &imx_gpio_handle_swd_gpionum_swdio,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for swdio.",
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.usage = "[swdio]",
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},
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{
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.name = "imx_gpio_srst_num",
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.handler = &imx_gpio_handle_jtag_gpionum_srst,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for srst.",
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.usage = "[srst]",
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},
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{
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.name = "imx_gpio_trst_num",
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.handler = &imx_gpio_handle_jtag_gpionum_trst,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for trst.",
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.usage = "[trst]",
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},
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{
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.name = "imx_gpio_speed_coeffs",
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.handler = &imx_gpio_handle_speed_coeffs,
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.mode = COMMAND_CONFIG,
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.help = "SPEED_COEFF and SPEED_OFFSET for delay calculations.",
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.usage = "[SPEED_COEFF SPEED_OFFSET]",
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},
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{
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.name = "imx_gpio_peripheral_base",
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.handler = &imx_gpio_handle_peripheral_base,
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.mode = COMMAND_CONFIG,
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.help = "peripheral base to access GPIOs (0x0209c000 for most IMX).",
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.usage = "[base]",
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},
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COMMAND_REGISTRATION_DONE
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};
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static const char * const imx_gpio_transports[] = { "jtag", "swd", NULL };
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static struct jtag_interface imx_gpio_interface = {
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.supported = DEBUG_CAP_TMS_SEQ,
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.execute_queue = bitbang_execute_queue,
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};
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struct adapter_driver imx_gpio_adapter_driver = {
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.name = "imx_gpio",
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.transports = imx_gpio_transports,
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.commands = imx_gpio_command_handlers,
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.init = imx_gpio_init,
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.quit = imx_gpio_quit,
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.reset = imx_gpio_reset,
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.speed = imx_gpio_speed,
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.khz = imx_gpio_khz,
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.speed_div = imx_gpio_speed_div,
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.jtag_ops = &imx_gpio_interface,
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.swd_ops = &bitbang_swd,
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};
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static bool imx_gpio_jtag_mode_possible(void)
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{
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if (!is_gpio_valid(tck_gpio))
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return 0;
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if (!is_gpio_valid(tms_gpio))
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return 0;
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if (!is_gpio_valid(tdi_gpio))
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return 0;
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if (!is_gpio_valid(tdo_gpio))
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return 0;
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return 1;
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}
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static bool imx_gpio_swd_mode_possible(void)
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{
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if (!is_gpio_valid(swclk_gpio))
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return 0;
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if (!is_gpio_valid(swdio_gpio))
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return 0;
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return 1;
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}
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static int imx_gpio_init(void)
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{
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bitbang_interface = &imx_gpio_bitbang;
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LOG_INFO("imx_gpio GPIO JTAG/SWD bitbang driver");
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if (transport_is_jtag() && !imx_gpio_jtag_mode_possible()) {
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LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
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return ERROR_JTAG_INIT_FAILED;
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}
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if (transport_is_swd() && !imx_gpio_swd_mode_possible()) {
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LOG_ERROR("Require swclk and swdio gpio for SWD mode");
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return ERROR_JTAG_INIT_FAILED;
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}
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dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
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if (dev_mem_fd < 0) {
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LOG_ERROR("open: %s", strerror(errno));
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return ERROR_JTAG_INIT_FAILED;
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}
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LOG_INFO("imx_gpio mmap: pagesize: %u, regionsize: %u",
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(unsigned int) sysconf(_SC_PAGE_SIZE), IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE);
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pio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE,
|
|
PROT_READ | PROT_WRITE,
|
|
MAP_SHARED, dev_mem_fd, imx_gpio_peri_base);
|
|
|
|
if (pio_base == MAP_FAILED) {
|
|
LOG_ERROR("mmap: %s", strerror(errno));
|
|
close(dev_mem_fd);
|
|
return ERROR_JTAG_INIT_FAILED;
|
|
}
|
|
|
|
/*
|
|
* Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
|
|
* as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
|
|
*/
|
|
if (transport_is_jtag()) {
|
|
tdo_gpio_mode = gpio_mode_get(tdo_gpio);
|
|
tdi_gpio_mode = gpio_mode_get(tdi_gpio);
|
|
tck_gpio_mode = gpio_mode_get(tck_gpio);
|
|
tms_gpio_mode = gpio_mode_get(tms_gpio);
|
|
|
|
gpio_clear(tdi_gpio);
|
|
gpio_clear(tck_gpio);
|
|
gpio_set(tms_gpio);
|
|
|
|
gpio_mode_input_set(tdo_gpio);
|
|
gpio_mode_output_set(tdi_gpio);
|
|
gpio_mode_output_set(tck_gpio);
|
|
gpio_mode_output_set(tms_gpio);
|
|
|
|
if (trst_gpio != -1) {
|
|
trst_gpio_mode = gpio_mode_get(trst_gpio);
|
|
gpio_set(trst_gpio);
|
|
gpio_mode_output_set(trst_gpio);
|
|
}
|
|
}
|
|
|
|
if (transport_is_swd()) {
|
|
swclk_gpio_mode = gpio_mode_get(swclk_gpio);
|
|
swdio_gpio_mode = gpio_mode_get(swdio_gpio);
|
|
|
|
gpio_clear(swdio_gpio);
|
|
gpio_clear(swclk_gpio);
|
|
gpio_mode_output_set(swclk_gpio);
|
|
gpio_mode_output_set(swdio_gpio);
|
|
}
|
|
|
|
if (srst_gpio != -1) {
|
|
srst_gpio_mode = gpio_mode_get(srst_gpio);
|
|
gpio_set(srst_gpio);
|
|
gpio_mode_output_set(srst_gpio);
|
|
}
|
|
|
|
LOG_DEBUG("saved pinmux settings: tck %d tms %d tdi %d "
|
|
"tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode,
|
|
tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int imx_gpio_quit(void)
|
|
{
|
|
if (transport_is_jtag()) {
|
|
gpio_mode_set(tdo_gpio, tdo_gpio_mode);
|
|
gpio_mode_set(tdi_gpio, tdi_gpio_mode);
|
|
gpio_mode_set(tck_gpio, tck_gpio_mode);
|
|
gpio_mode_set(tms_gpio, tms_gpio_mode);
|
|
|
|
if (trst_gpio != -1)
|
|
gpio_mode_set(trst_gpio, trst_gpio_mode);
|
|
}
|
|
|
|
if (transport_is_swd()) {
|
|
gpio_mode_set(swclk_gpio, swclk_gpio_mode);
|
|
gpio_mode_set(swdio_gpio, swdio_gpio_mode);
|
|
}
|
|
|
|
if (srst_gpio != -1)
|
|
gpio_mode_set(srst_gpio, srst_gpio_mode);
|
|
|
|
return ERROR_OK;
|
|
}
|