5a0b4889d0
GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver. Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164). Configuration file is added because its cortex-M23 CPU ID is different. I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32, but nowadays quick solution is welcome. Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com> Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8 Reviewed-on: https://review.openocd.org/c/openocd/+/6527 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
75 lines
1.8 KiB
INI
75 lines
1.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for GigaDevice gd32e23x Cortex-M23 Series
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# https://www.gigadevice.com/microcontroller/gd32e230c8t6/
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#
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# gd32e23x devices support SWD transports only.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME gd32e23x
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 4kB (as found on some GD32E230s)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1000
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}
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# Allow overriding the Flash bank size
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if { [info exists FLASH_SIZE] } {
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set _FLASH_SIZE $FLASH_SIZE
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} else {
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# autodetect size
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set _FLASH_SIZE 0
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# this is the SW-DP tap id not the jtag tap id
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set _CPUTAPID 0x0bf11477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
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# SWD speed (may be updated to higher value in board config file)
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adapter speed 1000
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Debug clock enable
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# RCU_APB2EN |= DBGMCUEN
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mmw 0x40021018 0x00400000 0
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# Stop watchdog counters during halt
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# DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
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mmw 0x40015804 0x00000307 0
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}
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