2053120ba1
ESP32-S3 is a dual core Xtensa SoC Not full featured yet. Some of the missing functionality: -Semihosting -Flash breakpoints -Flash loader -Apptrace -FreeRTOS Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794 Reviewed-on: https://review.openocd.org/c/openocd/+/6990 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
22 lines
759 B
INI
22 lines
759 B
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog.
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#
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# For example, OpenOCD can be started for ESP32-S3 debugging on
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#
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# openocd -f board/esp32s3-ftdi.cfg
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#
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# Source the JTAG interface configuration file
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source [find interface/ftdi/esp32_devkitj_v1.cfg]
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# Source the ESP32-S3 configuration file
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source [find target/esp32s3.cfg]
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# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
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# do not relate to OpenOCD trying to read from a memory range without physical
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# memory being present there), you can try lowering this.
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#
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# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
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# if CPU frequency is 160MHz or 240MHz.
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adapter speed 20000
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