c945d6e616
Create the TPIU and SWO device in target config file. Replace the target event 'trace-config' with the TPIU/SWO event 'post-enable'. Extend the existing code in the event handler to properly set the gpio mode and speed to permit synchronous trace. This patch is not exhaustive of all the targets that have SWO, but has to be considered as an initial example. Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5859 Tested-by: jenkins Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
309 lines
9.2 KiB
INI
309 lines
9.2 KiB
INI
# script for stm32h7x family
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#
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# stm32h7 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32h7x
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}
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if { [info exists DUAL_BANK] } {
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set $_CHIPNAME.DUAL_BANK $DUAL_BANK
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unset DUAL_BANK
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} else {
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set $_CHIPNAME.DUAL_BANK 0
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}
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if { [info exists DUAL_CORE] } {
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set $_CHIPNAME.DUAL_CORE $DUAL_CORE
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unset DUAL_CORE
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} else {
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set $_CHIPNAME.DUAL_CORE 0
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}
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# Issue a warning when hla is used, and fallback to single core configuration
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if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
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echo "Warning : hla does not support multicore debugging"
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set $_CHIPNAME.DUAL_CORE 0
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}
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if { [info exists USE_CTI] } {
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set $_CHIPNAME.USE_CTI $USE_CTI
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unset USE_CTI
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} else {
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set $_CHIPNAME.USE_CTI 0
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}
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# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
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if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
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echo "Warning : could not use CTI with a single core device, CTI is disabled"
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set $_CHIPNAME.USE_CTI 0
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} {
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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if {![using_hla]} {
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# STM32H7 provides an APB-AP at access port 2, which allows the access to
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# the debug and trace features on the system APB System Debug Bus (APB-D).
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target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
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swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
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}
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target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
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$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
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if {[set $_CHIPNAME.DUAL_BANK]} {
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flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
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}
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if {[set $_CHIPNAME.DUAL_CORE]} {
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target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
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$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
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if {[set $_CHIPNAME.DUAL_BANK]} {
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flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
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}
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}
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# Make sure that cpu0 is selected
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targets $_CHIPNAME.cpu0
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
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} else {
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if { [info exists OCTOSPI1] && $OCTOSPI1 } {
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set a [llength [flash list]]
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set _OCTOSPINAME1 $_CHIPNAME.octospi1
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flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
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}
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if { [info exists OCTOSPI2] && $OCTOSPI2 } {
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set b [llength [flash list]]
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set _OCTOSPINAME2 $_CHIPNAME.octospi2
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flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
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}
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}
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter speed 1800
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# use hardware reset
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#
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# The STM32H7 does not support connect_assert_srst mode because the AXI is
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# unavailable while SRST is asserted, and that is used to access the DBGMCU
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# component at 0x5C001000 in the examine-end event handler.
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#
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# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
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# of the default AP0, and that works with SRST asserted; however, nonzero AP
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# usage does not work with HLA, so is not done by default. That change could be
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# made in a local configuration file if connect_assert_srst mode is needed for
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# a specific application and a non-HLA adapter is in use.
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reset_config srst_only srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
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if {[set $_CHIPNAME.DUAL_CORE]} {
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$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
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}
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# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
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# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
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# makes the data access cacheable. This allows reading and writing data in the
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# CPU cache from the debugger, which is far more useful than going straight to
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# RAM when operating on typical variables, and is generally no worse when
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# operating on special memory locations.
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$_CHIPNAME.dap apcsw 0x08000000 0x08000000
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}
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$_CHIPNAME.cpu0 configure -event examine-end {
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# Enable D3 and D1 DBG clocks
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# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
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stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
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stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
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stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
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# Stop watchdog counters during halt
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# DBGMCU_APB3FZ1 |= WWDG1
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stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
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# DBGMCU_APB1LFZ1 |= WWDG2
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stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
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# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
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stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
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# Enable clock for tracing
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# DBGMCU_CR |= TRACECLKEN
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stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
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# RM0399 (id 0x450) M7+M4 with SWO Funnel
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# RM0433 (id 0x450) M7 with SWO Funnel
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# RM0455 (id 0x480) M7 without SWO Funnel
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# RM0468 (id 0x483) M7 without SWO Funnel
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# Enable CM7 and CM4 slave ports in SWO trace Funnel
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# Works ok also on devices single core and without SWO funnel
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# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
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# SWTF_CTRL |= ENS0 | ENS1
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stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
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}
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$_CHIPNAME.cpu0 configure -event reset-init {
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter speed 4000
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}
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# get _CHIPNAME from current target
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proc stm32h7x_get_chipname {} {
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set t [target current]
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set sep [string last "." $t]
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if {$sep == -1} {
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return $t
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}
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return [string range $t 0 [expr $sep - 1]]
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}
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if {[set $_CHIPNAME.DUAL_CORE]} {
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$_CHIPNAME.cpu1 configure -event examine-end {
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set _CHIPNAME [stm32h7x_get_chipname]
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global $_CHIPNAME.USE_CTI
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# Stop watchdog counters during halt
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# DBGMCU_APB3FZ2 |= WWDG1
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stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
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# DBGMCU_APB1LFZ2 |= WWDG2
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stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
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# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
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stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
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if {[set $_CHIPNAME.USE_CTI]} {
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stm32h7x_cti_start
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}
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}
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}
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# like mrw, but with target selection
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proc stm32h7x_mrw {used_target reg} {
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set value ""
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$used_target mem2array value 32 $reg 1
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return $value(0)
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}
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# like mmw, but with target selection
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proc stm32h7x_mmw {used_target reg setbits clearbits} {
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set old [stm32h7x_mrw $used_target $reg]
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set new [expr ($old & ~$clearbits) | $setbits]
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$used_target mww $reg $new
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}
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# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
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# this procedure will use the mem_ap on AP2 whenever possible
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proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
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# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
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if {![using_hla]} {
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set _CHIPNAME [stm32h7x_get_chipname]
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set used_target $_CHIPNAME.ap2
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set reg_addr [expr 0xE00E1000 + $reg_offset]
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} {
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set used_target [target current]
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set reg_addr [expr 0x5C001000 + $reg_offset]
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}
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stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
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}
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if {[set $_CHIPNAME.USE_CTI]} {
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# create CTI instances for both cores
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cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
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cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
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$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
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$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
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$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
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$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
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proc stm32h7x_cti_start {} {
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set _CHIPNAME [stm32h7x_get_chipname]
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# Configure Cores' CTIs to halt each other
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# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
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$_CHIPNAME.cti0 write INEN0 0x1
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$_CHIPNAME.cti0 write OUTEN0 0x1
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$_CHIPNAME.cti1 write INEN0 0x1
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$_CHIPNAME.cti1 write OUTEN0 0x1
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# enable CTIs
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$_CHIPNAME.cti0 enable on
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$_CHIPNAME.cti1 enable on
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}
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proc stm32h7x_cti_stop {} {
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set _CHIPNAME [stm32h7x_get_chipname]
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$_CHIPNAME.cti0 enable off
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$_CHIPNAME.cti1 enable off
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}
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proc stm32h7x_cti_prepare_restart_all {} {
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stm32h7x_cti_prepare_restart cti0
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stm32h7x_cti_prepare_restart cti1
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}
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proc stm32h7x_cti_prepare_restart {cti} {
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set _CHIPNAME [stm32h7x_get_chipname]
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# Acknowlodge EDBGRQ at TRIGOUT0
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$_CHIPNAME.$cti write INACK 0x01
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$_CHIPNAME.$cti write INACK 0x00
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}
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}
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