a5354ff5cb
- Bugfixes:
* internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
+ except new Tempest parts where it's 16 MHz (and calibrated!)
+ or some old Sandstorm ones, where 15 MHz was valid
* crystal config:
+ read and use the crystal config, don't assume 6 MHz
+ know when that field is 4 bits vs 5
* an RCC2 register may be overriding the original RCC
+ more clock source options
+ bigger dividers
+ fractional dividers on Tempest (NYET handled)
* there's a 30 KHz osc on newer chips (for deep sleep)
* there's a 32768 Hz osc on newer chips (for hibernation)
- Cosmetic
* say "rev A0" not "vA.0", to match vendor docs
* don't always report master clock as an "estimate":
+ give the error bound if it's approximate, like "±30%"
+ else don't say anything
* fix whitespace and caps in some messages
* these are not AT91SAM chips!!
Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.
That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor. What's less clear is which chips are "old" like that.
Lightly tested, on a DustDevil part.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
100 lines
3.0 KiB
C
100 lines
3.0 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef STELLARIS_FLASH_H
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#define STELLARIS_FLASH_H
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#include "flash.h"
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typedef struct stellaris_flash_bank_s
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{
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/* chip id register */
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uint32_t did0;
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uint32_t did1;
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uint32_t dc0;
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uint32_t dc1;
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char * target_name;
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uint32_t sramsiz;
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uint32_t flshsz;
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/* flash geometry */
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uint32_t num_pages;
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uint32_t pagesize;
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uint32_t pages_in_lockregion;
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/* nv memory bits */
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uint16_t num_lockbits;
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uint32_t lockbits;
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/* main clock status */
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uint32_t rcc;
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uint32_t rcc2;
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uint8_t mck_valid;
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uint8_t xtal_mask;
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uint32_t iosc_freq;
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uint32_t mck_freq;
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const char *iosc_desc;
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const char *mck_desc;
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} stellaris_flash_bank_t;
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/* STELLARIS control registers */
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#define SCB_BASE 0x400FE000
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#define DID0 0x000
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#define DID1 0x004
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#define DC0 0x008
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#define DC1 0x010
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#define DC2 0x014
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#define DC3 0x018
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#define DC4 0x01C
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#define RIS 0x050
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#define RCC 0x060
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#define PLLCFG 0x064
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#define RCC2 0x070
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#define FMPRE 0x130
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#define FMPPE 0x134
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#define USECRL 0x140
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#define FLASH_CONTROL_BASE 0x400FD000
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#define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
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#define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
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#define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
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#define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
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#define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
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#define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
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#define AMISC 1
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#define PMISC 2
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#define AMASK 1
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#define PMASK 2
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/* Flash Controller Command bits */
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#define FMC_WRKEY (0xA442 << 16)
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#define FMC_COMT (1 << 3)
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#define FMC_MERASE (1 << 2)
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#define FMC_ERASE (1 << 1)
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#define FMC_WRITE (1 << 0)
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/* STELLARIS constants */
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#endif /* STELLARIS_H */
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