4ab75a3634
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
32 lines
1.6 KiB
C
32 lines
1.6 KiB
C
/***************************************************************************
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* Copyright (C) 2017 by Square, Inc. *
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* Steven Stallion <stallion@squareup.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H
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#define OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtos/rtos.h>
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extern const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking;
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extern const struct rtos_register_stacking rtos_uCOS_III_eSi_RISC_stacking;
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#endif /* OPENOCD_RTOS_RTOS_UCOS_III_STACKINGS_H */
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