1662c854e2
After SPI flash was written by the assembly language stub, the last SPI command was not terminated by raising CS. This left the SPI device in a hung state that prevented the flash from being read by the M4 SPIFI controller, even after the M4 was fully reset. To access the flash via SPIFI, it was necessary to completely power cycle the board. This fix adds the missing instructions to raise CS and terminate the SPI command after the last byte. This allows the M4 to be resumed or reset cleanly after flashing. The SPIFI memory is now immediately accessable at address 0x1400 0000 after flashing is complete. Change-Id: I4d5e03bded0fa00c430c2991f182dc18611d5f48 Signed-off-by: Anders <anders@openpuma.org> Reviewed-on: http://openocd.zylin.com/2359 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> |
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| .. | ||
| libdcc | ||
| loaders | ||
| remote_bitbang | ||
| rpc_examples | ||
| xsvf_tools | ||
| 99-openocd.rules | ||
| coresight-trace.txt | ||
| cross-build.sh | ||
| gen-stellaris-part-header.pl | ||
| itmdump.c | ||