4ab75a3634
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
37 lines
905 B
INI
37 lines
905 B
INI
#
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# EnSilica eSi-32xx SoC (eSi-RISC Family)
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# http://www.ensilica.com/risc-ip/
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME esi32xx
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x11234001
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu
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# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set
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# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.
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if { [info exists CACHEARCH] } {
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$_TARGETNAME esirisc cache_arch $CACHEARCH
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}
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adapter_khz 2000
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reset_config none
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# The default linker scripts provided by the eSi-RISC toolchain do not
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# specify attributes on memory regions, which results in incorrect
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# application of software breakpoints by GDB.
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gdb_breakpoint_override hard
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