Embedded_Projects
/
CH32V307_FreeRTOS_Hello
Template
generated from Embedded_Projects/CH32V307_Template
1
1
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Initial FreeRTOS support.

This commit is contained in:
imi415 2022-05-01 21:45:10 +08:00
parent ad82a78c45
commit fad64957ce
Signed by: imi415
GPG Key ID: 885EC2B5A8A6F8A7
14 changed files with 736 additions and 520 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.gitmodules vendored Normal file
View File

@ -0,0 +1,3 @@
[submodule "lib/FreeRTOS-Kernel"]
path = lib/FreeRTOS-Kernel
url = https://github.com/imi415/FreeRTOS-Kernel.git

23
BSP/Debug/debug.c
View File

@ -168,26 +168,3 @@ __attribute__((used)) int _write(int fd, char *buf, int size)
return size; return size;
} }
/*********************************************************************
* @fn _sbrk
*
* @brief Change the spatial position of data segment.
*
* @return size: Data length
*/
void *_sbrk(ptrdiff_t incr)
{
extern char _end[];
extern char _heap_end[];
static char *curbrk = _end;
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
return NULL - 1;
curbrk += incr;
return curbrk - incr;
}

120
BSP/Ld/Link.ld
View File

@ -18,59 +18,45 @@ MEMORY
SECTIONS SECTIONS
{ {
.init : .vectors :
{ {
_sinit = .;
. = ALIGN(4); . = ALIGN(4);
KEEP(*(SORT_NONE(.init))) KEEP(*(SORT_NONE(.vectors)))
. = ALIGN(4); . = ALIGN(4);
_einit = .;
} >FLASH } >FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH
.text : .text :
{ {
. = ALIGN(4); . = ALIGN(4);
_stext = .;
*(.text) *(.text)
*(.text.*) *(.text.*)
*(.gnu.linkonce.t.*)
*(.rodata) *(.rodata)
*(.rodata*) *(.rodata*)
*(.glue_7) *(.gnu.linkonce.r.*)
*(.glue_7t)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
} >FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4); . = ALIGN(4);
_etext = .;
} >FLASH } >FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array : .preinit_array :
{ {
PROVIDE_HIDDEN (__preinit_array_start = .); PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array)) KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .); PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH } >FLASH
.init_array : .init_array :
{ {
PROVIDE_HIDDEN (__init_array_start = .); PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .); PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH } >FLASH
.fini_array : .fini_array :
{ {
PROVIDE_HIDDEN (__fini_array_start = .); PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
@ -78,31 +64,16 @@ SECTIONS
PROVIDE_HIDDEN (__fini_array_end = .); PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH } >FLASH
.ctors : .ctors :
{ {
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in.
*/
KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors)) KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
the crtend.o file until after the sorted ctors. KEEP (*(SORT(.ctors.*)))
The .ctor section from the crtend file contains the KEEP (*(.ctors))
end of ctors marker and it must be last
*/
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH } >FLASH
.dtors : .dtors :
{ {
KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors)) KEEP (*crtbegin?.o(.dtors))
@ -111,55 +82,47 @@ SECTIONS
KEEP (*(.dtors)) KEEP (*(.dtors))
} >FLASH } >FLASH
.dalign : _sidata = LOADADDR(.data);
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data : .data :
{ {
*(.gnu.linkonce.r.*) . = ALIGN(4);
_sdata = .;
*(.data .data.*) *(.data .data.*)
*(.gnu.linkonce.d.*) *(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*) *(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*) *(.srodata .srodata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(4); . = ALIGN(4);
PROVIDE( _edata = .); _edata = .;
} >RAM AT>FLASH } >RAM AT>FLASH
. = ALIGN(16);
PROVIDE( __global_pointer$ = . );
.bss : .bss :
{ {
. = ALIGN(4); . = ALIGN(4);
PROVIDE( _sbss = .); _sbss = .;
*(.sbss*)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*) *(.gnu.linkonce.sb.*)
*(.bss*) *(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*) *(.gnu.linkonce.b.*)
*(COMMON*) *(COMMON)
. = ALIGN(4); . = ALIGN(4);
PROVIDE(_ebss = .); _ebss = .;
} >RAM } >RAM
.heap_stack : .heap_stack :
{ {
. = ALIGN(8); . = ALIGN(8);
PROVIDE(_end = .); _end = .;
PROVIDE(end = . ); PROVIDE(end = . );
. = . + __heap_size; . = . + __heap_size;
@ -174,4 +137,5 @@ SECTIONS
/* Place initial SP to the end of SRAM */ /* Place initial SP to the end of SRAM */
__stack_top = ORIGIN(RAM) + LENGTH(RAM); __stack_top = ORIGIN(RAM) + LENGTH(RAM);
PROVIDE(_eusrstack = __stack_top); PROVIDE(_eusrstack = __stack_top);
PROVIDE(__freertos_irq_stack_top = __stack_top);
} }

2
BSP/Peripheral/src/ch32v30x_eth.c
View File

@ -1285,8 +1285,6 @@ FlagStatus ETH_GetSoftwareResetStatus(void)
{ {
bitstatus = RESET; bitstatus = RESET;
} }
printf("ETH->DMABMR is:%08lx\n", ETH->DMABMR);
return bitstatus; return bitstatus;
} }

537
BSP/Startup/startup_ch32v30x_D8C.S
View File

@ -8,384 +8,195 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*******************************************************************************/ *******************************************************************************/
.section .init,"ax",@progbits .section .vectors,"ax",@progbits
.global _start .global _start
.align 1 .align 4
.option push
.option norvc
_start: _start:
j handle_reset j Reset_Handler /* Go! */
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00000013
.word 0x00100073
.section .vector,"ax",@progbits
.align 1
_vector_base:
.option norvc;
.word _start
.word 0
.word NMI_Handler /* NMI */
.word HardFault_Handler /* Hard Fault */
.word 0
.word Ecall_M_Mode_Handler /* Ecall M Mode */
.word 0
.word 0
.word Ecall_U_Mode_Handler /* Ecall U Mode */
.word Break_Point_Handler /* Break Point */
.word 0
.word 0
.word SysTick_Handler /* SysTick */
.word 0
.word SW_Handler /* SW */
.word 0
/* External Interrupts */
.word WWDG_IRQHandler /* Window Watchdog */
.word PVD_IRQHandler /* PVD through EXTI Line detect */
.word TAMPER_IRQHandler /* TAMPER */
.word RTC_IRQHandler /* RTC */
.word FLASH_IRQHandler /* Flash */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line 0 */
.word EXTI1_IRQHandler /* EXTI Line 1 */
.word EXTI2_IRQHandler /* EXTI Line 2 */
.word EXTI3_IRQHandler /* EXTI Line 3 */
.word EXTI4_IRQHandler /* EXTI Line 4 */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.word ADC1_2_IRQHandler /* ADC1_2 */
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.word TIM1_BRK_IRQHandler /* TIM1 Break */
.word TIM1_UP_IRQHandler /* TIM1 Update */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.word TIM8_BRK_IRQHandler /* TIM8 Break */
.word TIM8_UP_IRQHandler /* TIM8 Update */
.word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word RNG_IRQHandler /* RNG */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_IRQHandler /* TIM6 */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
.word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
.word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
.word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
.word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
.word ETH_IRQHandler /* ETH */
.word ETH_WKUP_IRQHandler /* ETH WakeUp */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* OTGFS */
.word USBHSWakeup_IRQHandler /* USBHS Wakeup */
.word USBHS_IRQHandler /* USBHS */
.word DVP_IRQHandler /* DVP */
.word UART6_IRQHandler /* UART6 */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word TIM9_BRK_IRQHandler /* TIM9 Break */
.word TIM9_UP_IRQHandler /* TIM9 Update */
.word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */
.word TIM9_CC_IRQHandler /* TIM9 Capture Compare */
.word TIM10_BRK_IRQHandler /* TIM10 Break */
.word TIM10_UP_IRQHandler /* TIM10 Update */
.word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */
.word TIM10_CC_IRQHandler /* TIM10 Capture Compare */
.word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
.word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
.word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
.word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */
.word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
.word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
.option rvc; /**
* The only mode WCH didn't break is MODE 0, non-vectored exception.
* We place the jump table here, but processed by software.
*
*/
_vectors:
j Exception_Handler /* 0: Exception */
j Default_Handler /* 1: Reserved */
j NMI_Handler /* 2: NMI */
j Default_Handler /* 3: Reserved */
j Default_Handler /* 4: Reserved */
j Default_Handler /* 5: Reserved */
j Default_Handler /* 6: Reserved */
j Default_Handler /* 7: Reserved */
j Default_Handler /* 8: Reserved */
j Default_Handler /* 9: Reserved */
j Default_Handler /* 10: Reserved */
j Default_Handler /* 11: Reserved */
j SysTick_Handler /* 12: SysTick */
j Default_Handler /* 13: Reserved */
j SW_Handler /* 14: Software */
j Default_Handler /* 15: Reserved */
j WWDG_IRQHandler /* 16: Window Watchdog */
j PVD_IRQHandler /* 17: PVD through EXTI Line detect */
j TAMPER_IRQHandler /* 18: TAMPER */
j RTC_IRQHandler /* 19: RTC */
j FLASH_IRQHandler /* 20: Flash */
j RCC_IRQHandler /* 21: RCC */
j EXTI0_IRQHandler /* 22: EXTI Line 0 */
j EXTI1_IRQHandler /* 23: EXTI Line 1 */
j EXTI2_IRQHandler /* 24: EXTI Line 2 */
j EXTI3_IRQHandler /* 25: EXTI Line 3 */
j EXTI4_IRQHandler /* 26: EXTI Line 4 */
j DMA1_Channel1_IRQHandler /* 27: DMA1 Channel 1 */
j DMA1_Channel2_IRQHandler /* 28: DMA1 Channel 2 */
j DMA1_Channel3_IRQHandler /* 29: DMA1 Channel 3 */
j DMA1_Channel4_IRQHandler /* 30: DMA1 Channel 4 */
j DMA1_Channel5_IRQHandler /* 31: DMA1 Channel 5 */
j DMA1_Channel6_IRQHandler /* 32: DMA1 Channel 6 */
j DMA1_Channel7_IRQHandler /* 33: DMA1 Channel 7 */
j ADC1_2_IRQHandler /* 34: ADC1_2 */
j USB_HP_CAN1_TX_IRQHandler /* 35: USB HP and CAN1 TX */
j USB_LP_CAN1_RX0_IRQHandler /* 36: USB LP and CAN1RX0 */
j CAN1_RX1_IRQHandler /* 37: CAN1 RX1 */
j CAN1_SCE_IRQHandler /* 38: CAN1 SCE */
j EXTI9_5_IRQHandler /* 39: EXTI Line 9..5 */
j TIM1_BRK_IRQHandler /* 40: TIM1 Break */
j TIM1_UP_IRQHandler /* 41: TIM1 Update */
j TIM1_TRG_COM_IRQHandler /* 42: TIM1 Trigger and Commutation */
j TIM1_CC_IRQHandler /* 43: TIM1 Capture Compare */
j TIM2_IRQHandler /* 44: TIM2 */
j TIM3_IRQHandler /* 45: TIM3 */
j TIM4_IRQHandler /* 46: TIM4 */
j I2C1_EV_IRQHandler /* 47: I2C1 Event */
j I2C1_ER_IRQHandler /* 48: I2C1 Error */
j I2C2_EV_IRQHandler /* 49: I2C2 Event */
j I2C2_ER_IRQHandler /* 50: I2C2 Error */
j SPI1_IRQHandler /* 51: SPI1 */
j SPI2_IRQHandler /* 52: SPI2 */
j USART1_IRQHandler /* 53: USART1 */
j USART2_IRQHandler /* 54: USART2 */
j USART3_IRQHandler /* 55: USART3 */
j EXTI15_10_IRQHandler /* 56: EXTI Line 15..10 */
j RTCAlarm_IRQHandler /* 57: RTC Alarm through EXTI Line */
j USBWakeUp_IRQHandler /* 58: USB Wakeup from suspend */
j TIM8_BRK_IRQHandler /* 59: TIM8 Break */
j TIM8_UP_IRQHandler /* 60: TIM8 Update */
j TIM8_TRG_COM_IRQHandler /* 61: TIM8 Trigger and Commutation */
j TIM8_CC_IRQHandler /* 62: TIM8 Capture Compare */
j RNG_IRQHandler /* 63: RNG */
j FSMC_IRQHandler /* 64: FSMC */
j SDIO_IRQHandler /* 65: SDIO */
j TIM5_IRQHandler /* 66: TIM5 */
j SPI3_IRQHandler /* 67: SPI3 */
j UART4_IRQHandler /* 68: UART4 */
j UART5_IRQHandler /* 69: UART5 */
j TIM6_IRQHandler /* 70: TIM6 */
j TIM7_IRQHandler /* 71: TIM7 */
j DMA2_Channel1_IRQHandler /* 72: DMA2 Channel 1 */
j DMA2_Channel2_IRQHandler /* 73: DMA2 Channel 2 */
j DMA2_Channel3_IRQHandler /* 74: DMA2 Channel 3 */
j DMA2_Channel4_IRQHandler /* 75: DMA2 Channel 4 */
j DMA2_Channel5_IRQHandler /* 76: DMA2 Channel 5 */
j ETH_IRQHandler /* 77: ETH */
j ETH_WKUP_IRQHandler /* 78: ETH WakeUp */
j CAN2_TX_IRQHandler /* 79: CAN2 TX */
j CAN2_RX0_IRQHandler /* 80: CAN2 RX0 */
j CAN2_RX1_IRQHandler /* 81: CAN2 RX1 */
j CAN2_SCE_IRQHandler /* 82: CAN2 SCE */
j OTG_FS_IRQHandler /* 83: OTGFS */
j USBHSWakeup_IRQHandler /* 84: USBHS Wakeup */
j USBHS_IRQHandler /* 85: USBHS */
j DVP_IRQHandler /* 86: DVP */
j UART6_IRQHandler /* 87: UART6 */
j UART7_IRQHandler /* 88: UART7 */
j UART8_IRQHandler /* 89: UART8 */
j TIM9_BRK_IRQHandler /* 90: TIM9 Break */
j TIM9_UP_IRQHandler /* 91: TIM9 Update */
j TIM9_TRG_COM_IRQHandler /* 92: TIM9 Trigger and Commutation */
j TIM9_CC_IRQHandler /* 93: TIM9 Capture Compare */
j TIM10_BRK_IRQHandler /* 94: TIM10 Break */
j TIM10_UP_IRQHandler /* 95: TIM10 Update */
j TIM10_TRG_COM_IRQHandler /* 96: TIM10 Trigger and Commutation */
j TIM10_CC_IRQHandler /* 97: TIM10 Capture Compare */
j DMA2_Channel6_IRQHandler /* 98: DMA2 Channel 6 */
j DMA2_Channel7_IRQHandler /* 99: DMA2 Channel 7 */
j DMA2_Channel8_IRQHandler /* 100: DMA2 Channel 8 */
j DMA2_Channel9_IRQHandler /* 101: DMA2 Channel 9 */
j DMA2_Channel10_IRQHandler /* 102: DMA2 Channel 10 */
j DMA2_Channel11_IRQHandler /* 103: DMA2 Channel 11 */
.option pop
.section .text.vector_handler, "ax", @progbits Reset_Handler:
.weak NMI_Handler /* NMI */
.weak HardFault_Handler /* Hard Fault */
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
.weak Break_Point_Handler /* Break Point */
.weak SysTick_Handler /* SysTick */
.weak SW_Handler /* SW */
.weak WWDG_IRQHandler /* Window Watchdog */
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
.weak TAMPER_IRQHandler /* TAMPER */
.weak RTC_IRQHandler /* RTC */
.weak FLASH_IRQHandler /* Flash */
.weak RCC_IRQHandler /* RCC */
.weak EXTI0_IRQHandler /* EXTI Line 0 */
.weak EXTI1_IRQHandler /* EXTI Line 1 */
.weak EXTI2_IRQHandler /* EXTI Line 2 */
.weak EXTI3_IRQHandler /* EXTI Line 3 */
.weak EXTI4_IRQHandler /* EXTI Line 4 */
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.weak ADC1_2_IRQHandler /* ADC1_2 */
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
.weak TIM1_UP_IRQHandler /* TIM1 Update */
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.weak TIM2_IRQHandler /* TIM2 */
.weak TIM3_IRQHandler /* TIM3 */
.weak TIM4_IRQHandler /* TIM4 */
.weak I2C1_EV_IRQHandler /* I2C1 Event */
.weak I2C1_ER_IRQHandler /* I2C1 Error */
.weak I2C2_EV_IRQHandler /* I2C2 Event */
.weak I2C2_ER_IRQHandler /* I2C2 Error */
.weak SPI1_IRQHandler /* SPI1 */
.weak SPI2_IRQHandler /* SPI2 */
.weak USART1_IRQHandler /* USART1 */
.weak USART2_IRQHandler /* USART2 */
.weak USART3_IRQHandler /* USART3 */
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.weak TIM8_BRK_IRQHandler /* TIM8 Break */
.weak TIM8_UP_IRQHandler /* TIM8 Update */
.weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
.weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.weak RNG_IRQHandler /* RNG */
.weak FSMC_IRQHandler /* FSMC */
.weak SDIO_IRQHandler /* SDIO */
.weak TIM5_IRQHandler /* TIM5 */
.weak SPI3_IRQHandler /* SPI3 */
.weak UART4_IRQHandler /* UART4 */
.weak UART5_IRQHandler /* UART5 */
.weak TIM6_IRQHandler /* TIM6 */
.weak TIM7_IRQHandler /* TIM7 */
.weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
.weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
.weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
.weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
.weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
.weak ETH_IRQHandler /* ETH */
.weak ETH_WKUP_IRQHandler /* ETH WakeUp */
.weak CAN2_TX_IRQHandler /* CAN2 TX */
.weak CAN2_RX0_IRQHandler /* CAN2 RX0 */
.weak CAN2_RX1_IRQHandler /* CAN2 RX1 */
.weak CAN2_SCE_IRQHandler /* CAN2 SCE */
.weak OTG_FS_IRQHandler /* OTGFS */
.weak USBHSWakeup_IRQHandler /* USBHS Wakeup */
.weak USBHS_IRQHandler /* USBHS */
.weak DVP_IRQHandler /* DVP */
.weak UART6_IRQHandler /* UART6 */
.weak UART7_IRQHandler /* UART7 */
.weak UART8_IRQHandler /* UART8 */
.weak TIM9_BRK_IRQHandler /* TIM9 Break */
.weak TIM9_UP_IRQHandler /* TIM9 Update */
.weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */
.weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */
.weak TIM10_BRK_IRQHandler /* TIM10 Break */
.weak TIM10_UP_IRQHandler /* TIM10 Update */
.weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */
.weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */
.weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
.weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
.weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
.weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */
.weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
.weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
NMI_Handler: 1: j 1b
HardFault_Handler: 1: j 1b
Ecall_M_Mode_Handler: 1: j 1b
Ecall_U_Mode_Handler: 1: j 1b
Break_Point_Handler: 1: j 1b
SysTick_Handler: 1: j 1b
SW_Handler: 1: j 1b
WWDG_IRQHandler: 1: j 1b
PVD_IRQHandler: 1: j 1b
TAMPER_IRQHandler: 1: j 1b
RTC_IRQHandler: 1: j 1b
FLASH_IRQHandler: 1: j 1b
RCC_IRQHandler: 1: j 1b
EXTI0_IRQHandler: 1: j 1b
EXTI1_IRQHandler: 1: j 1b
EXTI2_IRQHandler: 1: j 1b
EXTI3_IRQHandler: 1: j 1b
EXTI4_IRQHandler: 1: j 1b
DMA1_Channel1_IRQHandler: 1: j 1b
DMA1_Channel2_IRQHandler: 1: j 1b
DMA1_Channel3_IRQHandler: 1: j 1b
DMA1_Channel4_IRQHandler: 1: j 1b
DMA1_Channel5_IRQHandler: 1: j 1b
DMA1_Channel6_IRQHandler: 1: j 1b
DMA1_Channel7_IRQHandler: 1: j 1b
ADC1_2_IRQHandler: 1: j 1b
USB_HP_CAN1_TX_IRQHandler: 1: j 1b
USB_LP_CAN1_RX0_IRQHandler: 1: j 1b
CAN1_RX1_IRQHandler: 1: j 1b
CAN1_SCE_IRQHandler: 1: j 1b
EXTI9_5_IRQHandler: 1: j 1b
TIM1_BRK_IRQHandler: 1: j 1b
TIM1_UP_IRQHandler: 1: j 1b
TIM1_TRG_COM_IRQHandler: 1: j 1b
TIM1_CC_IRQHandler: 1: j 1b
TIM2_IRQHandler: 1: j 1b
TIM3_IRQHandler: 1: j 1b
TIM4_IRQHandler: 1: j 1b
I2C1_EV_IRQHandler: 1: j 1b
I2C1_ER_IRQHandler: 1: j 1b
I2C2_EV_IRQHandler: 1: j 1b
I2C2_ER_IRQHandler: 1: j 1b
SPI1_IRQHandler: 1: j 1b
SPI2_IRQHandler: 1: j 1b
USART1_IRQHandler: 1: j 1b
USART2_IRQHandler: 1: j 1b
USART3_IRQHandler: 1: j 1b
EXTI15_10_IRQHandler: 1: j 1b
RTCAlarm_IRQHandler: 1: j 1b
USBWakeUp_IRQHandler: 1: j 1b
TIM8_BRK_IRQHandler: 1: j 1b
TIM8_UP_IRQHandler: 1: j 1b
TIM8_TRG_COM_IRQHandler: 1: j 1b
TIM8_CC_IRQHandler: 1: j 1b
RNG_IRQHandler: 1: j 1b
FSMC_IRQHandler: 1: j 1b
SDIO_IRQHandler: 1: j 1b
TIM5_IRQHandler: 1: j 1b
SPI3_IRQHandler: 1: j 1b
UART4_IRQHandler: 1: j 1b
UART5_IRQHandler: 1: j 1b
TIM6_IRQHandler: 1: j 1b
TIM7_IRQHandler: 1: j 1b
DMA2_Channel1_IRQHandler: 1: j 1b
DMA2_Channel2_IRQHandler: 1: j 1b
DMA2_Channel3_IRQHandler: 1: j 1b
DMA2_Channel4_IRQHandler: 1: j 1b
DMA2_Channel5_IRQHandler: 1: j 1b
ETH_IRQHandler: 1: j 1b
ETH_WKUP_IRQHandler: 1: j 1b
CAN2_TX_IRQHandler: 1: j 1b
CAN2_RX0_IRQHandler: 1: j 1b
CAN2_RX1_IRQHandler: 1: j 1b
CAN2_SCE_IRQHandler: 1: j 1b
OTG_FS_IRQHandler: 1: j 1b
USBHSWakeup_IRQHandler: 1: j 1b
USBHS_IRQHandler: 1: j 1b
DVP_IRQHandler: 1: j 1b
UART6_IRQHandler: 1: j 1b
UART7_IRQHandler: 1: j 1b
UART8_IRQHandler: 1: j 1b
TIM9_BRK_IRQHandler: 1: j 1b
TIM9_UP_IRQHandler: 1: j 1b
TIM9_TRG_COM_IRQHandler: 1: j 1b
TIM9_CC_IRQHandler: 1: j 1b
TIM10_BRK_IRQHandler: 1: j 1b
TIM10_UP_IRQHandler: 1: j 1b
TIM10_TRG_COM_IRQHandler: 1: j 1b
TIM10_CC_IRQHandler: 1: j 1b
DMA2_Channel6_IRQHandler: 1: j 1b
DMA2_Channel7_IRQHandler: 1: j 1b
DMA2_Channel8_IRQHandler: 1: j 1b
DMA2_Channel9_IRQHandler: 1: j 1b
DMA2_Channel10_IRQHandler: 1: j 1b
DMA2_Channel11_IRQHandler: 1: j 1b
.section .text.handle_reset,"ax",@progbits
.weak handle_reset
.align 1
handle_reset:
.option push .option push
.option norelax .option norelax
la gp, __global_pointer$ la gp, __global_pointer$
.option pop .option pop
1:
la sp, _eusrstack la sp, _eusrstack
2: copy_data:
/* Load data section from flash to RAM */ /* Load data section from flash to RAM */
la a0, _data_lma la a0, _sidata
la a1, _data_vma la a1, _sdata
la a2, _edata la a2, _edata
bgeu a1, a2, 2f bgeu a1, a2, clear_bss
1:
lw t0, (a0) loop_copy_data:
sw t0, (a1) lw t0, (a0)
addi a0, a0, 4 sw t0, (a1)
addi a1, a1, 4 addi a0, a0, 4
bltu a1, a2, 1b addi a1, a1, 4
2: bltu a1, a2, loop_copy_data
/* Clear bss section */
la a0, _sbss clear_bss:
la a1, _ebss /* Clear bss section */
bgeu a0, a1, 2f la a0, _sbss
1: la a1, _ebss
sw zero, (a0) bgeu a0, a1, setup_interrupts
addi a0, a0, 4 loop_clear_bss:
bltu a0, a1, 1b sw zero, (a0)
2: addi a0, a0, 4
bltu a0, a1, loop_clear_bss
setup_interrupts:
li t0, 0x1f li t0, 0x1f
csrw 0xbc0, t0 csrw 0xbc0, t0
/* Enable nested and hardware stack */ /* Enable nested and hardware stack */
/* li t0, 0x1f */ /* For MRS proprietary GCC compilers */ /* li t0, 0x1f */ /* For MRS proprietary GCC compilers */
/* Enable nested interrupt, disable hardware stack */ /* Enable nested interrupt, disable hardware stack */
li t0, 0x1e /* Refer to RISC-V4 PFIC manual */ li t0, 0x1e /* Refer to RISC-V4 PFIC manual */
csrw 0x804, t0 csrw 0x804, t0
/* Enable floating point and interrupt */ /* FS: Initial, MPP: M mode, MPIE: EN, MIE: EN */
li t0, 0x6088 li t0, 0x3888
csrs mstatus, t0 csrs mstatus, t0
la t0, _vector_base la t0, _vectors
ori t0, t0, 3 ori t0, t0, 0 /* Non-vectored exception handling */
csrw mtvec, t0 csrw mtvec, t0 /* Use standard RISC-V exception model. */
jal SystemInit jal SystemInit
la t0, main jal main
csrw mepc, t0
mret
dead_loop:
j dead_loop
Exception_Handler:
csrr t0, mcause
ble t0, x0, Interrupt_Handler /* Check interrupt */
li t1, 11 /* Find an M mode ecall (11) */
beq t1, t0, Ecall_M_Handler
li t1, 8
beq t1, t0, Ecall_U_Handler
j Fault_Handler
Interrupt_Handler: /* Home made vector table */
slli t0, t0, 2
la t1, _vectors
add t1, t1, t0
jr t1

6
CMakeLists.txt
View File

@ -47,6 +47,7 @@ set(TARGET_C_SOURCES
"BSP/Peripheral/src/ch32v30x_wwdg.c" "BSP/Peripheral/src/ch32v30x_wwdg.c"
"src/board.c" "src/board.c"
"src/ch32v30x_it.c" "src/ch32v30x_it.c"
"src/freertos_helper.c"
"src/main.c" "src/main.c"
"src/syscalls.c" "src/syscalls.c"
"src/system_ch32v30x.c" "src/system_ch32v30x.c"
@ -71,6 +72,7 @@ set(TARGET_C_INCLUDES
# Shared libraries linked with application # Shared libraries linked with application
set(TARGET_LIBS set(TARGET_LIBS
"freertos_kernel"
) )
# Shared library and linker script search paths # Shared library and linker script search paths
@ -99,6 +101,10 @@ set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} ${CMAKE_C_FLAGS} -x assembler-wit
set(CMAKE_EXE_LINKER_FLAGS "-specs=nano.specs -specs=nosys.specs -Wl,--gc-sections -nostartfiles -nostdlib ${TARGET_LDFLAGS_EXTRA}") set(CMAKE_EXE_LINKER_FLAGS "-specs=nano.specs -specs=nosys.specs -Wl,--gc-sections -nostartfiles -nostdlib ${TARGET_LDFLAGS_EXTRA}")
# Include sub directories here # Include sub directories here
set(FREERTOS_PORT "GCC_RISC_V_WCH_RISC_V4A_FPU" CACHE STRING "")
set(FREERTOS_CONFIG_FILE_DIRECTORY "${CMAKE_SOURCE_DIR}/include" CACHE STRING "")
set(FREERTOS_HEAP "4" CACHE STRING "")
add_subdirectory(lib/FreeRTOS-Kernel)
# Shared sources, includes and definitions # Shared sources, includes and definitions
add_compile_definitions(${TARGET_C_DEFINES}) add_compile_definitions(${TARGET_C_DEFINES})

89
include/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,89 @@
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "system_ch32v30x.h"
/* RISC-V related configuration */
#define configMTIME_BASE_ADDRESS 0
#define configMTIMECMP_BASE_ADDRESS 0
/* General configuration */
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configUSE_TICKLESS_IDLE 0
#define configCPU_CLOCK_HZ 144000000 /* This is literally not used, keep it to make port.c happy. */
#define configTICK_RATE_HZ 1000
#define configMAX_PRIORITIES 8
#define configMINIMAL_STACK_SIZE 128
#define configMAX_TASK_NAME_LEN 16
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_TASK_NOTIFICATIONS 1
#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3
#define configUSE_MUTEXES 0
#define configUSE_RECURSIVE_MUTEXES 0
#define configUSE_COUNTING_SEMAPHORES 0
#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
#define configQUEUE_REGISTRY_SIZE 10
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 0
#define configUSE_NEWLIB_REENTRANT 1
#define configENABLE_BACKWARD_COMPATIBILITY 0
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
#define configSTACK_DEPTH_TYPE uint16_t
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
/* Memory allocation related definitions. */
#define configSUPPORT_STATIC_ALLOCATION 0
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configTOTAL_HEAP_SIZE 10240
#define configAPPLICATION_ALLOCATED_HEAP 0
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
/* Hook function related definitions. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCHECK_FOR_STACK_OVERFLOW 0
#define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
/* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_TRACE_FACILITY 0
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Co-routine related definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 1
/* Software timer related definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY 3
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Define to trap errors during development. */
#define configASSERT( x ) if( ( x ) == 0 ) for(;;) { }
/* Optional functions - most linkers will remove unused functions anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_xResumeFromISR 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 0
#define INCLUDE_xEventGroupSetBitFromISR 1
#define INCLUDE_xTimerPendFunctionCall 0
#define INCLUDE_xTaskAbortDelay 0
#define INCLUDE_xTaskGetHandle 0
#define INCLUDE_xTaskResumeFromISR 1
/* A header file that defines trace macro can be included here. */
#endif /* FREERTOS_CONFIG_H */

1
include/ch32v30x_conf.h
View File

@ -31,7 +31,6 @@
#include "ch32v30x_tim.h" #include "ch32v30x_tim.h"
#include "ch32v30x_usart.h" #include "ch32v30x_usart.h"
#include "ch32v30x_wwdg.h" #include "ch32v30x_wwdg.h"
#include "ch32v30x_it.h"
#include "ch32v30x_misc.h" #include "ch32v30x_misc.h"

20
include/ch32v30x_it.h
View File

@ -1,18 +1,4 @@
/********************************** (C) COPYRIGHT ******************************* #ifndef CH32V30X_IT_H
* File Name : ch32v30x_it.h #define CH32V30X_IT_H
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains the headers of the interrupt handlers.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V30x_IT_H
#define __CH32V30x_IT_H
#include "debug.h"
#endif /* __CH32V30x_IT_H */
#endif

1
lib/FreeRTOS-Kernel Submodule

@ -0,0 +1 @@
Subproject commit 89cf6815ee9287d2b93dac797a12816f237ec2e8

369
src/ch32v30x_it.c
View File

@ -1,40 +1,349 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v30x_it.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : Main Interrupt Service Routines.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ch32v30x_it.h" #include "ch32v30x_it.h"
void NMI_Handler(void) __attribute__((interrupt())); #define __IRQ __attribute__((interrupt()))
void HardFault_Handler(void) __attribute__((interrupt())); #define __IRQ_WEAK __attribute__((interrupt(), weak))
#define __IRQ_NAKED __attribute__((naked))
/*********************************************************************
* @fn NMI_Handler /**
* * FreeRTOS supports both non-vectored and vectored exception model.
* @brief This function handles NMI exception. * For non-vectored exception, use `freertos_risc_v_trap_handler`,
* * this function will determine the type of current exception.
* @return none * For vectored exception, use `freertos_risc_v_exception_handler`,
* and use `freertos_risc_v_mtimer_interrupt_handler` for timer interrupt.
*
*/ */
void NMI_Handler(void)
{ /**
* @brief Default Handler for exceptions and interrupts
*
*/
__IRQ_WEAK void Default_Handler(void) {
for(;;) {
/* Where are you from? */
}
} }
/********************************************************************* /**
* @fn HardFault_Handler * @brief Fault handler
* *
* @brief This function handles Hard Fault exception.
*
* @return none
*/ */
void HardFault_Handler(void) __IRQ_WEAK void Fault_Handler(void) {
{ for(;;) {
while (1) /* Emmmmmmmmm? */
{ }
}
} }
/**
* @brief U mode ecall handler
*
*/
__IRQ_WEAK void Ecall_U_Handler(void) {
for(;;) {
/* Who called me? */
}
}
/**
* @brief M mode ecall handler
*
*/
__IRQ_NAKED void Ecall_M_Handler(void) {
/* Use naked function to generate a short call, without saving stack. */
asm("j freertos_risc_v_exception_handler");
}
/**
* @brief Non-maskable interrupt handler
*
*/
__IRQ_WEAK void NMI_Handler(void) {
/* NMI handler */
}
/**
* @brief SysTick interrupt handler
*
* @return __IRQ_NAKED
*/
__IRQ_NAKED void SysTick_Handler(void) {
/* Use naked function to generate a short call, without causing stack unbalance. */
asm volatile(
"li t0, 0xE000F004\n" /* Clear SysTick->SR */
"sw zero, 0(t0)\n"
"j freertos_risc_v_mtimer_interrupt_handler"
);
}
/**
* @brief Software interrupt handler
*
*/
__IRQ_WEAK void SW_Handler(void) {
/* Software handler */
}
__IRQ_WEAK void WWDG_IRQHandler(void) {
/**/
}
__IRQ_WEAK void PVD_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TAMPER_IRQHandler(void) {
/**/
}
__IRQ_WEAK void RTC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void FLASH_IRQHandler(void) {
/**/
}
__IRQ_WEAK void RCC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI0_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI3_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI4_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel3_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel4_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel5_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel6_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA1_Channel7_IRQHandler(void) {
/**/
}
__IRQ_WEAK void ADC1_2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USB_HP_CAN1_TX_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USB_LP_CAN1_RX0_IRQHandler(void) {
/**/
}
__IRQ_WEAK void CAN1_RX1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void CAN1_SCE_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI9_5_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM1_BRK_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM1_UP_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM1_TRG_COM_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM1_CC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM3_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM4_IRQHandler(void) {
/**/
}
__IRQ_WEAK void I2C1_EV_IRQHandler(void) {
/**/
}
__IRQ_WEAK void I2C1_ER_IRQHandler(void) {
/**/
}
__IRQ_WEAK void I2C2_EV_IRQHandler(void) {
/**/
}
__IRQ_WEAK void I2C2_ER_IRQHandler(void) {
/**/
}
__IRQ_WEAK void SPI1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void SPI2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USART1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USART2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USART3_IRQHandler(void) {
/**/
}
__IRQ_WEAK void EXTI15_10_IRQHandler(void) {
/**/
}
__IRQ_WEAK void RTCAlarm_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USBWakeUp_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM8_BRK_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM8_UP_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM8_TRG_COM_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM8_CC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void RNG_IRQHandler(void) {
/**/
}
__IRQ_WEAK void FSMC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void SDIO_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM5_IRQHandler(void) {
/**/
}
__IRQ_WEAK void SPI3_IRQHandler(void) {
/**/
}
__IRQ_WEAK void UART4_IRQHandler(void) {
/**/
}
__IRQ_WEAK void UART5_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM6_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM7_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel2_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel3_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel4_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel5_IRQHandler(void) {
/**/
}
__IRQ_WEAK void ETH_IRQHandler(void) {
/**/
}
__IRQ_WEAK void ETH_WKUP_IRQHandler(void) {
/**/
}
__IRQ_WEAK void CAN2_TX_IRQHandler(void) {
/**/
}
__IRQ_WEAK void CAN2_RX0_IRQHandler(void) {
/**/
}
__IRQ_WEAK void CAN2_RX1_IRQHandler(void) {
/**/
}
__IRQ_WEAK void CAN2_SCE_IRQHandler(void) {
/**/
}
__IRQ_WEAK void OTG_FS_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USBHSWakeup_IRQHandler(void) {
/**/
}
__IRQ_WEAK void USBHS_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DVP_IRQHandler(void) {
/**/
}
__IRQ_WEAK void UART6_IRQHandler(void) {
/**/
}
__IRQ_WEAK void UART7_IRQHandler(void) {
/**/
}
__IRQ_WEAK void UART8_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM9_BRK_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM9_UP_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM9_TRG_COM_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM9_CC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM10_BRK_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM10_UP_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM10_TRG_COM_IRQHandler(void) {
/**/
}
__IRQ_WEAK void TIM10_CC_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel6_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel7_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel8_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel9_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel10_IRQHandler(void) {
/**/
}
__IRQ_WEAK void DMA2_Channel11_IRQHandler(void) {
/**/
}

37
src/freertos_helper.c Normal file
View File

@ -0,0 +1,37 @@
#include "FreeRTOS.h"
#include "task.h"
#include "ch32v30x.h"
#include "system_ch32v30x.h"
void SysTick_Handler(void) __attribute__((interrupt()));
void Ecall_M_Mode_Handler(void) __attribute__((interrupt()));
extern void freertos_risc_v_mtimer_interrupt_handler(void);
/**
* Notes on FreeRTOS:
* Current FreeRTOS supports both vectored and Non-Vectored exception model,
* handled in portASM.h. WCH, however, has an unique exception model which
* vectors both exceptions and interrupts to a fixed vector table, making trap handler
* useless while handling ECALL exceptions, since they have their own entry point in IVT.
*/
/**
* @brief Initialize SysTick interrupt.
*
*/
void vPortSetupTimerInterrupt(void) {
/* Configure SysTick and interrupts. */
SysTick->SR = 0UL;
SysTick->CTLR = 0UL;
SysTick->CNT = 0UL;
NVIC_EnableIRQ(SysTicK_IRQn);
SysTick->CMP = (uint64_t)((SystemCoreClock / configTICK_RATE_HZ) - 1);
SysTick->CTLR = 0x1E; /* COUNTDOWN | AUTO RELOAD | HCLK | INT */
SysTick->CTLR |= 0x20; /* INIT */
SysTick->CTLR |= 0x01; /* EN */
}

24
src/main.c
View File

@ -6,23 +6,35 @@
#include "board.h" #include "board.h"
#include "FreeRTOS.h"
#include "task.h"
void vTaskHello(void *pvParameters);
int main(void) { int main(void) {
/* Initialize board components. */ /* Initialize board components. */
BOARD_SystemClock_Config(); BOARD_SystemClock_Config();
BOARD_IOMUX_Init(); BOARD_IOMUX_Init();
BOARD_Peripheral_Init(); BOARD_Peripheral_Init();
/* Initialize UART for libc function calls. */ /* Initialize UART for libc function calls. */
USART_Printf_Init(115200); USART_Printf_Init(115200);
Delay_Init(); /* Silly function, will be replaced next time. */
printf("Hello world?\r\n"); printf("Hello world, FreeRTOS?\r\n");
uint32_t i = 0; xTaskCreate(vTaskHello, "HELLO", 256, NULL, 4, NULL);
vTaskStartScheduler();
for(;;) { for(;;) {
Delay_Ms(500); /* Never reaches here. */
printf("Dead loop @%lu\r\n", i++);
} }
} }
void vTaskHello(void *pvParameters) {
for(;;) {
printf("Hello world? @%lu\r\n", xTaskGetTickCount());
vTaskDelay(pdMS_TO_TICKS(500));
}
}

24
src/syscalls.c
View File

@ -1,5 +1,29 @@
#include <sys/stat.h> #include <sys/stat.h>
#include "FreeRTOS.h"
#include "task.h"
void *_sbrk(ptrdiff_t incr) {
extern char _end[];
extern char _heap_end[];
static char *curbrk = _end;
void *ret;
taskENTER_CRITICAL();
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
return NULL - 1;
curbrk += incr;
ret = curbrk - incr;
taskEXIT_CRITICAL();
return ret;
}
int _fstat(int file, struct stat *st) { int _fstat(int file, struct stat *st) {
st->st_mode = S_IFCHR; st->st_mode = S_IFCHR;