Initial interrupt routine support.

include/stx7105.h

@@ -80,6 +80,29 @@ typedef struct {
     uint32_t      TCPR2;      /* Offset: 0x2C */
 } TMU_TypeDef;
 
+typedef struct {
+    __IO uint32_t PTEH;        /* Offset: 0x00, Page table entry high register */
+    __IO uint32_t PTEL;        /* Offset: 0x04, Page table entry low register */
+    __IO uint32_t TTB;         /* Offset: 0x08, Translation table base register */
+    __IO uint32_t TEA;         /* Offset: 0x0C, TLB exception address register */
+    __IO uint32_t MMUCR;       /* Offset: 0x10, MMU control register */
+    __IO uint8_t  BASRA;       /* Offset: 0x14, Break ASID register A*/
+    uint8_t       UNUSED0[3];  /* Offset: 0x15 */
+    __IO uint8_t  BASRB;       /* Offset: 0x18, Break ASID register B*/
+    uint8_t       UNUSED1[3];  /* Offset: 0x19 */
+    __IO uint32_t CCR;         /* Offset: 0x1C, Cache control register */
+    __IO uint32_t TRA;         /* Offset: 0x20, TRAPA exception register */
+    __IO uint32_t EXPEVT;      /* Offset: 0x24, Exception event register */
+    __IO uint32_t INTEVT;      /* Offset: 0x28, Interrupt event register */
+    uint32_t      UNUSED2[3];  /* Offset: 0x2C */
+    __IO uint32_t QACR0;       /* Offset: 0x38, Queue address control register 0 */
+    __IO uint32_t QACR1;       /* Offset: 0x3C, Queue address control register 1 */
+    uint32_t      UNUSED3[12]; /* Offset: 0x40 */
+    __IO uint32_t PASCR;       /* Offset: 0x70, Physical address space control register */
+    __IO uint32_t RAMCR;       /* Offset: 0x74, On-chip memory control register */
+    __IO uint32_t IRMCR;       /* Offset: 0x78, Instruction refetch inhibit control register */
+} CSR_TypeDef;
+
 #define XX sizeof(TMU_TypeDef)
 
 #define PIO0_BASE (0xFD020000U)
@@ -88,6 +111,7 @@ typedef struct {
 #define ASC1_BASE (0xFD031000U)
 #define ASC2_BASE (0xFD032000U)
 #define ASC3_BASE (0xFD033000U)
+#define CSR_BASE  (0xFF000000U)
 #define TMU_BASE  (0xFFD80000U)
 
 #define PIO0 ((PIO_TypeDef *)PIO0_BASE)
@@ -96,6 +120,7 @@ typedef struct {
 #define ASC1 ((ASC_TypeDef *)ASC1_BASE)
 #define ASC2 ((ASC_TypeDef *)ASC2_BASE)
 #define ASC3 ((ASC_TypeDef *)ASC3_BASE)
+#define CSR  ((CSR_TypeDef *)CSR_BASE)
 #define TMU  ((TMU_TypeDef *)TMU_BASE)
 
 #endif

sh4helpers.gdb

@@ -0,0 +1,13 @@
+# The magic number below is the point where bootloader has completed initializing the LMI.
+
+define box_setup
+    sh4tp STMCLT2333_A:iptv7105:st40,no_pokes=1
+    hbreak *0xA000008C
+    continue
+    delete breakpoint 1
+        load
+
+        hbreak _main
+end
+
+box_setup

src/stx7105_exc.c

@@ -1,12 +1,17 @@
 #include "stx7105.h"
 
-#define EXPEVT_BASE 0xFF000024
+#define __WEAK     __attribute__((weak))
-#define TRA_BASE    0xFF000020
+#define __IRQ      __attribute__((interrupt_handler))
+#define __WEAK_IRQ __attribute__((weak, interrupt_handler))
 
 typedef enum {
     EXP_TYPE_TRAP = 0x160,
 } expevt_type_t;
 
+typedef enum {
+    INT_TYPE_TMU = 0x000,
+} intevt_type_t;
+
 typedef enum {
     TRA_TYPE_SYSCALL = 34,
 } tra_type_t;
@@ -22,7 +27,7 @@ static int uart_write(char *ptr, int len) {
     return len;
 }
 
-static int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
+__WEAK int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
     if (p1 == 4) {
         return uart_write((char *)p3, (int)p4);
     }
@@ -30,8 +35,8 @@ static int syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
     return 0;
 }
 
-static int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
+__WEAK int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
-    tra_type_t tra = *(uint32_t *)TRA_BASE;
+    tra_type_t tra = CSR->TRA;
 
     switch (tra) {
         case TRA_TYPE_SYSCALL:
@@ -44,11 +49,8 @@ static int trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
     return 0;
 }
 
-__attribute__((interrupt_handler)) int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
+__WEAK_IRQ int general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
-    expevt_type_t expevt = *(uint32_t *)EXPEVT_BASE;
+    expevt_type_t expevt = CSR->EXPEVT;
-
-    PIO0->SET_POUT = (1 << 5);
-
     switch (expevt) {
         case EXP_TYPE_TRAP:
             trap_handler(p1, p2, p3, p4);
@@ -57,5 +59,9 @@ __attribute__((interrupt_handler)) int general_exc_handler(uint32_t p1, uint32_t
             break;
     }
 
+    return 0;
+}
+
+__WEAK_IRQ int general_int_handler(void) {
     return 0;
 }

startup_stx7105.S

@@ -1,7 +1,8 @@
 /*
- * This section is read by bootloader, then the application will be copied.
+ * This section is read by bootloader,
- * DO NOT REMOVE.
+ * then the application will be copied according to the contents.
- * See SPL README for details.
+ * !!DO NOT REMOVE!!
+ * See SPL project README for details.
  */
 
     .section .text.vtors, "ax"
@@ -9,12 +10,10 @@ _vtors:
     .long _eidata
     .long _start
 
-/* Startup code, we can't use non-PIC code nor RAM before the LMI is initialized:
+/*
- * The CPU starts with physical address 0x0, however the linker is linked to virtual
+ * Startup code (CRT0)
- * addresses and LMI.
- * Non-PIC code means any indirect addressing other than relative to PC.
  */
-    .section .text.init
+    .section .text.init, "ax"
     .global _start
 
 _start:
@@ -49,6 +48,15 @@ _setup_fpu:
     mov #0, r4
     lds r3, fpscr
 
+_setup_irq:
+    mov.l _exc_base_k, r0
+    ldc r0, vbr
+
+    stc sr, r0 /* Store SR into R0 */
+    mov.l _exc_imask_k, r1
+    and r1, r0
+    ldc r0, sr
+
     .align 2
 _main_entry:
     mov.l _main_k, r0
@@ -84,17 +92,34 @@ _exit_k:
     .long _exit
 _exc_base_k:
     .long _exc_base
+_exc_imask_k:
+    .long 0xFFFFFF0F /* Clear IMASK (SR[7:4]) to 0, enable all exception levels */
 
+/*
+ * Exception handlers
+ * These handlers are placed at VBR related addresses
+ */
 
     .section .text.exc, "ax"
     .align 4
 _exc_base:
     .org 0x100, 0x00
 _exc_grnl_vector:
-    mov.l _exc_grnl_entry, r0
+    mov.l _exc_grnl_entry_k, r0
     jmp @r0
     nop
 
     .align 4
-_exc_grnl_entry:
+_exc_grnl_entry_k:
-    .long _general_exc_handler
+    .long _general_exc_handler
+
+_int_base:
+    .org 0x600, 0x00
+_int_grnl_vector:
+    mov.l _int_grnl_entry_k, r0
+    jmp @r0
+    nop
+
+    .align 4
+_int_grnl_entry_k:
+    .long _general_int_handler