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12 Commits
8f749c1f02 ... master

Author SHA1 Message Date
imi415
b04dfa766a
Added LwIP sources.
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2021-03-10 00:52:13 +08:00
imi415
80e83fb1db
Working SDCard and FATFS
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continuous-integration/drone/push Build is passing
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2021-03-08 23:15:17 +08:00
imi415
4cfa9bc892
Added SDMMC and LwIP code.
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2021-03-08 02:01:49 +08:00
imi415
707299b7c8
Refactored build system.
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2021-03-07 00:48:31 +08:00
imi415
3d353d5adc
Added FatFS.
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2021-02-10 01:49:45 +08:00
imi415
205ef215dd
Fixed GPIO issue.
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2021-02-09 01:13:48 +08:00
imi415
2239e5e6dc
Added eLCDIF drivers, modified liner scripts.
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2021-02-08 23:09:12 +08:00
imi415
0482ec6dd2
Added SEMC drivers, refined scripts. 2021-02-08 22:37:11 +08:00
imi415
f48615ba58
CI: set environmental variables.
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2021-02-04 02:27:31 +08:00
imi415
0b0255ecf6
Always pull image.
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2021-02-04 02:25:23 +08:00
imi415
e5ee49ecb7
Fixed script.
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2021-02-04 02:24:30 +08:00
imi415
5dda159afd
Added README.md
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2021-02-04 02:15:08 +08:00
716 changed files with 260211 additions and 1472 deletions
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149
.clang-format Normal file
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@ -0,0 +1,149 @@
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Language: Cpp
# BasedOnStyle: LLVM
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveMacros: false
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AlignConsecutiveDeclarations: false
AlignEscapedNewlines: Right
AlignOperands: Align
AlignTrailingComments: true
AllowAllArgumentsOnNextLine: true
AllowAllConstructorInitializersOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortEnumsOnASingleLine: true
AllowShortBlocksOnASingleLine: Never
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortLambdasOnASingleLine: All
AllowShortIfStatementsOnASingleLine: true
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: Never
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AfterObjCDeclaration: false
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AfterUnion: false
AfterExternBlock: false
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BeforeElse: false
BeforeLambdaBody: false
BeforeWhile: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Attach
BreakBeforeInheritanceComma: false
BreakInheritanceList: BeforeColon
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeColon
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DeriveLineEnding: true
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: true
ForEachMacros:
- foreach
- Q_FOREACH
- BOOST_FOREACH
IncludeBlocks: Preserve
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SortPriority: 0
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IncludeIsMainRegex: '(Test)?$'
IncludeIsMainSourceRegex: ''
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IndentCaseBlocks: false
IndentGotoLabels: true
IndentPPDirectives: None
IndentExternBlock: AfterExternBlock
IndentWidth: 4
IndentWrappedFunctionNames: false
InsertTrailingCommas: None
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...

8
.drone.yml
View File

@ -5,8 +5,14 @@ name: default
steps:
- name: build
image: registry.aws.minori.work/imi415/arm-none-toolchain:latest
pull: always
commands:
- bash build_all.sh
- mkdir build
- cd build
- cmake -DCMAKE_TOOLCHAIN_FILE=arm-none-eabi.cmake ..
- make
environment:
ARMGCC_DIR: /usr/local
image_pull_secrets:
- pull-secret

10
CMSIS/CMSIS_Include_common_MIMXRT1052.cmake
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@ -1,10 +0,0 @@
if(NOT CMSIS_INCLUDE_COMMON_MIMXRT1052_INCLUDED)
set(CMSIS_INCLUDE_COMMON_MIMXRT1052_INCLUDED true CACHE BOOL "CMSIS_Include_common component is included.")
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
endif()

14
CMSIS/CMSIS_Include_core_cm7_MIMXRT1052.cmake
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@ -1,14 +0,0 @@
if(NOT CMSIS_INCLUDE_CORE_CM7_MIMXRT1052_INCLUDED)
set(CMSIS_INCLUDE_CORE_CM7_MIMXRT1052_INCLUDED true CACHE BOOL "CMSIS_Include_core_cm7 component is included.")
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(CMSIS_Include_common_MIMXRT1052)
include(CMSIS_Include_dsp_MIMXRT1052)
endif()

10
CMSIS/CMSIS_Include_dsp_MIMXRT1052.cmake
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@ -1,10 +0,0 @@
if(NOT CMSIS_INCLUDE_DSP_MIMXRT1052_INCLUDED)
set(CMSIS_INCLUDE_DSP_MIMXRT1052_INCLUDED true CACHE BOOL "CMSIS_Include_dsp component is included.")
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
endif()

351
CMakeLists.txt
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@ -1,123 +1,296 @@
# CROSS COMPILER SETTING
SET(CMAKE_SYSTEM_NAME Generic)
CMAKE_MINIMUM_REQUIRED (VERSION 3.1.1)
# THE VERSION NUMBER
SET (Tutorial_VERSION_MAJOR 1)
SET (Tutorial_VERSION_MINOR 0)
# ENABLE ASM
ENABLE_LANGUAGE(ASM)
SET(CMAKE_STATIC_LIBRARY_PREFIX)
SET(CMAKE_STATIC_LIBRARY_SUFFIX)
SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
# CURRENT DIRECTORY
SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
cmake_minimum_required(VERSION 3.10)
project(rt1050_freertos_hello)
set(MCUX_SDK_PROJECT_NAME rt1050_rt1050_freertos_hello.elf)
enable_language(CXX)
enable_language(ASM)
include(${ProjDirPath}/.//flags.cmake)
# Device specific settings, goes to CFLAGS and LDFLAGS
set(CFLAGS_HARDWARE "-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb")
include(${ProjDirPath}/.//config.cmake)
# Extra CFlags
set(CFLAGS_EXTRA "-Og")
set(LDFLAGS_EXTRA "-Wl,--print-memory-usage")
add_executable(${MCUX_SDK_PROJECT_NAME}
"${ProjDirPath}/board/board.c"
"${ProjDirPath}/board/board.h"
"${ProjDirPath}/board/clock_config.c"
"${ProjDirPath}/board/clock_config.h"
"${ProjDirPath}/board/dcd.c"
"${ProjDirPath}/board/dcd.h"
"${ProjDirPath}/board/pin_mux.c"
"${ProjDirPath}/board/pin_mux.h"
"${ProjDirPath}/board/peripherals.c"
"${ProjDirPath}/board/peripherals.h"
"${ProjDirPath}/source/FreeRTOSConfig.h"
"${ProjDirPath}/source/freertos_hello.c"
# Different linker scripts
set(LDSCRIPT_RAM "${CMAKE_SOURCE_DIR}/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld")
set(LDSCRIPT_FLEXSPI "${CMAKE_SOURCE_DIR}/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld")
set(LDSCRIPT_SDRAM "${CMAKE_SOURCE_DIR}/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld")
# Copy them from Makefile
set(C_SOURCES
"drivers/fsl_common.c"
"drivers/fsl_elcdif.c"
"drivers/fsl_clock.c"
"drivers/fsl_enet.c"
"drivers/fsl_gpio.c"
"drivers/fsl_semc.c"
"drivers/fsl_lpuart.c"
"drivers/fsl_usdhc.c"
"drivers/fsl_cache.c"
"freertos/freertos_kernel/tasks.c"
"freertos/freertos_kernel/event_groups.c"
"freertos/freertos_kernel/croutine.c"
"freertos/freertos_kernel/list.c"
"freertos/freertos_kernel/timers.c"
"freertos/freertos_kernel/portable/GCC/ARM_CM4F/port.c"
"freertos/freertos_kernel/portable/MemMang/heap_4.c"
"freertos/freertos_kernel/stream_buffer.c"
"freertos/freertos_kernel/queue.c"
"device/system_MIMXRT1052.c"
"xip/evkbimxrt1050_flexspi_nor_config.c"
"xip/fsl_flexspi_nor_boot.c"
"component/lists/fsl_component_generic_list.c"
"component/serial_manager/fsl_component_serial_port_uart.c"
"component/serial_manager/fsl_component_serial_manager.c"
"component/osa/fsl_os_abstraction_free_rtos.c"
"component/uart/fsl_adapter_lpuart.c"
"component/phy/device/phyksz8081/fsl_phyksz8081.c"
"component/phy/mdio/enet/fsl_enet_mdio.c"
"source/freertos_hello.c"
"source/user_irqhandlers.c"
"source/sdmmc_config.c"
"source/tasks/user_hello_task.c"
"source/tasks/user_sdcard_task.c"
"board/peripherals.c"
"board/pin_mux.c"
"board/board.c"
"board/dcd.c"
"board/clock_config.c"
"utilities/fsl_debug_console.c"
"utilities/fsl_sbrk.c"
"utilities/fsl_assert.c"
"utilities/fsl_str.c"
"middleware/sdmmc/sd/fsl_sd.c"
"middleware/sdmmc/common/fsl_sdmmc_common.c"
"middleware/sdmmc/mmc/fsl_mmc.c"
"middleware/sdmmc/osa/fsl_sdmmc_osa.c"
"middleware/sdmmc/sdio/fsl_sdio.c"
"middleware/sdmmc/host/usdhc/non_blocking/fsl_sdmmc_host.c"
"middleware/fatfs/source/ffsystem.c"
"middleware/fatfs/source/ffunicode.c"
"middleware/fatfs/source/diskio.c"
"middleware/fatfs/source/ff.c"
"middleware/fatfs/source/fsl_sd_disk/fsl_sd_disk.c"
"middleware/lwip/src/core/ipv4/ip4.c"
"middleware/lwip/src/core/ipv4/ip4_frag.c"
"middleware/lwip/src/core/ipv4/acd.c"
"middleware/lwip/src/core/ipv4/dhcp.c"
"middleware/lwip/src/core/ipv4/icmp.c"
"middleware/lwip/src/core/ipv4/ip4_addr.c"
"middleware/lwip/src/core/ipv4/igmp.c"
"middleware/lwip/src/core/ipv4/autoip.c"
"middleware/lwip/src/core/ipv4/etharp.c"
"middleware/lwip/src/core/memp.c"
"middleware/lwip/src/core/sys.c"
"middleware/lwip/src/core/altcp.c"
"middleware/lwip/src/core/ip.c"
"middleware/lwip/src/core/udp.c"
"middleware/lwip/src/core/tcp_in.c"
"middleware/lwip/src/core/mem.c"
"middleware/lwip/src/core/raw.c"
"middleware/lwip/src/core/dns.c"
"middleware/lwip/src/core/tcp.c"
"middleware/lwip/src/core/inet_chksum.c"
"middleware/lwip/src/core/ipv6/mld6.c"
"middleware/lwip/src/core/ipv6/ethip6.c"
"middleware/lwip/src/core/ipv6/ip6_frag.c"
"middleware/lwip/src/core/ipv6/dhcp6.c"
"middleware/lwip/src/core/ipv6/ip6.c"
"middleware/lwip/src/core/ipv6/inet6.c"
"middleware/lwip/src/core/ipv6/ip6_addr.c"
"middleware/lwip/src/core/ipv6/nd6.c"
"middleware/lwip/src/core/ipv6/icmp6.c"
"middleware/lwip/src/core/netif.c"
"middleware/lwip/src/core/def.c"
"middleware/lwip/src/core/tcp_out.c"
"middleware/lwip/src/core/init.c"
"middleware/lwip/src/core/altcp_tcp.c"
"middleware/lwip/src/core/pbuf.c"
"middleware/lwip/src/core/altcp_alloc.c"
"middleware/lwip/src/core/timeouts.c"
"middleware/lwip/src/core/stats.c"
"middleware/lwip/src/api/sockets.c"
"middleware/lwip/src/api/api_msg.c"
"middleware/lwip/src/api/netdb.c"
"middleware/lwip/src/api/api_lib.c"
"middleware/lwip/src/api/tcpip.c"
"middleware/lwip/src/api/netbuf.c"
"middleware/lwip/src/api/if_api.c"
"middleware/lwip/src/api/err.c"
"middleware/lwip/src/api/netifapi.c"
"middleware/lwip/src/netif/ethernet.c"
"middleware/lwip/src/netif/slipif.c"
"middleware/lwip/src/netif/ppp/ccp.c"
"middleware/lwip/src/netif/ppp/utils.c"
"middleware/lwip/src/netif/ppp/chap-md5.c"
"middleware/lwip/src/netif/ppp/upap.c"
"middleware/lwip/src/netif/ppp/eui64.c"
"middleware/lwip/src/netif/ppp/eap.c"
"middleware/lwip/src/netif/ppp/lwip_ecp.c"
"middleware/lwip/src/netif/ppp/mppe.c"
"middleware/lwip/src/netif/ppp/ipcp.c"
"middleware/lwip/src/netif/ppp/ipv6cp.c"
"middleware/lwip/src/netif/ppp/multilink.c"
"middleware/lwip/src/netif/ppp/pppcrypt.c"
"middleware/lwip/src/netif/ppp/polarssl/md4.c"
"middleware/lwip/src/netif/ppp/polarssl/des.c"
"middleware/lwip/src/netif/ppp/polarssl/sha1.c"
"middleware/lwip/src/netif/ppp/polarssl/md5.c"
"middleware/lwip/src/netif/ppp/polarssl/arc4.c"
"middleware/lwip/src/netif/ppp/pppol2tp.c"
"middleware/lwip/src/netif/ppp/demand.c"
"middleware/lwip/src/netif/ppp/pppapi.c"
"middleware/lwip/src/netif/ppp/lcp.c"
"middleware/lwip/src/netif/ppp/vj.c"
"middleware/lwip/src/netif/ppp/ppp.c"
"middleware/lwip/src/netif/ppp/chap-new.c"
"middleware/lwip/src/netif/ppp/pppoe.c"
"middleware/lwip/src/netif/ppp/fsm.c"
"middleware/lwip/src/netif/ppp/pppos.c"
"middleware/lwip/src/netif/ppp/auth.c"
"middleware/lwip/src/netif/ppp/magic.c"
"middleware/lwip/src/netif/ppp/chap_ms.c"
"middleware/lwip/src/netif/zepif.c"
"middleware/lwip/src/netif/lowpan6_ble.c"
"middleware/lwip/src/netif/lowpan6_common.c"
"middleware/lwip/src/netif/bridgeif.c"
"middleware/lwip/src/netif/bridgeif_fdb.c"
"middleware/lwip/src/netif/lowpan6.c"
"middleware/lwip/port/sys_arch.c"
"middleware/lwip/port/enet_ethernetif.c"
"middleware/lwip/port/enet_ethernetif_kinetis.c"
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${ProjDirPath}/board
${ProjDirPath}/source
# Copy them from Makefile
set(ASM_SOURCES
"startup/startup_MIMXRT1052.S"
)
set(CMAKE_MODULE_PATH
${ProjDirPath}/./
${ProjDirPath}/CMSIS
${ProjDirPath}/component/lists
${ProjDirPath}/component/serial_manager
${ProjDirPath}/component/uart
${ProjDirPath}/device
${ProjDirPath}/drivers
${ProjDirPath}/freertos
${ProjDirPath}/startup
${ProjDirPath}/utilities
${ProjDirPath}/xip
# Copy them from Makefile
add_definitions(
"-DCPU_MIMXRT1052DVL6B"
"-DFSL_RTOS_FREE_RTOS"
"-DUSE_RTOS"
"-DSERIAL_PORT_TYPE_UART=1"
"-D__STARTUP_CLEAR_BSS"
"-D__STARTUP_INITIALIZE_NONCACHEDATA"
"-DSD_ENABLED"
)
# include modules
include(driver_clock_MIMXRT1052)
# Copy them from Makefile
include_directories(
"drivers"
"CMSIS"
"freertos/freertos_kernel/include"
"freertos/freertos_kernel/portable/GCC/ARM_CM4F"
"device"
"xip"
"component/lists"
"component/serial_manager"
"component/osa"
"component/uart"
"component/phy"
"component/phy/mdio/enet"
"component/phy/device/phyksz8081"
"source"
"board"
"utilities"
"middleware/sdmmc/sd"
"middleware/sdmmc/common"
"middleware/sdmmc/mmc"
"middleware/sdmmc/osa"
"middleware/sdmmc/sdio"
"middleware/sdmmc/host/usdhc"
"middleware/fatfs/source"
"middleware/fatfs/source/fsl_sd_disk"
"middleware/lwip/src/include"
"middleware/lwip/port"
)
include(middleware_freertos-kernel_heap_4_MIMXRT1052)
# Conditional compiler flags
set(CMAKE_C_FLAGS_DEBUG "-g -DDEBUG")
set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG")
include(driver_common_MIMXRT1052)
set(CMAKE_CXX_FLAGS_DEBUG "-g -DDEBUG")
set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG")
include(device_MIMXRT1052_CMSIS_MIMXRT1052)
set(CMAKE_EXE_LINKER_FLAGS_DEBUG "-g")
include(utility_debug_console_MIMXRT1052)
# Final compiler flags
set(CMAKE_C_FLAGS "${CFLAGS_HARDWARE} ${CFLAGS_EXTRA} -Wall -fdata-sections -ffunction-sections -ffreestanding -fno-builtin")
set(CMAKE_CXX_FLAGS "${CFLAGS_HARDWARE} ${CFLAGS_EXTRA} -Wall -fdata-sections -ffunction-sections -ffreestanding -fno-builtin")
set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
set(CMAKE_EXE_LINKER_FLAGS "${CFLAGS_HARDWARE} -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections -lc -lm -lnosys ${LDFLAGS_EXTRA}")
include(component_lpuart_adapter_MIMXRT1052)
# Main targets are added here
include(component_serial_manager_MIMXRT1052)
# **** All In SRAM ****
include(component_lists_MIMXRT1052)
# Create ELF
add_executable("${CMAKE_PROJECT_NAME}_RAM.elf" ${C_SOURCES} ${ASM_SOURCES})
include(component_serial_manager_uart_MIMXRT1052)
# Linker script and Map files
target_link_options("${CMAKE_PROJECT_NAME}_RAM.elf"
PRIVATE "-T${LDSCRIPT_RAM}"
PRIVATE "-Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}_RAM.map,--cref"
)
include(driver_lpuart_MIMXRT1052)
add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_RAM.hex"
COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_RAM.elf" "${CMAKE_PROJECT_NAME}_RAM.hex"
DEPENDS "${CMAKE_PROJECT_NAME}_RAM.elf"
)
include(device_MIMXRT1052_startup_MIMXRT1052)
add_custom_target("${CMAKE_PROJECT_NAME}_RAM_HEX"
DEPENDS "${CMAKE_PROJECT_NAME}_RAM.hex"
)
include(driver_iomuxc_MIMXRT1052)
# **** FLEXSPI ****
include(utility_assert_MIMXRT1052)
# Create ELF
add_executable("${CMAKE_PROJECT_NAME}_FLEXSPI.elf" ${C_SOURCES} ${ASM_SOURCES})
include(driver_igpio_MIMXRT1052)
# Linker script and Map files
target_link_options("${CMAKE_PROJECT_NAME}_FLEXSPI.elf"
PRIVATE "-T${LDSCRIPT_FLEXSPI}"
PRIVATE "-Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}_FLEXSPI.map,--cref"
)
include(driver_xip_device_MIMXRT1052)
target_compile_definitions("${CMAKE_PROJECT_NAME}_FLEXSPI.elf"
PRIVATE "XIP_EXTERNAL_FLASH=1"
PRIVATE "XIP_BOOT_HEADER_ENABLE=1"
)
include(driver_xip_board_MIMXRT1052)
add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_FLEXSPI.hex"
COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_FLEXSPI.elf" "${CMAKE_PROJECT_NAME}_FLEXSPI.hex"
DEPENDS "${CMAKE_PROJECT_NAME}_FLEXSPI.elf"
)
include(middleware_freertos-kernel_MIMXRT1052)
add_custom_target("${CMAKE_PROJECT_NAME}_FLEXSPI_HEX"
DEPENDS "${CMAKE_PROJECT_NAME}_FLEXSPI.hex"
)
include(middleware_freertos-kernel_extension_MIMXRT1052)
# **** SDRAM ****
include(utilities_misc_utilities_MIMXRT1052)
# Create ELF
add_executable("${CMAKE_PROJECT_NAME}_SDRAM.elf" ${C_SOURCES} ${ASM_SOURCES})
include(CMSIS_Include_core_cm7_MIMXRT1052)
# Linker script and Map files
target_link_options("${CMAKE_PROJECT_NAME}_SDRAM.elf"
PRIVATE "-T${LDSCRIPT_SDRAM}"
PRIVATE "-Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}_SDRAM.map,--cref"
)
include(CMSIS_Include_common_MIMXRT1052)
include(CMSIS_Include_dsp_MIMXRT1052)
include(device_MIMXRT1052_system_MIMXRT1052)
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys)
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
target_compile_definitions("${CMAKE_PROJECT_NAME}_SDRAM.elf"
PRIVATE "DATA_SECTION_IS_CACHABLE=1"
PRIVATE "SKIP_SYSCLK_INIT"
)
add_custom_command(OUTPUT "${CMAKE_PROJECT_NAME}_SDRAM.hex"
COMMAND ${CMAKE_OBJCOPY} "-O" "ihex" "${CMAKE_PROJECT_NAME}_SDRAM.elf" "${CMAKE_PROJECT_NAME}_SDRAM.hex"
DEPENDS "${CMAKE_PROJECT_NAME}_SDRAM.elf"
)
add_custom_target("${CMAKE_PROJECT_NAME}_SDRAM_HEX"
DEPENDS "${CMAKE_PROJECT_NAME}_SDRAM.hex"
)

4
MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
View File

@ -41,6 +41,8 @@ MEMORY
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01800000
m_sdram_ncache (RW) : ORIGIN = 0x81800000, LENGTH = 0x00800000
}
/* Define output sections */
@ -207,7 +209,7 @@ SECTIONS
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_sdram_ncache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);

6
MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld
View File

@ -38,6 +38,8 @@ MEMORY
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01800000
m_sdram_ncache (RW) : ORIGIN = 0x81800000, LENGTH = 0x00800000
}
/* Define output sections */
@ -174,7 +176,7 @@ SECTIONS
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_sdram_ncache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -194,7 +196,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
} > m_data2
.heap :
{

6
MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld
View File

@ -30,7 +30,7 @@ ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81E00000 - HEAP_SIZE;
NCACHE_HEAP_START = DEFINED(__heap_noncacheable__) ? 0x82000000 - HEAP_SIZE : 0x81800000 - HEAP_SIZE;
NCACHE_HEAP_SIZE = DEFINED(__heap_noncacheable__) ? HEAP_SIZE : 0x0000;
/* Specify the memory areas */
@ -38,8 +38,8 @@ MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01E00000 : 0x01E00000 - HEAP_SIZE
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00200000 - HEAP_SIZE : 0x00200000
m_data (RW) : ORIGIN = 0x80000000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x01800000 : 0x01800000 - HEAP_SIZE
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = DEFINED(__heap_noncacheable__) ? 0x00800000 - HEAP_SIZE : 0x00800000
m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_heap (RW) : ORIGIN = NCACHE_HEAP_START, LENGTH = HEAP_SIZE

3
README.md Normal file
View File

@ -0,0 +1,3 @@
# i.MX RT1052 Example FreeRTOS App
[![Build Status](https://ci.minori.work/api/badges/Embedded_Drivers/RT1050_FreeRTOS_Hello/status.svg)](https://ci.minori.work/Embedded_Drivers/RT1050_FreeRTOS_Hello)

5
arm-none-eabi.cmake Normal file
View File

@ -0,0 +1,5 @@
set(CMAKE_C_COMPILER arm-none-eabi-gcc)
set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
# Make CMake happy about those compilers
set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY")

56
armgcc.cmake
View File

@ -1,56 +0,0 @@
# TOOLCHAIN EXTENSION
IF(WIN32)
SET(TOOLCHAIN_EXT ".exe")
ELSE()
SET(TOOLCHAIN_EXT "")
ENDIF()
# EXECUTABLE EXTENSION
SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
# TOOLCHAIN_DIR AND NANO LIBRARY
SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
STRING(REGEX REPLACE "\\\\" "/" TOOLCHAIN_DIR "${TOOLCHAIN_DIR}")
IF(NOT TOOLCHAIN_DIR)
MESSAGE(FATAL_ERROR "***Please set ARMGCC_DIR in envionment variables***")
ENDIF()
MESSAGE(STATUS "TOOLCHAIN_DIR: " ${TOOLCHAIN_DIR})
# TARGET_TRIPLET
SET(TARGET_TRIPLET "arm-none-eabi")
SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
SET(CMAKE_SYSTEM_NAME Generic)
SET(CMAKE_SYSTEM_PROCESSOR arm)
SET(CMAKE_C_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT})
SET(CMAKE_CXX_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-g++${TOOLCHAIN_EXT})
SET(CMAKE_ASM_COMPILER ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-gcc${TOOLCHAIN_EXT})
set(CMAKE_C_COMPILER_FORCED TRUE)
set(CMAKE_CXX_COMPILER_FORCED TRUE)
SET(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objcopy CACHE INTERNAL "objcopy tool")
SET(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/${TARGET_TRIPLET}-objdump CACHE INTERNAL "objdump tool")
SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "c compiler flags debug")
SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -g" CACHE INTERNAL "cxx compiler flags debug")
SET(CMAKE_ASM_FLAGS_DEBUG "${CMAKE_ASM_FLAGS_DEBUG} -g" CACHE INTERNAL "asm compiler flags debug")
SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG}" CACHE INTERNAL "linker flags debug")
SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -O3 " CACHE INTERNAL "c compiler flags release")
SET(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 " CACHE INTERNAL "cxx compiler flags release")
SET(CMAKE_ASM_FLAGS_RELEASE "${CMAKE_ASM_FLAGS_RELEASE}" CACHE INTERNAL "asm compiler flags release")
SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "${CMAKE_EXE_LINKER_FLAGS_RELEASE}" CACHE INTERNAL "linker flags release")
SET(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_DIR}/${TARGET_TRIPLET} ${EXTRA_FIND_PATH})
SET(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
MESSAGE(STATUS "BUILD_TYPE: " ${CMAKE_BUILD_TYPE})

129
board/board.c
View File

@ -234,28 +234,6 @@ status_t BOARD_Camera_I2C_ReceiveSCCB(
/* MPU configuration. */
void BOARD_ConfigMPU(void)
{
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
0 :
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
#endif
volatile uint32_t i = 0;
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
@ -269,109 +247,18 @@ void BOARD_ConfigMPU(void)
/* Disable MPU */
ARM_MPU_Disable();
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/
/*
* Add default region to deny access to whole address space to workaround speculative prefetch.
* Refer to Arm errata 1013783-B for more details.
*
*/
/* Region 0 setting: Instruction access disabled, No data access permission. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
#endif
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 1, 1, 1, 0, 0, ARM_MPU_REGION_SIZE_32MB);
MPU->RBAR = ARM_MPU_RBAR(2, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
MPU->RBAR = ARM_MPU_RBAR(3, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
MPU->RBAR = ARM_MPU_RBAR(4, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
while ((size >> i) > 0x1U)
{
i++;
}
if (i != 0)
{
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t)(1 << i));
assert(i >= 5);
/* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

2
board/board.h
View File

@ -30,7 +30,7 @@
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
#define BOARD_DEBUG_UART_BAUDRATE (921600)
#endif /* BOARD_DEBUG_UART_BAUDRATE */
/*! @brief The USER_LED used for board */

44
board/clock_config.c
View File

@ -19,7 +19,7 @@ product: Clocks v7.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 9.0.0
processor_version: 9.0.1
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@ -58,16 +58,16 @@ outputs:
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 125 MHz}
- {id: ENET_125M_CLK.outFreq, value: 125 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 25 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 33.75 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
@ -84,7 +84,7 @@ outputs:
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 150 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
@ -95,11 +95,14 @@ settings:
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '4', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.SEMC_PODF.scale, value: '4', locked: true}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM_ANALOG.ENET_DIV.scale, value: '4', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@ -124,8 +127,8 @@ settings:
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
@ -160,6 +163,13 @@ const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 3, /* Set frequency of ethernet reference clock to 125 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
@ -231,7 +241,7 @@ void BOARD_BootClockRUN(void)
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
CLOCK_SetDiv(kCLOCK_SemcDiv, 3);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
@ -326,7 +336,7 @@ void BOARD_BootClockRUN(void)
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 3);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
@ -426,16 +436,10 @@ void BOARD_BootClockRUN(void)
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK;
/* Disable bypass for Video PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Disable pfd offset. */
CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */

54
board/clock_config.c.bak
View File

@ -1,9 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
@ -25,7 +19,7 @@ product: Clocks v7.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 0.7.9
processor_version: 9.0.1
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@ -64,16 +58,16 @@ outputs:
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 125 MHz}
- {id: ENET_125M_CLK.outFreq, value: 125 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 25 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 36 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
@ -90,7 +84,7 @@ outputs:
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 150 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
@ -101,11 +95,14 @@ settings:
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LCDIF_PODF.scale, value: '5', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '3', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.SEMC_PODF.scale, value: '4', locked: true}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM_ANALOG.ENET_DIV.scale, value: '4', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@ -130,8 +127,8 @@ settings:
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
@ -166,6 +163,13 @@ const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 3, /* Set frequency of ethernet reference clock to 125 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
@ -237,7 +241,7 @@ void BOARD_BootClockRUN(void)
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
CLOCK_SetDiv(kCLOCK_SemcDiv, 3);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
@ -252,7 +256,7 @@ void BOARD_BootClockRUN(void)
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
@ -332,9 +336,9 @@ void BOARD_BootClockRUN(void)
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 2);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
CLOCK_SetDiv(kCLOCK_LcdifDiv, 4);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
@ -432,16 +436,10 @@ void BOARD_BootClockRUN(void)
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK;
/* Disable bypass for Video PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Disable pfd offset. */
CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */

13
board/clock_config.h
View File

@ -44,16 +44,16 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 125000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 125000000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 25000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 33750000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
@ -72,7 +72,7 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
@ -94,6 +94,9 @@ extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration

19
board/clock_config.h.bak
View File

@ -1,9 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
@ -50,16 +44,16 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 125000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 125000000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 25000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 36000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
@ -78,7 +72,7 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
@ -100,6 +94,9 @@ extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration

2
board/dcd.c
View File

@ -24,7 +24,7 @@ product: DCDx V2.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 9.0.0
processor_version: 9.0.1
board: IMXRT1050-EVKB
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

9
board/dcd.c.bak
View File

@ -1,10 +1,3 @@
/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@ -31,7 +24,7 @@ product: DCDx V2.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 0.0.0
processor_version: 9.0.0
board: IMXRT1050-EVKB
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

436
board/peripherals.c
View File

@ -10,7 +10,7 @@ product: Peripherals v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 9.0.0
processor_version: 9.0.1
board: IMXRT1050-EVKB
functionalGroups:
- name: BOARD_InitPeripherals
@ -55,7 +55,7 @@ instance:
- lpuartConfig:
- clockSource: 'LpuartClock'
- lpuartSrcClkFreq: 'BOARD_BootClockRUN'
- baudRate_Bps: '115200'
- baudRate_Bps: '921600'
- parityMode: 'kLPUART_ParityDisabled'
- dataBitsCount: 'kLPUART_EightDataBits'
- isMsb: 'false'
@ -70,11 +70,10 @@ instance:
- rxIdleConfig: 'kLPUART_IdleCharacter1'
- enableTx: 'true'
- enableRx: 'true'
- quick_selection: 'QuickSelection1'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
const lpuart_config_t LPUART1_config = {
.baudRate_Bps = 115200UL,
.baudRate_Bps = 921600UL,
.parityMode = kLPUART_ParityDisabled,
.dataBitsCount = kLPUART_EightDataBits,
.isMsb = false,
@ -95,6 +94,432 @@ static void LPUART1_init(void) {
LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
}
/***********************************************************************************************************************
* SEMC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'SEMC'
- type: 'semc'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'semc_84a769c198c91c527e11dcec2f5b4b81'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'SEMC'
- config_sets:
- fsl_semc:
- enableDCD: 'false'
- clockConfig:
- clockSource: 'kSEMC_ClkSrcPeri'
- clockSourceFreq: 'BOARD_BootClockRUN'
- semc_config_t:
- dqsMode: 'kSEMC_Loopbackdqspad'
- cmdTimeoutCycles: '0'
- busTimeoutCycles: '0'
- queueWeight:
- queueaEnable: 'false'
- queueaWeight:
- structORvalue: 'structure'
- queueaConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- slaveHitNoswitch: '0'
- queuebEnable: 'false'
- queuebWeight:
- structORvalue: 'structure'
- queuebConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- weightPagehit: '0'
- bankRotation: '0'
- semc_sdram_config_t:
- csxPinMux: 'kSEMC_MUXCSX0'
- semcSdramCs: 'kSEMC_SDRAM_CS0'
- address: '0x80000000'
- memsize_input: '32MB'
- portSize: 'kSEMC_PortSize16Bit'
- burstLen: 'kSEMC_Sdram_BurstLen1'
- columnAddrBitNum: 'kSEMC_SdramColunm_9bit'
- casLatency: 'kSEMC_LatencyThree'
- tPrecharge2Act_Ns: '18'
- tAct2ReadWrite_Ns: '18'
- tRefreshRecovery_Ns: '127'
- tWriteRecovery_Ns: '12'
- tCkeOff_Ns: '42'
- tAct2Prechage_Ns: '42'
- tSelfRefRecovery_Ns: '67'
- tRefresh2Refresh_Ns: '60'
- tAct2Act_Ns: '60'
- tPrescalePeriod_Ns: '160'
- tIdleTimeout_Ns: '0'
- refreshPeriod_nsPerRow: '64'
- refreshUrgThreshold: '64'
- refreshBurstLen: '1'
- sdramArray: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
semc_config_t SEMC_config = {
.dqsMode = kSEMC_Loopbackdqspad,
.cmdTimeoutCycles = 0U,
.busTimeoutCycles = 0U,
.queueWeight = {
.queueaEnable = false,
.queueaWeight = {
.queueaConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.slaveHitNoswitch = 0UL
},
},
.queuebEnable = false,
.queuebWeight = {
.queuebConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.weightPagehit = 0UL,
.bankRotation = 0UL
},
}
}
};
semc_sdram_config_t SEMC_sdram_struct = {
.csxPinMux = kSEMC_MUXCSX0,
.address = 0x80000000UL,
.memsize_kbytes = 32768,
.portSize = kSEMC_PortSize16Bit,
.burstLen = kSEMC_Sdram_BurstLen1,
.columnAddrBitNum = kSEMC_SdramColunm_9bit,
.casLatency = kSEMC_LatencyThree,
.tPrecharge2Act_Ns = 18U,
.tAct2ReadWrite_Ns = 18U,
.tRefreshRecovery_Ns = 127U,
.tWriteRecovery_Ns = 12U,
.tCkeOff_Ns = 42U,
.tAct2Prechage_Ns = 42U,
.tSelfRefRecovery_Ns = 67U,
.tRefresh2Refresh_Ns = 60U,
.tAct2Act_Ns = 60U,
.tPrescalePeriod_Ns = 160UL,
.tIdleTimeout_Ns = 0UL,
.refreshPeriod_nsPerRow = 64UL,
.refreshUrgThreshold = 64UL,
.refreshBurstLen = 1U,
};
static void SEMC_init(void) {
/* Initialize SEMC peripheral. */
SEMC_Init(SEMC_PERIPHERAL, &SEMC_config);
/* Initialize SEMC SDRAM. */
SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
}
/***********************************************************************************************************************
* LCDIF initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'LCDIF'
- type: 'elcdif'
- mode: 'rgbMode'
- custom_name_enabled: 'false'
- type_id: 'elcdif_1c39bcb43ed1a24bc8980672c7378576'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'LCDIF'
- config_sets:
- fsl_elcdif:
- config:
- panelWidthInt: '800'
- panelHeightInt: '480'
- hsw: '20'
- hfp: '210'
- hbp: '46'
- vsw: '10'
- vfp: '22'
- vbp: '23'
- frameRate: '60 Hz'
- polarityFlags_st:
- vSyncActive: 'kELCDIF_VsyncActiveLow'
- hSyncActive: 'kELCDIF_HsyncActiveLow'
- dataEnableActive: 'kELCDIF_DataEnableActiveHigh'
- driveDataClkEdge: 'kELCDIF_DriveDataOnRisingClkEdge'
- bufferName: 'defaultBuffer'
- bufferAlign: '64'
- pixelFormat: 'kELCDIF_PixelFormatRGB565'
- dataBus: 'kELCDIF_DataBus16Bit'
- enablePxpHandShake: 'false'
- start: 'true'
- isInterruptEnabled: 'true'
- elcdifInterruptSources: 'kELCDIF_CurFrameDoneInterruptEnable'
- interrupt:
- IRQn: 'LCDIF_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'true'
- priority: '5'
- enable_custom_name: 'false'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* RGB mode configuration */
const elcdif_rgb_mode_config_t LCDIF_rgbConfig = {
.panelWidth = LCDIF_PANEL_WIDTH,
.panelHeight = LCDIF_PANEL_HEIGHT,
.hsw = 20U,
.hfp = 210U,
.hbp = 46U,
.vsw = 10U,
.vfp = 22U,
.vbp = 23U,
.polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveHigh | kELCDIF_DriveDataOnRisingClkEdge),
.bufferAddr = (uint32_t) LCDIF_Buffer[0],
.pixelFormat = kELCDIF_PixelFormatRGB565,
.dataBus = kELCDIF_DataBus16Bit
};
/* RGB buffer */
AT_NONCACHEABLE_SECTION_ALIGN(uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN);
static void LCDIF_init(void) {
/* RGB mode initialization */
ELCDIF_RgbModeInit(LCDIF_PERIPHERAL, &LCDIF_rgbConfig);
/* Enable interrupts */
ELCDIF_EnableInterrupts(LCDIF_PERIPHERAL, (kELCDIF_CurFrameDoneInterruptEnable));
/* Interrupt vector LCDIF_IRQn priority settings in the NVIC. */
NVIC_SetPriority(LCDIF_LCDIF_IRQN, LCDIF_LCDIF_IRQ_PRIORITY);
/* Enable interrupt LCDIF_IRQn request in the NVIC. */
EnableIRQ(LCDIF_LCDIF_IRQN);
/* RGB mode start */
ELCDIF_RgbModeStart(LCDIF_PERIPHERAL);
}
/***********************************************************************************************************************
* NVIC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'NVIC'
- type: 'nvic'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'NVIC'
- config_sets:
- nvic:
- interrupt_table:
- 0: []
- 1: []
- 2: []
- interrupts: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* Empty initialization function (commented out)
static void NVIC_init(void) {
} */
/***********************************************************************************************************************
* GPIO1 initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'GPIO1'
- type: 'igpio'
- mode: 'GPIO'
- custom_name_enabled: 'false'
- type_id: 'igpio_b1c1fa279aa7069dca167502b8589cb7'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'GPIO1'
- config_sets:
- fsl_gpio:
- enable_irq_comb_0_15: 'true'
- gpio_interrupt_comb_0_15:
- IRQn: 'GPIO1_Combined_0_15_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'true'
- priority: '6'
- enable_custom_name: 'false'
- enable_irq_comb_16_31: 'true'
- gpio_interrupt_comb_16_31:
- IRQn: 'GPIO1_Combined_16_31_IRQn'
- enable_interrrupt: 'noInit'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int0: 'false'
- gpio_interrupt_int0:
- IRQn: 'GPIO1_INT0_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int1: 'false'
- gpio_interrupt_int1:
- IRQn: 'GPIO1_INT1_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int2: 'false'
- gpio_interrupt_int2:
- IRQn: 'GPIO1_INT2_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int3: 'false'
- gpio_interrupt_int3:
- IRQn: 'GPIO1_INT3_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int4: 'false'
- gpio_interrupt_int4:
- IRQn: 'GPIO1_INT4_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int5: 'false'
- gpio_interrupt_int5:
- IRQn: 'GPIO1_INT5_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int6: 'false'
- gpio_interrupt_int6:
- IRQn: 'GPIO1_INT6_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int7: 'false'
- gpio_interrupt_int7:
- IRQn: 'GPIO1_INT7_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
static void GPIO1_init(void) {
/* Make sure, the clock gate for GPIO1 is enabled (e. g. in pin_mux.c) */
/* Interrupt vector GPIO1_Combined_0_15_IRQn priority settings in the NVIC. */
NVIC_SetPriority(GPIO1_GPIO_COMB_0_15_IRQN, GPIO1_GPIO_COMB_0_15_IRQ_PRIORITY);
/* Enable interrupt GPIO1_Combined_0_15_IRQn request in the NVIC. */
EnableIRQ(GPIO1_GPIO_COMB_0_15_IRQN);
/* Interrupt GPIO1_Combined_16_31_IRQn request in the NVIC is not initialized (disabled by default). */
/* It can be enabled later by EnableIRQ(GPIO1_GPIO_COMB_16_31_IRQN); function call. */
}
/***********************************************************************************************************************
* FATFS initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'FATFS'
- type: 'fatfs'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'fatfs_2f85acf758668258920f70258052a088'
- functional_group: 'BOARD_InitPeripherals'
- config_sets:
- init_config:
- initConfig:
- initPartitionsStr: 'false'
- multiplePartitions:
- 0:
- Volume: '0'
- Partition: 'autoDetect'
- 1:
- Volume: '0'
- Partition: 'autoDetect'
- enablePhysicalLayerInit: 'false'
- diskConfig:
- initFunctionID: 'FATFS_DiskInit'
- initResultObject: 'false'
- resultName: 'FATFS_Result'
- fatfsObjects:
- 0:
- objID: 'FATFS_System_0'
- diskMount: 'false'
- mountPath: '0:'
- mountInitOpt: 'false'
- filObjects: []
- filInfoObjects: []
- dirObjects: []
- ff_config:
- revisionID: 'rev14_1'
- MSDKadaptation: 'SD_DISK_ENABLE'
- functionConfig:
- FF_FS_READONLY: 'false'
- FF_FS_MINIMIZE: 'level1'
- FF_USE_STRFUNC: 'enableWithoutConversion'
- FF_USE_FIND: 'disableDirRead'
- FF_USE_MKFS: 'true'
- FF_USE_FASTSEEK: 'false'
- FF_USE_EXPAND: 'false'
- FF_USE_CHMOD: 'false'
- FF_USE_LABEL: 'false'
- FF_USE_FORWARD: 'false'
- namespaceConfig:
- FF_USE_LFN: 'enableLfnStack'
- FF_MAX_LFN: '255'
- FF_LFN_BUF: 'LFNID'
- FF_SFN_BUF: 'SFNID'
- FF_LFN_UNICODE: 'UTF8'
- FF_STRF_ENCODE: 'UTF8'
- FF_CODE_PAGE: 'cpUS'
- FF_FS_RPATH: 'enableRP2'
- driveConfig:
- FF_VOLUMES: '3'
- FF_STR_VOLUME_ID: 'stringIdWindows'
- volumes:
- 0:
- volumeStr: 'RAM'
- 1:
- volumeStr: 'USB'
- 2:
- volumeStr: 'SD'
- FF_MULTI_PARTITION: 'false'
- FF_MIN_SS: 'value512'
- FF_MAX_SS: 'value512'
- FF_LBA64: 'false'
- FF_MIN_GPT: '0x100000000'
- FF_USE_TRIM: 'false'
- systemConfig:
- FF_FS_TINY: 'false'
- FF_FS_EXFAT: 'false'
- FF_FS_NORTC: 'true'
- FF_NORTC_MON: '1'
- FF_NORTC_MDAY: '1'
- FF_NORTC_YEAR: '2021'
- FF_FS_NOFSINFO: ''
- FF_FS_LOCK: '0'
- FF_FS_REENTRANT: 'false'
- FF_FS_TIMEOUT: '1000'
- FF_SYNC_t: 'HANDLE'
- includeOS: 'false'
- headerFileName: 'somertos.h'
- fatfs_codegenerator: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* FATFS System object */
FATFS FATFS_System_0;
/* Empty initialization function (commented out)
static void FATFS_init(void) {
} */
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
@ -102,6 +527,9 @@ void BOARD_InitPeripherals(void)
{
/* Initialize components */
LPUART1_init();
SEMC_init();
LCDIF_init();
GPIO1_init();
}
/***********************************************************************************************************************

489
board/peripherals.c.bak
View File

@ -10,7 +10,7 @@ product: Peripherals v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 9.0.0
processor_version: 9.0.1
board: IMXRT1050-EVKB
functionalGroups:
- name: BOARD_InitPeripherals
@ -34,11 +34,498 @@ component:
**********************************************************************************************************************/
#include "peripherals.h"
/***********************************************************************************************************************
* BOARD_InitPeripherals functional group
**********************************************************************************************************************/
/***********************************************************************************************************************
* LPUART1 initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'LPUART1'
- type: 'lpuart'
- mode: 'polling'
- custom_name_enabled: 'false'
- type_id: 'lpuart_54a65a580e3462acdbacefd5299e0cac'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'LPUART1'
- config_sets:
- lpuartConfig_t:
- lpuartConfig:
- clockSource: 'LpuartClock'
- lpuartSrcClkFreq: 'BOARD_BootClockRUN'
- baudRate_Bps: '921600'
- parityMode: 'kLPUART_ParityDisabled'
- dataBitsCount: 'kLPUART_EightDataBits'
- isMsb: 'false'
- stopBitCount: 'kLPUART_OneStopBit'
- txFifoWatermark: '0'
- rxFifoWatermark: '1'
- enableRxRTS: 'false'
- enableTxCTS: 'false'
- txCtsSource: 'kLPUART_CtsSourcePin'
- txCtsConfig: 'kLPUART_CtsSampleAtStart'
- rxIdleType: 'kLPUART_IdleTypeStartBit'
- rxIdleConfig: 'kLPUART_IdleCharacter1'
- enableTx: 'true'
- enableRx: 'true'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
const lpuart_config_t LPUART1_config = {
.baudRate_Bps = 921600UL,
.parityMode = kLPUART_ParityDisabled,
.dataBitsCount = kLPUART_EightDataBits,
.isMsb = false,
.stopBitCount = kLPUART_OneStopBit,
.txFifoWatermark = 0U,
.rxFifoWatermark = 1U,
.enableRxRTS = false,
.enableTxCTS = false,
.txCtsSource = kLPUART_CtsSourcePin,
.txCtsConfig = kLPUART_CtsSampleAtStart,
.rxIdleType = kLPUART_IdleTypeStartBit,
.rxIdleConfig = kLPUART_IdleCharacter1,
.enableTx = true,
.enableRx = true
};
static void LPUART1_init(void) {
LPUART_Init(LPUART1_PERIPHERAL, &LPUART1_config, LPUART1_CLOCK_SOURCE);
}
/***********************************************************************************************************************
* SEMC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'SEMC'
- type: 'semc'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'semc_84a769c198c91c527e11dcec2f5b4b81'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'SEMC'
- config_sets:
- fsl_semc:
- enableDCD: 'false'
- clockConfig:
- clockSource: 'kSEMC_ClkSrcPeri'
- clockSourceFreq: 'BOARD_BootClockRUN'
- semc_config_t:
- dqsMode: 'kSEMC_Loopbackdqspad'
- cmdTimeoutCycles: '0'
- busTimeoutCycles: '0'
- queueWeight:
- queueaEnable: 'false'
- queueaWeight:
- structORvalue: 'structure'
- queueaConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- slaveHitNoswitch: '0'
- queuebEnable: 'false'
- queuebWeight:
- structORvalue: 'structure'
- queuebConfig:
- qos: '0'
- aging: '0'
- slaveHitSwith: '0'
- weightPagehit: '0'
- bankRotation: '0'
- semc_sdram_config_t:
- csxPinMux: 'kSEMC_MUXCSX0'
- semcSdramCs: 'kSEMC_SDRAM_CS0'
- address: '0x80000000'
- memsize_input: '32MB'
- portSize: 'kSEMC_PortSize16Bit'
- burstLen: 'kSEMC_Sdram_BurstLen1'
- columnAddrBitNum: 'kSEMC_SdramColunm_9bit'
- casLatency: 'kSEMC_LatencyThree'
- tPrecharge2Act_Ns: '18'
- tAct2ReadWrite_Ns: '18'
- tRefreshRecovery_Ns: '127'
- tWriteRecovery_Ns: '12'
- tCkeOff_Ns: '42'
- tAct2Prechage_Ns: '42'
- tSelfRefRecovery_Ns: '67'
- tRefresh2Refresh_Ns: '60'
- tAct2Act_Ns: '60'
- tPrescalePeriod_Ns: '160'
- tIdleTimeout_Ns: '0'
- refreshPeriod_nsPerRow: '64'
- refreshUrgThreshold: '64'
- refreshBurstLen: '1'
- sdramArray: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
semc_config_t SEMC_config = {
.dqsMode = kSEMC_Loopbackdqspad,
.cmdTimeoutCycles = 0U,
.busTimeoutCycles = 0U,
.queueWeight = {
.queueaEnable = false,
.queueaWeight = {
.queueaConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.slaveHitNoswitch = 0UL
},
},
.queuebEnable = false,
.queuebWeight = {
.queuebConfig = {
.qos = 0UL,
.aging = 0UL,
.slaveHitSwith = 0UL,
.weightPagehit = 0UL,
.bankRotation = 0UL
},
}
}
};
semc_sdram_config_t SEMC_sdram_struct = {
.csxPinMux = kSEMC_MUXCSX0,
.address = 0x80000000UL,
.memsize_kbytes = 32768,
.portSize = kSEMC_PortSize16Bit,
.burstLen = kSEMC_Sdram_BurstLen1,
.columnAddrBitNum = kSEMC_SdramColunm_9bit,
.casLatency = kSEMC_LatencyThree,
.tPrecharge2Act_Ns = 18U,
.tAct2ReadWrite_Ns = 18U,
.tRefreshRecovery_Ns = 127U,
.tWriteRecovery_Ns = 12U,
.tCkeOff_Ns = 42U,
.tAct2Prechage_Ns = 42U,
.tSelfRefRecovery_Ns = 67U,
.tRefresh2Refresh_Ns = 60U,
.tAct2Act_Ns = 60U,
.tPrescalePeriod_Ns = 160UL,
.tIdleTimeout_Ns = 0UL,
.refreshPeriod_nsPerRow = 64UL,
.refreshUrgThreshold = 64UL,
.refreshBurstLen = 1U,
};
static void SEMC_init(void) {
/* Initialize SEMC peripheral. */
SEMC_Init(SEMC_PERIPHERAL, &SEMC_config);
/* Initialize SEMC SDRAM. */
SEMC_ConfigureSDRAM(SEMC_PERIPHERAL, kSEMC_SDRAM_CS0, &SEMC_sdram_struct, 150000000);
}
/***********************************************************************************************************************
* LCDIF initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'LCDIF'
- type: 'elcdif'
- mode: 'rgbMode'
- custom_name_enabled: 'false'
- type_id: 'elcdif_1c39bcb43ed1a24bc8980672c7378576'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'LCDIF'
- config_sets:
- fsl_elcdif:
- config:
- panelWidthInt: '800'
- panelHeightInt: '480'
- hsw: '20'
- hfp: '210'
- hbp: '46'
- vsw: '10'
- vfp: '22'
- vbp: '23'
- frameRate: '60 Hz'
- polarityFlags_st:
- vSyncActive: 'kELCDIF_VsyncActiveLow'
- hSyncActive: 'kELCDIF_HsyncActiveLow'
- dataEnableActive: 'kELCDIF_DataEnableActiveHigh'
- driveDataClkEdge: 'kELCDIF_DriveDataOnRisingClkEdge'
- bufferName: 'defaultBuffer'
- bufferAlign: '64'
- pixelFormat: 'kELCDIF_PixelFormatRGB565'
- dataBus: 'kELCDIF_DataBus16Bit'
- enablePxpHandShake: 'false'
- start: 'true'
- isInterruptEnabled: 'true'
- elcdifInterruptSources: 'kELCDIF_CurFrameDoneInterruptEnable'
- interrupt:
- IRQn: 'LCDIF_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'true'
- priority: '5'
- enable_custom_name: 'false'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* RGB mode configuration */
const elcdif_rgb_mode_config_t LCDIF_rgbConfig = {
.panelWidth = LCDIF_PANEL_WIDTH,
.panelHeight = LCDIF_PANEL_HEIGHT,
.hsw = 20U,
.hfp = 210U,
.hbp = 46U,
.vsw = 10U,
.vfp = 22U,
.vbp = 23U,
.polarityFlags = (kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveHigh | kELCDIF_DriveDataOnRisingClkEdge),
.bufferAddr = (uint32_t) LCDIF_Buffer[0],
.pixelFormat = kELCDIF_PixelFormatRGB565,
.dataBus = kELCDIF_DataBus16Bit
};
/* RGB buffer */
AT_NONCACHEABLE_SECTION_ALIGN(uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH], LCDIF_RGB_BUFFER_ALIGN);
static void LCDIF_init(void) {
/* RGB mode initialization */
ELCDIF_RgbModeInit(LCDIF_PERIPHERAL, &LCDIF_rgbConfig);
/* Enable interrupts */
ELCDIF_EnableInterrupts(LCDIF_PERIPHERAL, (kELCDIF_CurFrameDoneInterruptEnable));
/* Interrupt vector LCDIF_IRQn priority settings in the NVIC. */
NVIC_SetPriority(LCDIF_LCDIF_IRQN, LCDIF_LCDIF_IRQ_PRIORITY);
/* Enable interrupt LCDIF_IRQn request in the NVIC. */
EnableIRQ(LCDIF_LCDIF_IRQN);
/* RGB mode start */
ELCDIF_RgbModeStart(LCDIF_PERIPHERAL);
}
/***********************************************************************************************************************
* NVIC initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'NVIC'
- type: 'nvic'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'NVIC'
- config_sets:
- nvic:
- interrupt_table:
- 0: []
- 1: []
- 2: []
- interrupts: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* Empty initialization function (commented out)
static void NVIC_init(void) {
} */
/***********************************************************************************************************************
* GPIO1 initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'GPIO1'
- type: 'igpio'
- mode: 'GPIO'
- custom_name_enabled: 'false'
- type_id: 'igpio_b1c1fa279aa7069dca167502b8589cb7'
- functional_group: 'BOARD_InitPeripherals'
- peripheral: 'GPIO1'
- config_sets:
- fsl_gpio:
- enable_irq_comb_0_15: 'true'
- gpio_interrupt_comb_0_15:
- IRQn: 'GPIO1_Combined_0_15_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'true'
- priority: '6'
- enable_custom_name: 'false'
- enable_irq_comb_16_31: 'true'
- gpio_interrupt_comb_16_31:
- IRQn: 'GPIO1_Combined_16_31_IRQn'
- enable_interrrupt: 'noInit'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int0: 'false'
- gpio_interrupt_int0:
- IRQn: 'GPIO1_INT0_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int1: 'false'
- gpio_interrupt_int1:
- IRQn: 'GPIO1_INT1_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int2: 'false'
- gpio_interrupt_int2:
- IRQn: 'GPIO1_INT2_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int3: 'false'
- gpio_interrupt_int3:
- IRQn: 'GPIO1_INT3_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int4: 'false'
- gpio_interrupt_int4:
- IRQn: 'GPIO1_INT4_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int5: 'false'
- gpio_interrupt_int5:
- IRQn: 'GPIO1_INT5_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int6: 'false'
- gpio_interrupt_int6:
- IRQn: 'GPIO1_INT6_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
- enable_irq_int7: 'false'
- gpio_interrupt_int7:
- IRQn: 'GPIO1_INT7_IRQn'
- enable_interrrupt: 'enabled'
- enable_priority: 'false'
- priority: '0'
- enable_custom_name: 'false'
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
static void GPIO1_init(void) {
/* Make sure, the clock gate for GPIO1 is enabled (e. g. in pin_mux.c) */
/* Interrupt vector GPIO1_Combined_0_15_IRQn priority settings in the NVIC. */
NVIC_SetPriority(GPIO1_GPIO_COMB_0_15_IRQN, GPIO1_GPIO_COMB_0_15_IRQ_PRIORITY);
/* Enable interrupt GPIO1_Combined_0_15_IRQn request in the NVIC. */
EnableIRQ(GPIO1_GPIO_COMB_0_15_IRQN);
/* Interrupt GPIO1_Combined_16_31_IRQn request in the NVIC is not initialized (disabled by default). */
/* It can be enabled later by EnableIRQ(GPIO1_GPIO_COMB_16_31_IRQN); function call. */
}
/***********************************************************************************************************************
* FATFS initialization code
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
instance:
- name: 'FATFS'
- type: 'fatfs'
- mode: 'general'
- custom_name_enabled: 'false'
- type_id: 'fatfs_2f85acf758668258920f70258052a088'
- functional_group: 'BOARD_InitPeripherals'
- config_sets:
- init_config:
- initConfig:
- initPartitionsStr: 'false'
- multiplePartitions:
- 0:
- Volume: '0'
- Partition: 'autoDetect'
- 1:
- Volume: '0'
- Partition: 'autoDetect'
- enablePhysicalLayerInit: 'false'
- diskConfig:
- initFunctionID: 'FATFS_DiskInit'
- initResultObject: 'false'
- resultName: 'FATFS_Result'
- fatfsObjects:
- 0:
- objID: 'FATFS_System_0'
- diskMount: 'false'
- mountPath: '0:'
- mountInitOpt: 'false'
- filObjects: []
- filInfoObjects: []
- dirObjects: []
- ff_config:
- revisionID: 'rev14_1'
- MSDKadaptation: 'SD_DISK_ENABLE'
- functionConfig:
- FF_FS_READONLY: 'false'
- FF_FS_MINIMIZE: 'level1'
- FF_USE_STRFUNC: 'enableWithoutConversion'
- FF_USE_FIND: 'disableDirRead'
- FF_USE_MKFS: 'true'
- FF_USE_FASTSEEK: 'false'
- FF_USE_EXPAND: 'false'
- FF_USE_CHMOD: 'false'
- FF_USE_LABEL: 'false'
- FF_USE_FORWARD: 'false'
- namespaceConfig:
- FF_USE_LFN: 'enableLfnStack'
- FF_MAX_LFN: '255'
- FF_LFN_BUF: 'LFNID'
- FF_SFN_BUF: 'SFNID'
- FF_LFN_UNICODE: 'UTF8'
- FF_STRF_ENCODE: 'UTF8'
- FF_CODE_PAGE: 'cpUS'
- FF_FS_RPATH: 'enableRP2'
- driveConfig:
- FF_VOLUMES: '1'
- FF_STR_VOLUME_ID: 'numericId'
- volumes:
- 0:
- volumeStr: 'SD'
- FF_MULTI_PARTITION: 'false'
- FF_MIN_SS: 'value512'
- FF_MAX_SS: 'value512'
- FF_LBA64: 'false'
- FF_MIN_GPT: '0x100000000'
- FF_USE_TRIM: 'false'
- systemConfig:
- FF_FS_TINY: 'false'
- FF_FS_EXFAT: 'false'
- FF_FS_NORTC: 'true'
- FF_NORTC_MON: '1'
- FF_NORTC_MDAY: '1'
- FF_NORTC_YEAR: '2021'
- FF_FS_NOFSINFO: ''
- FF_FS_LOCK: '0'
- FF_FS_REENTRANT: 'false'
- FF_FS_TIMEOUT: '1000'
- FF_SYNC_t: 'HANDLE'
- includeOS: 'false'
- headerFileName: 'somertos.h'
- fatfs_codegenerator: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/* FATFS System object */
FATFS FATFS_System_0;
/* Empty initialization function (commented out)
static void FATFS_init(void) {
} */
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void)
{
/* Initialize components */
LPUART1_init();
SEMC_init();
LCDIF_init();
GPIO1_init();
}
/***********************************************************************************************************************

42
board/peripherals.h
View File

@ -12,6 +12,11 @@
#include "fsl_common.h"
#include "fsl_lpuart.h"
#include "fsl_clock.h"
#include "fsl_semc.h"
#include "fsl_elcdif.h"
#include "fsl_gpio.h"
#include "ff.h"
#include "diskio.h"
#if defined(__cplusplus)
extern "C" {
@ -25,11 +30,48 @@ extern "C" {
#define LPUART1_PERIPHERAL LPUART1
/* Definition of the clock source frequency */
#define LPUART1_CLOCK_SOURCE 80000000UL
/* BOARD_InitPeripherals defines for SEMC */
/* Definition of peripheral ID. */
#define SEMC_PERIPHERAL SEMC
/* Definition of peripheral ID */
#define LCDIF_PERIPHERAL LCDIF
/* Definition of the expected display clock frequency */
#define LCDIF_EXPECTED_DCLK_FREQ 34539600UL
/* Definition of the panel width */
#define LCDIF_PANEL_WIDTH 800
/* Definition of the panel height */
#define LCDIF_PANEL_HEIGHT 480
/* Definition of the RGB buffer alignment */
#define LCDIF_RGB_BUFFER_ALIGN 64
/* LCDIF interrupt vector ID (number). */
#define LCDIF_LCDIF_IRQN LCDIF_IRQn
/* LCDIF interrupt vector priority. */
#define LCDIF_LCDIF_IRQ_PRIORITY 5
/* LCDIF interrupt handler identifier. */
#define LCDIF_LCDIF_IRQHANDLER LCDIF_IRQHandler
/* GPIO1 interrupt vector ID (number). */
#define GPIO1_GPIO_COMB_0_15_IRQN GPIO1_Combined_0_15_IRQn
/* GPIO1 interrupt vector priority. */
#define GPIO1_GPIO_COMB_0_15_IRQ_PRIORITY 6
/* GPIO1 interrupt handler identifier. */
#define GPIO1_GPIO_COMB_0_15_IRQHANDLER GPIO1_Combined_0_15_IRQHandler
/* GPIO1 interrupt vector ID (number). */
#define GPIO1_GPIO_COMB_16_31_IRQN GPIO1_Combined_16_31_IRQn
/* GPIO1 interrupt handler identifier. */
#define GPIO1_GPIO_COMB_16_31_IRQHANDLER GPIO1_Combined_16_31_IRQHandler
/***********************************************************************************************************************
* Global variables
**********************************************************************************************************************/
extern const lpuart_config_t LPUART1_config;
extern semc_config_t SEMC_config;
extern semc_sdram_config_t SEMC_sdram_struct;
/* RGB mode configuration */
extern const elcdif_rgb_mode_config_t LCDIF_rgbConfig;
/* RGB buffer */
extern uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH];
/* FATFS System object */
extern FATFS FATFS_System_0;
/***********************************************************************************************************************
* Initialization functions

59
board/peripherals.h.bak
View File

@ -6,10 +6,69 @@
#ifndef _PERIPHERALS_H_
#define _PERIPHERALS_H_
/***********************************************************************************************************************
* Included files
**********************************************************************************************************************/
#include "fsl_common.h"
#include "fsl_lpuart.h"
#include "fsl_clock.h"
#include "fsl_semc.h"
#include "fsl_elcdif.h"
#include "fsl_gpio.h"
#include "ff.h"
#include "diskio.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/* Definitions for BOARD_InitPeripherals functional group */
/* Definition of peripheral ID */
#define LPUART1_PERIPHERAL LPUART1
/* Definition of the clock source frequency */
#define LPUART1_CLOCK_SOURCE 80000000UL
/* BOARD_InitPeripherals defines for SEMC */
/* Definition of peripheral ID. */
#define SEMC_PERIPHERAL SEMC
/* Definition of peripheral ID */
#define LCDIF_PERIPHERAL LCDIF
/* Definition of the expected display clock frequency */
#define LCDIF_EXPECTED_DCLK_FREQ 34539600UL
/* Definition of the panel width */
#define LCDIF_PANEL_WIDTH 800
/* Definition of the panel height */
#define LCDIF_PANEL_HEIGHT 480
/* Definition of the RGB buffer alignment */
#define LCDIF_RGB_BUFFER_ALIGN 64
/* LCDIF interrupt vector ID (number). */
#define LCDIF_LCDIF_IRQN LCDIF_IRQn
/* LCDIF interrupt vector priority. */
#define LCDIF_LCDIF_IRQ_PRIORITY 5
/* LCDIF interrupt handler identifier. */
#define LCDIF_LCDIF_IRQHANDLER LCDIF_IRQHandler
/* GPIO1 interrupt vector ID (number). */
#define GPIO1_GPIO_COMB_0_15_IRQN GPIO1_Combined_0_15_IRQn
/* GPIO1 interrupt vector priority. */
#define GPIO1_GPIO_COMB_0_15_IRQ_PRIORITY 6
/* GPIO1 interrupt handler identifier. */
#define GPIO1_GPIO_COMB_0_15_IRQHANDLER GPIO1_Combined_0_15_IRQHandler
/***********************************************************************************************************************
* Global variables
**********************************************************************************************************************/
extern const lpuart_config_t LPUART1_config;
extern semc_config_t SEMC_config;
extern semc_sdram_config_t SEMC_sdram_struct;
/* RGB mode configuration */
extern const elcdif_rgb_mode_config_t LCDIF_rgbConfig;
/* RGB buffer */
extern uint16_t LCDIF_Buffer[2][LCDIF_PANEL_HEIGHT][LCDIF_PANEL_WIDTH];
/* FATFS System object */
extern FATFS FATFS_System_0;
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/

213
board/pin_mux.c
View File

@ -10,13 +10,20 @@ product: Pins v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 9.0.0
processor_version: 9.0.1
board: IMXRT1050-EVKB
pin_labels:
- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: LCDIF_RESET, identifier: LCDIF_RESEt;LCDIF_RESET}
- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: 'USB_OTG1_OC/J24[1]', identifier: SD1_CD}
- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: LED_BLUE, identifier: INT1_COMBO;LED_BLUE}
- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: LCDIF_BL, identifier: CAN2_RX;LCDIF_BL}
power_domains: {NVCC_GPIO: '3.3', NVCC_SD0: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
@ -38,6 +45,89 @@ BOARD_InitPins:
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
- {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, identifier: LCDIF_RESET, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: G13, peripheral: GPIO1, signal: 'gpio_io, 10', pin_signal: GPIO_AD_B0_10, identifier: LED_BLUE, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: L10, peripheral: GPIO1, signal: 'gpio_io, 15', pin_signal: GPIO_AD_B0_15, identifier: LCDIF_BL, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: L12, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_AD_B1_04}
- {pin_num: B14, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_B1_15}
- {pin_num: B13, peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_B1_10}
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
- {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
- {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03, direction: INPUT, gpio_interrupt: kGPIO_IntRisingOrFallingEdge, pull_up_down_config: Pull_Up_100K_Ohm,
pull_keeper_select: Pull}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@ -50,8 +140,129 @@ BOARD_InitPins:
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of LCDIF_RESET on GPIO_AD_B0_02 (pin M11) */
gpio_pin_config_t LCDIF_RESET_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */
GPIO_PinInit(GPIO1, 2U, &LCDIF_RESET_config);
/* GPIO configuration of SD1_CD on GPIO_AD_B0_03 (pin G11) */
gpio_pin_config_t SD1_CD_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_IntRisingOrFallingEdge
};
/* Initialize GPIO functionality on GPIO_AD_B0_03 (pin G11) */
GPIO_PinInit(GPIO1, 3U, &SD1_CD_config);
/* Enable GPIO pin interrupt on GPIO_AD_B0_03 (pin G11) */
GPIO_PortEnableInterrupts(GPIO1, 1U << 3U);
/* GPIO configuration of LED_BLUE on GPIO_AD_B0_10 (pin G13) */
gpio_pin_config_t LED_BLUE_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_10 (pin G13) */
GPIO_PinInit(GPIO1, 10U, &LED_BLUE_config);
/* GPIO configuration of LCDIF_BL on GPIO_AD_B0_15 (pin L10) */
gpio_pin_config_t LCDIF_BL_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_15 (pin L10) */
GPIO_PinInit(GPIO1, 15U, &LCDIF_BL_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_GPIO1_IO15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_ENET_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_TX_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0xB0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}

254
board/pin_mux.c.bak
View File

@ -1,10 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@ -13,16 +6,24 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v7.0
product: Pins v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 6.0.0
processor_version: 9.0.1
board: IMXRT1050-EVKB
pin_labels:
- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: LCDIF_RESET, identifier: LCDIF_RESEt;LCDIF_RESET}
- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: 'USB_OTG1_OC/J24[1]', identifier: SD1_CD}
- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: LED_BLUE, identifier: INT1_COMBO;LED_BLUE}
- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: LCDIF_BL, identifier: CAN2_RX;LCDIF_BL}
power_domains: {NVCC_GPIO: '3.3', NVCC_SD0: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
@ -44,6 +45,88 @@ BOARD_InitPins:
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: A7, peripheral: SEMC, signal: semc_rdy, pin_signal: GPIO_EMC_40}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00}
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01}
- {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02, identifier: LCDIF_RESET, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: G13, peripheral: GPIO1, signal: 'gpio_io, 10', pin_signal: GPIO_AD_B0_10, identifier: LED_BLUE, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: L10, peripheral: GPIO1, signal: 'gpio_io, 15', pin_signal: GPIO_AD_B0_15, identifier: LCDIF_BL, direction: OUTPUT, gpio_init_state: 'true'}
- {pin_num: L12, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_AD_B1_04}
- {pin_num: B14, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_B1_15}
- {pin_num: B13, peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_B1_10}
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
- {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
- {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 03', pin_signal: GPIO_AD_B0_03, direction: INPUT, gpio_interrupt: kGPIO_IntRisingOrFallingEdge, pull_up_down_config: Pull_Up_22K_Ohm}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@ -54,34 +137,133 @@ BOARD_InitPins:
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
/* GPIO configuration of LCDIF_RESET on GPIO_AD_B0_02 (pin M11) */
gpio_pin_config_t LCDIF_RESET_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_02 (pin M11) */
GPIO_PinInit(GPIO1, 2U, &LCDIF_RESET_config);
/* GPIO configuration of SD1_CD on GPIO_AD_B0_03 (pin G11) */
gpio_pin_config_t SD1_CD_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_IntRisingOrFallingEdge
};
/* Initialize GPIO functionality on GPIO_AD_B0_03 (pin G11) */
GPIO_PinInit(GPIO1, 3U, &SD1_CD_config);
/* Enable GPIO pin interrupt on GPIO_AD_B0_03 (pin G11) */
GPIO_PortEnableInterrupts(GPIO1, 1U << 3U);
/* GPIO configuration of LED_BLUE on GPIO_AD_B0_10 (pin G13) */
gpio_pin_config_t LED_BLUE_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_10 (pin G13) */
GPIO_PinInit(GPIO1, 10U, &LED_BLUE_config);
/* GPIO configuration of LCDIF_BL on GPIO_AD_B0_15 (pin L10) */
gpio_pin_config_t LCDIF_BL_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 1U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_15 (pin L10) */
GPIO_PinInit(GPIO1, 15U, &LCDIF_BL_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_GPIO1_IO15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_ENET_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_TX_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, 0xD0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
/***********************************************************************************************************************

505
board/pin_mux.h
View File

@ -47,6 +47,511 @@ void BOARD_InitBootPins(void);
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */
#define BOARD_INITPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDC_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDC_SIGNAL semc_rdy /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */
/* GPIO_AD_B0_02 (coord M11), LCDIF_RESET */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_RESET_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_RESET_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LCDIF_RESET_CHANNEL 2U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LCDIF_RESET_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN 2U /*!< GPIO pin number */
#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LCDIF_RESET_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LCDIF_RESET_PIN 2U /*!< PORT pin number */
#define BOARD_INITPINS_LCDIF_RESET_PIN_MASK (1U << 2U) /*!< PORT pin mask */
/* GPIO_AD_B0_10 (coord G13), LED_BLUE */
/* Routed pin properties */
#define BOARD_INITPINS_LED_BLUE_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LED_BLUE_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LED_BLUE_CHANNEL 10U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_BLUE_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_BLUE_GPIO_PIN 10U /*!< GPIO pin number */
#define BOARD_INITPINS_LED_BLUE_GPIO_PIN_MASK (1U << 10U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LED_BLUE_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LED_BLUE_PIN 10U /*!< PORT pin number */
#define BOARD_INITPINS_LED_BLUE_PIN_MASK (1U << 10U) /*!< PORT pin mask */
/* GPIO_AD_B0_15 (coord L10), LCDIF_BL */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_BL_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_BL_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LCDIF_BL_CHANNEL 15U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LCDIF_BL_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN 15U /*!< GPIO pin number */
#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LCDIF_BL_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LCDIF_BL_PIN 15U /*!< PORT pin number */
#define BOARD_INITPINS_LCDIF_BL_PIN_MASK (1U << 15U) /*!< PORT pin mask */
/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
/* Routed pin properties */
#define BOARD_INITPINS_CSI_PIXCLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_CSI_PIXCLK_SIGNAL enet_mdc /*!< Signal name */
/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
/* Routed pin properties */
#define BOARD_INITPINS_BACKLIGHT_CTL_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_BACKLIGHT_CTL_SIGNAL enet_mdio /*!< Signal name */
/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TX_CLK_SIGNAL enet_tx_clk /*!< Signal name */
/* GPIO_B1_07 (coord B12), ENET_TXD0 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_08 (coord A12), ENET_TXD1 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_11 (coord C13), ENET_RXER */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */
/* GPIO_B1_09 (coord A13), ENET_TXEN */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */
/* GPIO_B1_04 (coord E12), ENET_RXD0 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_05 (coord D12), ENET_RXD1 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */
/* GPIO_B1_14 (coord C14), SD0_VSELECT */
/* Routed pin properties */
#define BOARD_INITPINS_SD0_VSELECT_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD0_VSELECT_SIGNAL usdhc_vselect /*!< Signal name */
/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */
/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */
/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_AD_B0_03 (coord G11), USB_OTG1_OC/J24[1] */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_CD_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_CD_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_SD1_CD_CHANNEL 3U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_SD1_CD_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_SD1_CD_GPIO_PIN 3U /*!< GPIO pin number */
#define BOARD_INITPINS_SD1_CD_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
#define BOARD_INITPINS_SD1_CD_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_SD1_CD_PIN 3U /*!< PORT pin number */
#define BOARD_INITPINS_SD1_CD_PIN_MASK (1U << 3U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.

508
board/pin_mux.h.bak
View File

@ -1,10 +1,3 @@
/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@ -44,6 +37,507 @@ extern "C" {
*/
void BOARD_InitBootPins(void);
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */
#define BOARD_INITPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_MDC_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_ENET_MDC_SIGNAL semc_rdy /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */
/* GPIO_AD_B0_02 (coord M11), LCDIF_RESET */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_RESET_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_RESET_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LCDIF_RESET_CHANNEL 2U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LCDIF_RESET_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN 2U /*!< GPIO pin number */
#define BOARD_INITPINS_LCDIF_RESET_GPIO_PIN_MASK (1U << 2U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LCDIF_RESET_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LCDIF_RESET_PIN 2U /*!< PORT pin number */
#define BOARD_INITPINS_LCDIF_RESET_PIN_MASK (1U << 2U) /*!< PORT pin mask */
/* GPIO_AD_B0_10 (coord G13), LED_BLUE */
/* Routed pin properties */
#define BOARD_INITPINS_LED_BLUE_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LED_BLUE_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LED_BLUE_CHANNEL 10U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LED_BLUE_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LED_BLUE_GPIO_PIN 10U /*!< GPIO pin number */
#define BOARD_INITPINS_LED_BLUE_GPIO_PIN_MASK (1U << 10U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LED_BLUE_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LED_BLUE_PIN 10U /*!< PORT pin number */
#define BOARD_INITPINS_LED_BLUE_PIN_MASK (1U << 10U) /*!< PORT pin mask */
/* GPIO_AD_B0_15 (coord L10), LCDIF_BL */
/* Routed pin properties */
#define BOARD_INITPINS_LCDIF_BL_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_LCDIF_BL_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_LCDIF_BL_CHANNEL 15U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_LCDIF_BL_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN 15U /*!< GPIO pin number */
#define BOARD_INITPINS_LCDIF_BL_GPIO_PIN_MASK (1U << 15U) /*!< GPIO pin mask */
#define BOARD_INITPINS_LCDIF_BL_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_LCDIF_BL_PIN 15U /*!< PORT pin number */
#define BOARD_INITPINS_LCDIF_BL_PIN_MASK (1U << 15U) /*!< PORT pin mask */
/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
/* Routed pin properties */
#define BOARD_INITPINS_CSI_PIXCLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_CSI_PIXCLK_SIGNAL enet_mdc /*!< Signal name */
/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
/* Routed pin properties */
#define BOARD_INITPINS_BACKLIGHT_CTL_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_BACKLIGHT_CTL_SIGNAL enet_mdio /*!< Signal name */
/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TX_CLK_SIGNAL enet_tx_clk /*!< Signal name */
/* GPIO_B1_07 (coord B12), ENET_TXD0 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_08 (coord A12), ENET_TXD1 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_11 (coord C13), ENET_RXER */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */
/* GPIO_B1_09 (coord A13), ENET_TXEN */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */
/* GPIO_B1_04 (coord E12), ENET_RXD0 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_05 (coord D12), ENET_RXD1 */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
/* Routed pin properties */
#define BOARD_INITPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */
/* GPIO_B1_14 (coord C14), SD0_VSELECT */
/* Routed pin properties */
#define BOARD_INITPINS_SD0_VSELECT_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD0_VSELECT_SIGNAL usdhc_vselect /*!< Signal name */
/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */
/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */
/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
/* Routed pin properties */
#define BOARD_INITPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */
/*!
* @brief Configures pin routing and optionally pin electrical features.

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#!/bin/sh
if [ ! -d "build" ]; then mkdir build; fi
cd build
TARGETS=(
"debug"
"release"
"sdram_debug"
"sdram_release"
"flexspi_nor_debug"
"flexspi_nor_release"
)
for TARGET in "${TARGETS[@]}" ; do
if [ -d "${TARGET}" ]; then rm -rf ${TARGET}; fi
mkdir ${TARGET} && cd ${TARGET}
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=${TARGET} ../..
make -j
cd ..
done

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#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
make -j 2>&1 | tee build_log.txt

7
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#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
make -j 2>&1 | tee build_log.txt

7
build_flexspi_nor_release.sh
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@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
make -j 2>&1 | tee build_log.txt

7
build_release.sh
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#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
make -j 2>&1 | tee build_log.txt

7
build_sdram_debug.sh
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@ -1,7 +0,0 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_debug .
make -j 2>&1 | tee build_log.txt

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build_sdram_release.sh
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#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=sdram_release .
make -j 2>&1 | tee build_log.txt

3
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#!/bin/sh
rm -rf debug release sdram_debug sdram_release flexspi_nor_debug flexspi_nor_release CMakeFiles
rm -rf Makefile cmake_install.cmake CMakeCache.txt

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if(NOT COMPONENT_LISTS_MIMXRT1052_INCLUDED)
set(COMPONENT_LISTS_MIMXRT1052_INCLUDED true CACHE BOOL "component_lists component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_component_generic_list.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_common_MIMXRT1052)
endif()

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_OS_ABSTRACTION_H_
#define _FSL_OS_ABSTRACTION_H_
#include "fsl_common.h"
#include "fsl_os_abstraction_config.h"
#include "fsl_component_generic_list.h"
/*!
* @addtogroup osa_adapter
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Type for the Task Priority*/
typedef uint16_t osa_task_priority_t;
/*! @brief Type for a task handler */
typedef void *osa_task_handle_t;
/*! @brief Type for the parameter to be passed to the task at its creation */
typedef void *osa_task_param_t;
/*! @brief Type for task pointer. Task prototype declaration */
typedef void (*osa_task_ptr_t)(osa_task_param_t task_param);
/*! @brief Type for the semaphore handler */
typedef void *osa_semaphore_handle_t;
/*! @brief Type for the mutex handler */
typedef void *osa_mutex_handle_t;
/*! @brief Type for the event handler */
typedef void *osa_event_handle_t;
/*! @brief Type for an event flags group, bit 32 is reserved. */
typedef uint32_t osa_event_flags_t;
/*! @brief Message definition. */
typedef void *osa_msg_handle_t;
/*! @brief Type for the message queue handler */
typedef void *osa_msgq_handle_t;
/*! @brief Type for the Timer handler */
typedef void *osa_timer_handle_t;
/*! @brief Type for the Timer callback function pointer. */
typedef void (*osa_timer_fct_ptr_t)(void const *argument);
/*! @brief Thread Definition structure contains startup information of a thread.*/
typedef struct osa_task_def_tag
{
osa_task_ptr_t pthread; /*!< start address of thread function*/
uint32_t tpriority; /*!< initial thread priority*/
uint32_t instances; /*!< maximum number of instances of that thread function*/
uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/
uint32_t *tstack; /*!< stack pointer*/
void *tlink; /*!< link pointer*/
uint8_t *tname; /*!< name pointer*/
uint8_t useFloat; /*!< is use float*/
} osa_task_def_t;
/*! @brief Thread Link Definition structure .*/
typedef struct osa_thread_link_tag
{
uint8_t link[12]; /*!< link*/
osa_task_handle_t osThreadId; /*!< thread id*/
osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/
uint32_t *osThreadStackHandle; /*!< pointer of thread stack handle*/
} osa_thread_link_t, *osa_thread_link_handle_t;
/*! @brief Definition structure contains timer parameters.*/
typedef struct osa_time_def_tag
{
osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */
void *argument; /* < argument of a timer function */
} osa_time_def_t;
/*! @brief Type for the timer definition*/
typedef enum _osa_timer
{
KOSA_TimerOnce = 0, /*!< one-shot timer*/
KOSA_TimerPeriodic = 1 /*!< repeating timer*/
} osa_timer_t;
/*! @brief Defines the return status of OSA's functions */
typedef enum _osa_status
{
KOSA_StatusSuccess = kStatus_Success, /*!< Success */
KOSA_StatusError = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */
KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */
KOSA_StatusIdle = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready
and timeout still not occur */
} osa_status_t;
#ifdef USE_RTOS
#undef USE_RTOS
#endif
#if defined(FSL_RTOS_MQX)
#define USE_RTOS (1)
#elif defined(FSL_RTOS_FREE_RTOS)
#define USE_RTOS (1)
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
#define OSA_TASK_HANDLE_SIZE (12U)
#else
#define OSA_TASK_HANDLE_SIZE (16U)
#endif
#define OSA_EVENT_HANDLE_SIZE (8U)
#define OSA_SEM_HANDLE_SIZE (4U)
#define OSA_MUTEX_HANDLE_SIZE (4U)
#define OSA_MSGQ_HANDLE_SIZE (4U)
#define OSA_MSG_HANDLE_SIZE (0U)
#elif defined(FSL_RTOS_UCOSII)
#define USE_RTOS (1)
#elif defined(FSL_RTOS_UCOSIII)
#define USE_RTOS (1)
#else
#define USE_RTOS (0)
#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
#define OSA_TASK_HANDLE_SIZE (24U)
#else
#define OSA_TASK_HANDLE_SIZE (28U)
#endif
#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
#define OSA_EVENT_HANDLE_SIZE (20U)
#else
#define OSA_EVENT_HANDLE_SIZE (16U)
#endif /* FSL_OSA_TASK_ENABLE */
#define OSA_SEM_HANDLE_SIZE (12U)
#define OSA_MUTEX_HANDLE_SIZE (12U)
#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
#define OSA_MSGQ_HANDLE_SIZE (32U)
#else
#define OSA_MSGQ_HANDLE_SIZE (28U)
#endif /* FSL_OSA_TASK_ENABLE */
#define OSA_MSG_HANDLE_SIZE (4U)
#endif
/*! @brief Priority setting for OSA. */
#ifndef OSA_PRIORITY_IDLE
#define OSA_PRIORITY_IDLE (6)
#endif
#ifndef OSA_PRIORITY_LOW
#define OSA_PRIORITY_LOW (5)
#endif
#ifndef OSA_PRIORITY_BELOW_NORMAL
#define OSA_PRIORITY_BELOW_NORMAL (4)
#endif
#ifndef OSA_PRIORITY_NORMAL
#define OSA_PRIORITY_NORMAL (3)
#endif
#ifndef OSA_PRIORITY_ABOVE_NORMAL
#define OSA_PRIORITY_ABOVE_NORMAL (2)
#endif
#ifndef OSA_PRIORITY_HIGH
#define OSA_PRIORITY_HIGH (1)
#endif
#ifndef OSA_PRIORITY_REAL_TIME
#define OSA_PRIORITY_REAL_TIME (0)
#endif
#ifndef OSA_TASK_PRIORITY_MAX
#define OSA_TASK_PRIORITY_MAX (0)
#endif
#ifndef OSA_TASK_PRIORITY_MIN
#define OSA_TASK_PRIORITY_MIN (15)
#endif
#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t))
/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
#define osaWaitForever_c ((uint32_t)(-1))
#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF))
#define osThreadStackArray(name) osThread_##name##_stack
#define osThreadStackDef(name, stacksize, instances) \
const uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)];
/* ==== Thread Management ==== */
/* Create a Thread Definition with function, priority, and stack requirements.
* \param name name of the thread function.
* \param priority initial priority of the thread function.
* \param instances number of possible thread instances.
* \param stackSz stack size (in bytes) requirements for the thread function.
* \param useFloat
*/
#if defined(FSL_RTOS_MQX)
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osa_thread_link_t osThreadLink_##name[instances] = {0}; \
osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
(name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
(uint8_t *)#name, (useFloat)}
#elif defined(FSL_RTOS_UCOSII)
#if gTaskMultipleInstancesManagement_c
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osa_thread_link_t osThreadLink_##name[instances] = {0}; \
osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
(name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
(uint8_t *)#name, (useFloat)}
#else
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
(name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)}
#endif
#else
#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
const osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \
NULL, NULL, (uint8_t *)#name, (useFloat)}
#endif
/* Access a Thread defintion.
* \param name name of the thread definition object.
*/
#define OSA_TASK(name) (const osa_task_def_t *)&os_thread_def_##name
#define OSA_TASK_PROTO(name) externosa_task_def_t os_thread_def_##name
/* ==== Timer Management ====
* Define a Timer object.
* \param name name of the timer object.
* \param function name of the timer call back function.
*/
#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL}
/* Access a Timer definition.
* \param name name of the timer object.
*/
#define OSA_TIMER(name) &os_timer_def_##name
/* ==== Buffer Definition ==== */
/*!
* @brief Defines the semaphore handle
*
* This macro is used to define a 4 byte aligned semaphore handle.
* Then use "(osa_semaphore_handle_t)name" to get the semaphore handle.
*
* The macro should be global and could be optional. You could also define semaphore handle by yourself.
*
* This is an example,
* @code
* OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
* @endcode
*
* @param name The name string of the semaphore handle.
*/
#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \
uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
/*!
* @brief Defines the mutex handle
*
* This macro is used to define a 4 byte aligned mutex handle.
* Then use "(osa_mutex_handle_t)name" to get the mutex handle.
*
* The macro should be global and could be optional. You could also define mutex handle by yourself.
*
* This is an example,
* @code
* OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
* @endcode
*
* @param name The name string of the mutex handle.
*/
#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
/*!
* @brief Defines the event handle
*
* This macro is used to define a 4 byte aligned event handle.
* Then use "(osa_event_handle_t)name" to get the event handle.
*
* The macro should be global and could be optional. You could also define event handle by yourself.
*
* This is an example,
* @code
* OSA_EVENT_HANDLE_DEFINE(eventHandle);
* @endcode
*
* @param name The name string of the event handle.
*/
#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
/*!
* @brief Defines the message queue handle
*
* This macro is used to define a 4 byte aligned message queue handle.
* Then use "(osa_msgq_handle_t)name" to get the message queue handle.
*
* The macro should be global and could be optional. You could also define message queue handle by yourself.
*
* This is an example,
* @code
* OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct));
* @endcode
*
* @param name The name string of the message queue handle.
* @param numberOfMsgs Number of messages.
* @param msgSize Message size.
*
*/
#if defined(FSL_RTOS_FREE_RTOS)
/*< Macro For FREE_RTOS*/
#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
#else
/*< Macro For BARE_MATEL*/
#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
uint32_t name[((OSA_MSGQ_HANDLE_SIZE + numberOfMsgs * msgSize) + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
#endif
/*!
* @brief Defines the TASK handle
*
* This macro is used to define a 4 byte aligned TASK handle.
* Then use "(osa_task_handle_t)name" to get the TASK handle.
*
* The macro should be global and could be optional. You could also define TASK handle by yourself.
*
* This is an example,
* @code
* OSA_TASK_HANDLE_DEFINE(taskHandle);
* @endcode
*
* @param name The name string of the TASK handle.
*/
#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
#if defined(FSL_RTOS_FREE_RTOS)
#include "fsl_os_abstraction_free_rtos.h"
#else
#include "fsl_os_abstraction_bm.h"
#endif
extern const uint8_t gUseRtos_c;
/*
* alloc the temporary memory to store the status
*/
#define OSA_SR_ALLOC() uint32_t osaCurrentSr;
/*
* Enter critical mode
*/
#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr)
/*
* Exit critical mode and retore the previous mode
*/
#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr)
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief Reserves the requested amount of memory in bytes.
*
* The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
*
* @param length Amount of bytes to reserve.
*
* @return Pointer to the reserved memory. NULL if memory can't be allocated.
*/
void *OSA_MemoryAllocate(uint32_t length);
/*!
* @brief Frees the memory previously reserved.
*
* The function is used to free the memory block previously reserved.
*
* @param p Pointer to the start of the memory block previously reserved.
*
*/
void OSA_MemoryFree(void *p);
/*!
* @brief Enter critical with nesting mode.
*
* @param sr Store current status and return to caller.
*/
void OSA_EnterCritical(uint32_t *sr);
/*!
* @brief Exit critical with nesting mode.
*
* @param sr Previous status to restore.
*/
void OSA_ExitCritical(uint32_t sr);
/*!
* @name Task management
* @{
*/
/*!
* @brief Creates a task.
*
* This function is used to create task based on the resources defined
* by the macro OSA_TASK_DEFINE.
*
* Example below shows how to use this API to create the task handle.
* @code
* OSA_TASK_HANDLE_DEFINE(taskHandle);
* OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);
* OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL);
* @endcode
*
* @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle.
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
* You can define the handle in the following two ways:
* #OSA_TASK_HANDLE_DEFINE(taskHandle);
* or
* uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
* @param thread_def pointer to theosa_task_def_t structure which defines the task.
* @param task_param Pointer to be passed to the task when it is created.
* @retval KOSA_StatusSuccess The task is successfully created.
* @retval KOSA_StatusError The task can not be created.
*/
#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle,
const osa_task_def_t *thread_def,
osa_task_param_t task_param);
#endif /* FSL_OSA_TASK_ENABLE */
/*!
* @brief Gets the handler of active task.
*
* @return Handler to current active task.
*/
#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
osa_task_handle_t OSA_TaskGetCurrentHandle(void);
#endif /* FSL_OSA_TASK_ENABLE */
/*!
* @brief Puts the active task to the end of scheduler's queue.
*
* When a task calls this function, it gives up the CPU and puts itself to the
* end of a task ready list.
*
* @retval KOSA_StatusSuccess The function is called successfully.
* @retval KOSA_StatusError Error occurs with this function.
*/
#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
osa_status_t OSA_TaskYield(void);
#endif /* FSL_OSA_TASK_ENABLE */
/*!
* @brief Gets the priority of a task.
*
* @param taskHandle The handler of the task whose priority is received.
*
* @return Task's priority.
*/
#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle);
#endif /* FSL_OSA_TASK_ENABLE */
/*!
* @brief Sets the priority of a task.
*
* @param taskHandle The handler of the task whose priority is set.
* @param taskPriority The priority to set.
*
* @retval KOSA_StatusSuccess Task's priority is set successfully.
* @retval KOSA_StatusError Task's priority can not be set.
*/
#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority);
#endif /* FSL_OSA_TASK_ENABLE */
/*!
* @brief Destroys a previously created task.
*
* @param taskHandle The handler of the task to destroy.
*
* @retval KOSA_StatusSuccess The task was successfully destroyed.
* @retval KOSA_StatusError Task destruction failed or invalid parameter.
*/
#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle);
#endif /* FSL_OSA_TASK_ENABLE */
/*!
* @brief Creates a semaphore with a given value.
*
* This function creates a semaphore and sets the value to the parameter
* initValue.
*
* Example below shows how to use this API to create the semaphore handle.
* @code
* OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
* OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff);
* @endcode
*
* @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
* You can define the handle in the following two ways:
* #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
* or
* uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
* @param initValue Initial value the semaphore will be set to.
*
* @retval KOSA_StatusSuccess the new semaphore if the semaphore is created successfully.
* @retval KOSA_StatusError if the semaphore can not be created.
*/
osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue);
/*!
* @brief Destroys a previously created semaphore.
*
* @param semaphoreHandle The semaphore handle.
* The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer,
* and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used.
*
* @retval KOSA_StatusSuccess The semaphore is successfully destroyed.
* @retval KOSA_StatusError The semaphore can not be destroyed.
*/
osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle);
/*!
* @brief Pending a semaphore with timeout.
*
* This function checks the semaphore's counting value. If it is positive,
* decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used
* to wait.
*
* @param semaphoreHandle The semaphore handle.
* @param millisec The maximum number of milliseconds to wait if semaphore is not
* positive. Pass osaWaitForever_c to wait indefinitely, pass 0
* will return KOSA_StatusTimeout immediately.
*
* @retval KOSA_StatusSuccess The semaphore is received.
* @retval KOSA_StatusTimeout The semaphore is not received within the specified 'timeout'.
* @retval KOSA_StatusError An incorrect parameter was passed.
*/
osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec);
/*!
* @brief Signals for someone waiting on the semaphore to wake up.
*
* Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
* the semaphore's counting value.
*
* @param semaphoreHandle The semaphore handle to signal.
*
* @retval KOSA_StatusSuccess The semaphore is successfully signaled.
* @retval KOSA_StatusError The object can not be signaled or invalid parameter.
*
*/
osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle);
/*!
* @brief Create an unlocked mutex.
*
* This function creates a non-recursive mutex and sets it to unlocked status.
*
* Example below shows how to use this API to create the mutex handle.
* @code
* OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
* OSA_MutexCreate((osa_mutex_handle_t)mutexHandle);
* @endcode
*
* @param mutexHandle Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller.
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
* You can define the handle in the following two ways:
* #OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
* or
* uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
* @retval KOSA_StatusSuccess the new mutex if the mutex is created successfully.
* @retval KOSA_StatusError if the mutex can not be created.
*/
osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle);
/*!
* @brief Waits for a mutex and locks it.
*
* This function checks the mutex's status. If it is unlocked, locks it and returns the
* KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock.
*
* @param mutexHandle The mutex handle.
* @param millisec The maximum number of milliseconds to wait for the mutex.
* If the mutex is locked, Pass the value osaWaitForever_c will
* wait indefinitely, pass 0 will return KOSA_StatusTimeout
* immediately.
*
* @retval KOSA_StatusSuccess The mutex is locked successfully.
* @retval KOSA_StatusTimeout Timeout occurred.
* @retval KOSA_StatusError Incorrect parameter was passed.
*
* @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
*/
osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec);
/*!
* @brief Unlocks a previously locked mutex.
*
* @param mutexHandle The mutex handle.
*
* @retval KOSA_StatusSuccess The mutex is successfully unlocked.
* @retval KOSA_StatusError The mutex can not be unlocked or invalid parameter.
*/
osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle);
/*!
* @brief Destroys a previously created mutex.
*
* @param mutexHandle The mutex handle.
*
* @retval KOSA_StatusSuccess The mutex is successfully destroyed.
* @retval KOSA_StatusError The mutex can not be destroyed.
*
*/
osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle);
/*!
* @brief Initializes an event object with all flags cleared.
*
* This function creates an event object and set its clear mode. If autoClear
* is 1, when a task gets the event flags, these flags will be
* cleared automatically. Otherwise these flags must
* be cleared manually.
*
* Example below shows how to use this API to create the event handle.
* @code
* OSA_EVENT_HANDLE_DEFINE(eventHandle);
* OSA_EventCreate((osa_event_handle_t)eventHandle, 0);
* @endcode
*
* @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller.
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
* You can define the handle in the following two ways:
* #OSA_EVENT_HANDLE_DEFINE(eventHandle);
* or
* uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
* @param autoClear 1 The event is auto-clear.
* 0 The event manual-clear
* @retval KOSA_StatusSuccess the new event if the event is created successfully.
* @retval KOSA_StatusError if the event can not be created.
*/
osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear);
/*!
* @brief Sets one or more event flags.
*
* Sets specified flags of an event object.
*
* @param eventHandle The event handle.
* @param flagsToSet Flags to be set.
*
* @retval KOSA_StatusSuccess The flags were successfully set.
* @retval KOSA_StatusError An incorrect parameter was passed.
*/
osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet);
/*!
* @brief Clears one or more flags.
*
* Clears specified flags of an event object.
*
* @param eventHandle The event handle.
* @param flagsToClear Flags to be clear.
*
* @retval KOSA_StatusSuccess The flags were successfully cleared.
* @retval KOSA_StatusError An incorrect parameter was passed.
*/
osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear);
/*!
* @brief Get event's flags.
*
* Get specified flags of an event object.
*
* @param eventHandle The event handle.
* The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer,
* and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used.
* @param flagsMask The flags user want to get are specified by this parameter.
* @param pFlagsOfEvent The event flags are obtained by this parameter.
*
* @retval KOSA_StatusSuccess The event flags were successfully got.
* @retval KOSA_StatusError An incorrect parameter was passed.
*/
osa_status_t OSA_EventGet(osa_event_handle_t eventHandle,
osa_event_flags_t flagsMask,
osa_event_flags_t *pFlagsOfEvent);
/*!
* @brief Waits for specified event flags to be set.
*
* This function waits for a combination of flags to be set in an event object.
* Applications can wait for any/all bits to be set. Also this function could
* obtain the flags who wakeup the waiting task.
*
* @param eventHandle The event handle.
* @param flagsToWait Flags that to wait.
* @param waitAll Wait all flags or any flag to be set.
* @param millisec The maximum number of milliseconds to wait for the event.
* If the wait condition is not met, pass osaWaitForever_c will
* wait indefinitely, pass 0 will return KOSA_StatusTimeout
* immediately.
* @param pSetFlags Flags that wakeup the waiting task are obtained by this parameter.
*
* @retval KOSA_StatusSuccess The wait condition met and function returns successfully.
* @retval KOSA_StatusTimeout Has not met wait condition within timeout.
* @retval KOSA_StatusError An incorrect parameter was passed.
*
* @note Please pay attention to the flags bit width, FreeRTOS uses the most
* significant 8 bis as control bits, so do not wait these bits while using
* FreeRTOS.
*
*/
osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
osa_event_flags_t flagsToWait,
uint8_t waitAll,
uint32_t millisec,
osa_event_flags_t *pSetFlags);
/*!
* @brief Destroys a previously created event object.
*
* @param eventHandle The event handle.
*
* @retval KOSA_StatusSuccess The event is successfully destroyed.
* @retval KOSA_StatusError Event destruction failed.
*/
osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle);
/*!
* @brief Initializes a message queue.
*
* This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
*
* Example below shows how to use this API to create the massage queue handle.
* @code
* OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
* OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg));
* @endcode
*
* @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel
* and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle.
* The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
* You can define the handle in the following two ways:
* #OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
* or
* For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
* For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
* @param msgNo :number of messages the message queue should accommodate.
* @param msgSize :size of a single message structure.
*
* @retval KOSA_StatusSuccess Message queue successfully Create.
* @retval KOSA_StatusError Message queue create failure.
*/
osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize);
/*!
* @brief Puts a message at the end of the queue.
*
* This function puts a message to the end of the message queue. If the queue
* is full, this function returns the KOSA_StatusError;
*
* @param msgqHandle Message Queue handler.
* @param pMessage Pointer to the message to be put into the queue.
*
* @retval KOSA_StatusSuccess Message successfully put into the queue.
* @retval KOSA_StatusError The queue was full or an invalid parameter was passed.
*/
osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage);
/*!
* @brief Reads and remove a message at the head of the queue.
*
* This function gets a message from the head of the message queue. If the
* queue is empty, timeout is used to wait.
*
* @param msgqHandle Message Queue handler.
* @param pMessage Pointer to a memory to save the message.
* @param millisec The number of milliseconds to wait for a message. If the
* queue is empty, pass osaWaitForever_c will wait indefinitely,
* pass 0 will return KOSA_StatusTimeout immediately.
*
* @retval KOSA_StatusSuccess Message successfully obtained from the queue.
* @retval KOSA_StatusTimeout The queue remains empty after timeout.
* @retval KOSA_StatusError Invalid parameter.
*/
osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec);
/*!
* @brief Get the available message
*
* This function is used to get the available message.
*
* @param msgqHandle Message Queue handler.
*
* @return Available message count
*/
int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle);
/*!
* @brief Destroys a previously created queue.
*
* @param msgqHandle Message Queue handler.
*
* @retval KOSA_StatusSuccess The queue was successfully destroyed.
* @retval KOSA_StatusError Message queue destruction failed.
*/
osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle);
/*!
* @brief Enable all interrupts.
*/
void OSA_InterruptEnable(void);
/*!
* @brief Disable all interrupts.
*/
void OSA_InterruptDisable(void);
/*!
* @brief Enable all interrupts using PRIMASK.
*/
void OSA_EnableIRQGlobal(void);
/*!
* @brief Disable all interrupts using PRIMASK.
*/
void OSA_DisableIRQGlobal(void);
/*!
* @brief Delays execution for a number of milliseconds.
*
* @param millisec The time in milliseconds to wait.
*/
void OSA_TimeDelay(uint32_t millisec);
/*!
* @brief This function gets current time in milliseconds.
*
* @retval current time in milliseconds
*/
uint32_t OSA_TimeGetMsec(void);
/*!
* @brief Installs the interrupt handler.
*
* @param IRQNumber IRQ number of the interrupt.
* @param handler The interrupt handler to install.
*/
void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
/*! @}*/
#ifdef __cplusplus
}
#endif
/*! @}*/
#endif

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/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if !defined(__FSL_OS_ABSTRACTION_BM_H__)
#define __FSL_OS_ABSTRACTION_BM_H__
/*!
* @addtogroup os_abstraction_bm
* @{
*/
/*******************************************************************************
* Declarations
******************************************************************************/
/*! @brief Bare Metal does not use timer. */
#ifndef FSL_OSA_BM_TIMER_NONE
#define FSL_OSA_BM_TIMER_NONE 0U
#endif
/*! @brief Bare Metal uses SYSTICK as timer. */
#ifndef FSL_OSA_BM_TIMER_SYSTICK
#define FSL_OSA_BM_TIMER_SYSTICK 1U
#endif
/*! @brief Configure what timer is used in Bare Metal. */
#ifndef FSL_OSA_BM_TIMER_CONFIG
#define FSL_OSA_BM_TIMER_CONFIG FSL_OSA_BM_TIMER_NONE
#endif
/*! @brief Type for task parameter */
typedef void *task_param_t;
/*! @brief Type for an event flags group, bit 32 is reserved */
typedef uint32_t event_flags_t;
/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
#define OSA_WAIT_FOREVER 0xFFFFFFFFU
/*! @brief How many tasks can the bare metal support. */
#ifndef TASK_MAX_NUM
#define TASK_MAX_NUM 7
#endif
/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
/*! @brief The default interrupt handler installed in vector table. */
#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
/*! @brief The default interrupt handler installed in vector table. */
extern void DefaultISR(void);
/*!
* @name Thread management
* @{
*/
/*!
* @brief To provide unified priority for upper layer, OSA layer makes conversation.
*/
#define PRIORITY_OSA_TO_RTOS(osa_prio) (osa_prio)
#define PRIORITY_RTOS_TO_OSA(rtos_prio) (rtos_prio)
/*! @}*/
/*! @}*/
#endif /* __FSL_OS_ABSTRACTION_BM_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
#define _FSL_OS_ABSTRACTION_CONFIG_H_
#ifndef gMainThreadStackSize_c
#define gMainThreadStackSize_c 1024
#endif
#ifndef gMainThreadPriority_c
#define gMainThreadPriority_c 7
#endif
#ifndef gTaskMultipleInstancesManagement_c
#define gTaskMultipleInstancesManagement_c 0
#endif
/*! @brief Definition to determine whether enable OSA's TASK module. */
#ifndef OSA_USED
#ifndef FSL_OSA_TASK_ENABLE
#define FSL_OSA_TASK_ENABLE 0U
#endif
#else
#if defined(FSL_OSA_TASK_ENABLE)
#undef FSL_OSA_TASK_ENABLE
#endif
#define FSL_OSA_TASK_ENABLE 1U
#endif /* OSA_USED */
#ifndef FSL_OSA_MAIN_FUNC_ENABLE
#define FSL_OSA_MAIN_FUNC_ENABLE 1U
#endif
#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */

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/*! *********************************************************************************
* Copyright (c) 2013-2014, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* ile
*
* SPDX-License-Identifier: BSD-3-Clause
********************************************************************************** */
#if !defined(__FSL_OS_ABSTRACTION_FREERTOS_H__)
#define __FSL_OS_ABSTRACTION_FREERTOS_H__
#if defined(__IAR_SYSTEMS_ICC__)
/**
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
*/
/* http://supp.iar.com/Support/?note=24725 */
#define MISRAC_DISABLE \
_Pragma( \
"diag_suppress= \
Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
Pm155")
#define MISRAC_ENABLE \
_Pragma( \
"diag_default= \
Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
Pm155")
#else
/* Empty MISRA C macros for other toolchains. */
#define MISRAC_DISABLE
#define MISRAC_ENABLE
#endif
MISRAC_DISABLE
#include "FreeRTOS.h"
#include "semphr.h"
#include "event_groups.h"
MISRAC_ENABLE
/*!
* @addtogroup os_abstraction_free_rtos
* @{
*/
/*******************************************************************************
* Declarations
******************************************************************************/
/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
typedef TaskHandle_t task_handler_t;
/*! @brief Type for a task stack.*/
typedef portSTACK_TYPE task_stack_t;
/*! @brief Type for task parameter */
typedef void *task_param_t;
/*! @brief Type for an event flags object.*/
typedef EventBits_t event_flags_t;
/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
#define OSA_WAIT_FOREVER 0xFFFFFFFFU
/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
/*! @brief The default interrupt handler installed in vector table. */
#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
extern void DefaultISR(void);
/*!
* @name Thread management
* @{
*/
/*!
* @brief To provide unified task piority for upper layer, OSA layer makes conversion.
*/
#define PRIORITY_OSA_TO_RTOS(osa_prio) ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U)
#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U)
/* @}*/
/*!
* @name Message queues
* @{
*/
/*!
* @brief This macro statically reserves the memory required for the queue.
*
* @param name Identifier for the memory region.
* @param number Number of elements in the queue.
* @param size Size of every elements in words.
*/
#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL
/* @}*/
/*! @}*/
/*! @}*/
/*! @}*/
#endif /* __FSL_OS_ABSTRACTION_FREERTOS_H__ */

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_phyksz8081.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the PHY KSZ8081 vendor defined registers. */
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
/*! @brief Defines the PHY KSZ8081 ID number. */
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1 */
/*! @brief Defines the mask flag of operation mode in control registers */
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the timeout macro. */
#define PHY_READID_TIMEOUT_COUNT 1000U
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
const phy_operations_t phyksz8081_ops = {.phyInit = PHY_KSZ8081_Init,
.phyWrite = PHY_KSZ8081_Write,
.phyRead = PHY_KSZ8081_Read,
.getAutoNegoStatus = PHY_KSZ8081_GetAutoNegotiationStatus,
.getLinkStatus = PHY_KSZ8081_GetLinkStatus,
.getLinkSpeedDuplex = PHY_KSZ8081_GetLinkSpeedDuplex,
.setLinkSpeedDuplex = PHY_KSZ8081_SetLinkSpeedDuplex,
.enableLoopback = PHY_KSZ8081_EnableLoopback};
/*******************************************************************************
* Code
******************************************************************************/
status_t PHY_KSZ8081_Init(phy_handle_t *handle, const phy_config_t *config)
{
uint32_t counter = PHY_READID_TIMEOUT_COUNT;
status_t result = kStatus_Success;
uint32_t regValue = 0;
/* Init MDIO interface. */
MDIO_Init(handle->mdioHandle);
/* Assign phy address. */
handle->phyAddr = config->phyAddr;
/* Check PHY ID. */
do
{
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, &regValue);
if (result != kStatus_Success)
{
return result;
}
counter--;
} while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
if (counter == 0U)
{
return kStatus_Fail;
}
/* Reset PHY. */
result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (result == kStatus_Success)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, &regValue);
if (result != kStatus_Success)
{
return result;
}
result =
MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, (regValue | PHY_CTL2_REFCLK_SELECT_MASK));
if (result != kStatus_Success)
{
return result;
}
#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
if (config->autoNeg)
{
/* Set the auto-negotiation then start it. */
result =
MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK));
if (result == kStatus_Success)
{
result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
}
}
else
{
/* This PHY only supports 10/100M speed. */
assert(config->speed <= kPHY_Speed100M);
/* Disable isolate mode */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
if (result != kStatus_Success)
{
return result;
}
regValue &= ~PHY_BCTL_ISOLATE_MASK;
result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
if (result != kStatus_Success)
{
return result;
}
/* Disable the auto-negotiation and set user-defined speed/duplex configuration. */
result = PHY_KSZ8081_SetLinkSpeedDuplex(handle, config->speed, config->duplex);
}
}
return result;
}
status_t PHY_KSZ8081_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data)
{
return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data);
}
status_t PHY_KSZ8081_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr)
{
return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr);
}
status_t PHY_KSZ8081_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status)
{
assert(status);
status_t result;
uint32_t regValue;
*status = false;
/* Check auto negotiation complete. */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, &regValue);
if (result == kStatus_Success)
{
if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U)
{
*status = true;
}
}
return result;
}
status_t PHY_KSZ8081_GetLinkStatus(phy_handle_t *handle, bool *status)
{
assert(status);
status_t result;
uint32_t regValue;
/* Read the basic status register. */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, &regValue);
if (result == kStatus_Success)
{
if ((PHY_BSTATUS_LINKSTATUS_MASK & regValue) != 0U)
{
/* Link up. */
*status = true;
}
else
{
/* Link down. */
*status = false;
}
}
return result;
}
status_t PHY_KSZ8081_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex)
{
assert(!((speed == NULL) && (duplex == NULL)));
status_t result;
uint32_t regValue;
uint32_t flag;
/* Read the control register. */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL1_REG, &regValue);
if (result == kStatus_Success)
{
if (speed != NULL)
{
flag = regValue & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_100HALFDUPLEX_MASK == flag) || (PHY_CTL1_100FULLDUPLEX_MASK == flag))
{
*speed = kPHY_Speed100M;
}
else
{
*speed = kPHY_Speed10M;
}
}
if (duplex != NULL)
{
flag = regValue & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_10FULLDUPLEX_MASK == flag) || (PHY_CTL1_100FULLDUPLEX_MASK == flag))
{
*duplex = kPHY_FullDuplex;
}
else
{
*duplex = kPHY_HalfDuplex;
}
}
}
return result;
}
status_t PHY_KSZ8081_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex)
{
/* This PHY only supports 10/100M speed. */
assert(speed <= kPHY_Speed100M);
status_t result;
uint32_t regValue;
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
if (result == kStatus_Success)
{
/* Disable the auto-negotiation and set according to user-defined configuration. */
regValue &= ~PHY_BCTL_AUTONEG_MASK;
if (speed == kPHY_Speed100M)
{
regValue |= PHY_BCTL_SPEED0_MASK;
}
else
{
regValue &= ~PHY_BCTL_SPEED0_MASK;
}
if (duplex == kPHY_FullDuplex)
{
regValue |= PHY_BCTL_DUPLEX_MASK;
}
else
{
regValue &= ~PHY_BCTL_DUPLEX_MASK;
}
result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
}
return result;
}
status_t PHY_KSZ8081_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable)
{
/* This PHY only supports local/remote loopback and 10/100M speed. */
assert(mode <= kPHY_RemoteLoop);
assert(speed <= kPHY_Speed100M);
status_t result;
uint32_t regValue;
/* Set the loop mode. */
if (enable)
{
if (mode == kPHY_LocalLoop)
{
if (speed == kPHY_Speed100M)
{
regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
else
{
regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
}
else
{
/* Remote loopback only supports 100M full-duplex. */
assert(speed == kPHY_Speed100M);
regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
if (result != kStatus_Success)
{
return result;
}
/* Set the remote loopback bit. */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, &regValue);
if (result == kStatus_Success)
{
return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG,
(regValue | PHY_CTL2_REMOTELOOP_MASK));
}
}
}
else
{
/* Disable the loop mode. */
if (mode == kPHY_LocalLoop)
{
/* First read the current status in control register. */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
if (result == kStatus_Success)
{
regValue &= ~PHY_BCTL_LOOP_MASK;
return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
(regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
}
}
else
{
/* First read the current status in control one register. */
result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG, &regValue);
if (result == kStatus_Success)
{
return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_CONTROL2_REG,
(regValue & ~PHY_CTL2_REMOTELOOP_MASK));
}
}
}
return result;
}

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*****************************************************************************
* PHY KSZ8081 driver change log
*****************************************************************************/
/*!
@page driver_log Driver Change Log
@section phyksz8081 PHYKSZ8081
The current PHYKSZ8081 driver version is 2.0.0.
- 2.0.0
- Initial version.
*/
#ifndef _FSL_PHYKSZ8081_H_
#define _FSL_PHYKSZ8081_H_
#include "fsl_phy.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*! @brief PHY operations structure. */
extern const phy_operations_t phyksz8081_ops;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize PHY.
*
* @param handle PHY device handle.
* @param config Pointer to structure of phy_config_t.
* @retval kStatus_Success PHY initialization succeeds
* @retval kStatus_Fail PHY initialization fails
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_Init(phy_handle_t *handle, const phy_config_t *config);
/*!
* @brief PHY Write function. This function writes data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param handle PHY device handle.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param handle PHY device handle.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr);
/*!
* @brief Gets the PHY auto-negotiation status.
*
* @param handle PHY device handle.
* @param status The auto-negotiation status of the PHY.
* - true the auto-negotiation is over.
* - false the auto-negotiation is on-going or not started.
* @retval kStatus_Success PHY gets status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status);
/*!
* @brief Gets the PHY link status.
*
* @param handle PHY device handle.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY gets link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_GetLinkStatus(phy_handle_t *handle, bool *status);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @brief This function gets the speed and duplex mode of PHY. User can give one of speed
* and duplex address paramter and set the other as NULL if only wants to get one of them.
*
* @param handle PHY device handle.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY gets link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex);
/*!
* @brief Sets the PHY link speed and duplex.
*
* @param handle PHY device handle.
* @param speed Specified PHY link speed.
* @param duplex Specified PHY link duplex.
* @retval kStatus_Success PHY gets status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex);
/*!
* @brief Enables/disables PHY loopback.
*
* @param handle PHY device handle.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* All loopback modes should not be set together, when one loopback mode is set
* another should be disabled.
* @param speed PHY speed for loopback mode.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY loopback success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_KSZ8081_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PHYKSZ8081_H_ */

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_MDIO_H_
#define _FSL_MDIO_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#if defined(MDIO_TIMEOUT_COUNT_NUMBER) && MDIO_TIMEOUT_COUNT_NUMBER
#define MDIO_TIMEOUT_COUNT MDIO_TIMEOUT_COUNT_NUMBER
#endif
/*! @brief Defines the PHY status. */
enum _mdio_status
{
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0), /*!< ENET PHY SMI visit timeout. */
};
typedef struct _mdio_operations mdio_operations_t;
/*! @brief MDIO resource. */
typedef struct _mdio_resource
{
void *base; /*!< ENET Ip register base. */
uint32_t csrClock_Hz; /*!< ENET CSR clock. */
} mdio_resource_t;
/*! @brief MDIO handle. */
typedef struct _mdio_handle
{
mdio_resource_t resource;
const mdio_operations_t *ops;
} mdio_handle_t;
/*! @brief Camera receiver operations. */
struct _mdio_operations
{
void (*mdioInit)(mdio_handle_t *handle); /*!< MDIO interface init. */
status_t (*mdioWrite)(mdio_handle_t *handle,
uint32_t phyAddr,
uint32_t devAddr,
uint32_t data); /*!< MDIO write data. */
status_t (*mdioRead)(mdio_handle_t *handle,
uint32_t phyAddr,
uint32_t devAddr,
uint32_t *dataPtr); /*!< MDIO read data. */
status_t (*mdioWriteExt)(mdio_handle_t *handle,
uint32_t phyAddr,
uint32_t devAddr,
uint32_t data); /*!< MDIO write data. */
status_t (*mdioReadExt)(mdio_handle_t *handle,
uint32_t phyAddr,
uint32_t devAddr,
uint32_t *dataPtr); /*!< MDIO read data. */
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name MDIO Driver
* @{
*/
/*!
* @brief MDIO Write function. This function write data over the SMI to
* the specified MDIO register. This function is called by all MDIO interfaces.
*
* @param handle MDIO device handle.
* @retval kStatus_Success MDIO write success
* @retval kStatus_MDIO_SMIVisitTimeout MDIO SMI visit time out
*/
static inline void MDIO_Init(mdio_handle_t *handle)
{
handle->ops->mdioInit(handle);
}
/*!
* @brief MDIO Write function. This function write data over the SMI to
* the specified MDIO register. This function is called by all MDIO interfaces.
*
* @param handle MDIO device handle.
* @param phyAddr MDIO PHY address handle.
* @param devAddr The PHY device register.
* @param data The data written to the MDIO register.
* @retval kStatus_Success MDIO write success
* @retval kStatus_MDIO_SMIVisitTimeout MDIO SMI visit time out
*/
static inline status_t MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data)
{
return handle->ops->mdioWrite(handle, phyAddr, devAddr, data);
}
/*!
* @brief MDIO Read function. This interface read data over the SMI from the
* specified MDIO register. This function is called by all MDIO interfaces.
*
* @param handle MDIO device handle.
* @param phyAddr MDIO PHY address handle.
* @param devAddr The PHY device register.
* @param dataPtr The address to store the data read from the MDIO register.
* @retval kStatus_Success MDIO read success
* @retval kStatus_MDIO_SMIVisitTimeout MDIO SMI visit time out
*/
static inline status_t MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr)
{
return handle->ops->mdioRead(handle, phyAddr, devAddr, dataPtr);
}
/* @} */
#if defined(__cplusplus)
}
#endif
#endif

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component/phy/fsl_phy.h Normal file
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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_mdio.h"
/*! @note The following PHY registers are the IEEE802.3 standard definition, same register and bit field may
have different names in various PHYs, but the feature they represent should be same or very similar. */
/*! @brief Defines the IEEE802.3 standard PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
#define PHY_AUTONEG_LINKPARTNER_REG 0x05U /*!< The PHY auto negotiation link partner ability register. */
#define PHY_AUTONEG_EXPANSION_REG 0x06U /*!< The PHY auto negotiation expansion register. */
#define PHY_1000BASET_CONTROL_REG 0x09U /*!< The PHY 1000BASE-T control register. */
#define PHY_MMD_ACCESS_CONTROL_REG 0x0DU /*!< The PHY MMD access control register. */
#define PHY_MMD_ACCESS_DATA_REG 0x0EU /*!< The PHY MMD access data register. */
/*! @brief Defines the mask flag in basic control register(Address 0x00). */
#define PHY_BCTL_SPEED1_MASK 0x0040U /*!< The PHY speed bit mask(MSB).*/
#define PHY_BCTL_ISOLATE_MASK 0x0400U /*!< The PHY isolate mask.*/
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED0_MASK 0x2000U /*!< The PHY speed bit mask(LSB). */
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
/*! @brief Defines the mask flag in basic status register(Address 0x01). */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register(Address 0x04). */
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
#define PHY_IEEE802_3_SELECTOR_MASK 0x001U /*!< The message type being sent by Auto-Nego.*/
/*! @brief Defines the mask flag in the 1000BASE-T control register(Address 0x09). */
#define PHY_1000BASET_FULLDUPLEX_MASK 0x200U /*!< The PHY has the 1000M full duplex ability.*/
#define PHY_1000BASET_HALFDUPLEX_MASK 0x100U /*!< The PHY has the 1000M half duplex ability.*/
/*******************************************************************************
* Definitions
******************************************************************************/
typedef struct _phy_handle phy_handle_t;
/*! @brief Defines the PHY link speed. */
typedef enum _phy_speed
{
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
kPHY_Speed100M, /*!< ENET PHY 100M speed. */
kPHY_Speed1000M /*!< ENET PHY 1000M speed. */
} phy_speed_t;
/*! @brief Defines the PHY link duplex. */
typedef enum _phy_duplex
{
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
kPHY_FullDuplex /*!< ENET PHY full duplex. */
} phy_duplex_t;
/*! @brief Defines the PHY loopback mode. */
typedef enum _phy_loop
{
kPHY_LocalLoop = 0U, /*!< ENET PHY local/digital loopback. */
kPHY_RemoteLoop, /*!< ENET PHY remote loopback. */
kPHY_ExternalLoop, /*!< ENET PHY external loopback. */
} phy_loop_t;
/*! @brief Defines the PHY MMD data access mode. */
typedef enum _phy_mmd_access_mode
{
kPHY_MMDAccessNoPostIncrement = (1U << 14), /*!< ENET PHY MMD access data with no address post increment. */
kPHY_MMDAccessRdWrPostIncrement =
(2U << 14), /*!< ENET PHY MMD access data with Read/Write address post increment. */
kPHY_MMDAccessWrPostIncrement = (3U << 14), /*!< ENET PHY MMD access data with Write address post increment. */
} phy_mmd_access_mode_t;
/*! @brief Defines PHY configuration. */
typedef struct _phy_config
{
uint32_t phyAddr; /*!< PHY address. */
phy_speed_t speed; /*!< PHY speed configuration. */
phy_duplex_t duplex; /*!< PHY duplex configuration. */
bool autoNeg; /*!< PHY auto-negotiation, true: enable, false: disable. */
bool enableEEE; /*!< PHY Energy Efficient Ethernet. */
} phy_config_t;
/*! @brief PHY device operations. */
typedef struct _phy_operations
{
status_t (*phyInit)(phy_handle_t *handle, const phy_config_t *config);
status_t (*phyWrite)(phy_handle_t *handle, uint32_t phyReg, uint32_t data);
status_t (*phyRead)(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr);
status_t (*getAutoNegoStatus)(phy_handle_t *handle, bool *status);
status_t (*getLinkStatus)(phy_handle_t *handle, bool *status);
status_t (*getLinkSpeedDuplex)(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex);
status_t (*setLinkSpeedDuplex)(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex);
status_t (*enableLoopback)(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable);
} phy_operations_t;
/*! @brief PHY device handle. */
struct _phy_handle
{
uint32_t phyAddr; /*!< PHY address. */
mdio_handle_t *mdioHandle; /*!< The MDIO handle used by the phy device, it is specified by device. */
const phy_operations_t *ops; /*!< The device related operations. */
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize PHY.
*
* @param handle PHY device handle.
* @param config Pointer to structure of phy_config_t.
* @retval kStatus_Success PHY initialization succeeds
* @retval kStatus_Fail PHY initialization fails
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_Init(phy_handle_t *handle, const phy_config_t *config)
{
return handle->ops->phyInit(handle, config);
}
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param handle PHY device handle.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data)
{
return handle->ops->phyWrite(handle, phyReg, data);
}
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param handle PHY device handle.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr)
{
return handle->ops->phyRead(handle, phyReg, dataPtr);
}
/*!
* @brief Gets the PHY auto-negotiation status.
*
* @param handle PHY device handle.
* @param status The auto-negotiation status of the PHY.
* - true the auto-negotiation is over.
* - false the auto-negotiation is on-going or not started.
* @retval kStatus_Success PHY gets status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status)
{
return handle->ops->getAutoNegoStatus(handle, status);
}
/*!
* @brief Gets the PHY link status.
*
* @param handle PHY device handle.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_GetLinkStatus(phy_handle_t *handle, bool *status)
{
return handle->ops->getLinkStatus(handle, status);
}
/*!
* @brief Gets the PHY link speed and duplex.
*
* @brief This function gets the speed and duplex mode of PHY. User can give one of speed
* and duplex address paramter and set the other as NULL if only wants to get one of them.
*
* @param handle PHY device handle.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex)
{
return handle->ops->getLinkSpeedDuplex(handle, speed, duplex);
}
/*!
* @brief Sets the PHY link speed and duplex.
*
* @param handle PHY device handle.
* @param speed Specified PHY link speed.
* @param duplex Specified PHY link duplex.
* @retval kStatus_Success PHY gets status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex)
{
return handle->ops->setLinkSpeedDuplex(handle, speed, duplex);
}
/*!
* @brief Enable PHY loopcback mode.
*
* @param handle PHY device handle.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* All loopback modes should not be set together, when one loopback mode is set
* another should be disabled.
* @param speed PHY speed for loopback mode.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
static inline status_t PHY_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable)
{
return handle->ops->enableLoopback(handle, mode, speed, enable);
}
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif

133
component/phy/mdio/enet/fsl_enet_mdio.c Normal file
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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_enet_mdio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
static void ENET_MDIO_Init(mdio_handle_t *handle);
static status_t ENET_MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data);
static status_t ENET_MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr);
/*******************************************************************************
* Variables
******************************************************************************/
const mdio_operations_t enet_ops = {.mdioInit = ENET_MDIO_Init,
.mdioWrite = ENET_MDIO_Write,
.mdioRead = ENET_MDIO_Read,
.mdioWriteExt = NULL,
.mdioReadExt = NULL};
/*******************************************************************************
* Code
******************************************************************************/
static void ENET_MDIO_Init(mdio_handle_t *handle)
{
mdio_resource_t *resource = (mdio_resource_t *)&handle->resource;
ENET_Type *base = (ENET_Type *)resource->base;
uint32_t instance = ENET_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
(void)CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI(base, resource->csrClock_Hz, false);
}
static status_t ENET_MDIO_Write(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t data)
{
mdio_resource_t *resource = (mdio_resource_t *)&handle->resource;
ENET_Type *base = (ENET_Type *)resource->base;
status_t result = kStatus_Success;
#ifdef MDIO_TIMEOUT_COUNT
uint32_t counter;
#endif
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI write command. */
ENET_StartSMIWrite(base, phyAddr, devAddr, kENET_MiiWriteValidFrame, data);
/* Wait for SMI complete. */
#ifdef MDIO_TIMEOUT_COUNT
for (counter = MDIO_TIMEOUT_COUNT; counter > 0U; counter--)
{
if (ENET_EIR_MII_MASK == (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
{
break;
}
}
/* Check for timeout. */
if (0U == counter)
{
result = kStatus_PHY_SMIVisitTimeout;
}
#else
while (ENET_EIR_MII_MASK != (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
{
}
#endif
/* Clear SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return result;
}
static status_t ENET_MDIO_Read(mdio_handle_t *handle, uint32_t phyAddr, uint32_t devAddr, uint32_t *dataPtr)
{
assert(dataPtr);
mdio_resource_t *resource = (mdio_resource_t *)&handle->resource;
ENET_Type *base = (ENET_Type *)resource->base;
#ifdef MDIO_TIMEOUT_COUNT
uint32_t counter;
#endif
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI read command operation. */
ENET_StartSMIRead(base, phyAddr, devAddr, kENET_MiiReadValidFrame);
/* Wait for SMI complete. */
#ifdef MDIO_TIMEOUT_COUNT
for (counter = MDIO_TIMEOUT_COUNT; counter > 0U; counter--)
{
if (ENET_EIR_MII_MASK == (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
{
break;
}
}
/* Check for timeout. */
if (0U == counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
#else
while (ENET_EIR_MII_MASK != (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK))
{
}
#endif
/* Get data from SMI register. */
*dataPtr = ENET_ReadSMIData(base);
/* Clear SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}

21
component/phy/mdio/enet/fsl_enet_mdio.h Normal file
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@ -0,0 +1,21 @@
/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ENET_MDIO_H_
#define _FSL_ENET_MDIO_H_
#include "fsl_enet.h"
#include "fsl_mdio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief ENET MDIO operations structure. */
extern const mdio_operations_t enet_ops;
#endif

40
component/serial_manager/component_serial_manager_MIMXRT1052.cmake
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@ -1,40 +0,0 @@
if(NOT COMPONENT_SERIAL_MANAGER_MIMXRT1052_INCLUDED)
set(COMPONENT_SERIAL_MANAGER_MIMXRT1052_INCLUDED true CACHE BOOL "component_serial_manager component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_component_serial_manager.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
#OR Logic component
if(CONFIG_USE_component_serial_manager_uart_MIMXRT1052)
include(component_serial_manager_uart_MIMXRT1052)
endif()
if(CONFIG_USE_component_serial_manager_usb_cdc_MIMXRT1052)
include(component_serial_manager_usb_cdc_MIMXRT1052)
endif()
if(CONFIG_USE_component_serial_manager_virtual_MIMXRT1052)
include(component_serial_manager_virtual_MIMXRT1052)
endif()
if(CONFIG_USE_component_serial_manager_swo_MIMXRT1052)
include(component_serial_manager_swo_MIMXRT1052)
endif()
if(CONFIG_USE_component_serial_manager_rpmsg_MIMXRT1052)
include(component_serial_manager_rpmsg_MIMXRT1052)
endif()
if(NOT (CONFIG_USE_component_serial_manager_uart_MIMXRT1052 OR CONFIG_USE_component_serial_manager_usb_cdc_MIMXRT1052 OR CONFIG_USE_component_serial_manager_virtual_MIMXRT1052 OR CONFIG_USE_component_serial_manager_swo_MIMXRT1052 OR CONFIG_USE_component_serial_manager_rpmsg_MIMXRT1052))
message(WARNING "Since component_serial_manager_uart_MIMXRT1052/component_serial_manager_usb_cdc_MIMXRT1052/component_serial_manager_virtual_MIMXRT1052/component_serial_manager_swo_MIMXRT1052/component_serial_manager_rpmsg_MIMXRT1052 is not included at first or config in config.cmake file, use component_serial_manager_uart_MIMXRT1052 by default.")
include(component_serial_manager_uart_MIMXRT1052)
endif()
include(driver_common_MIMXRT1052)
include(component_lists_MIMXRT1052)
endif()

28
component/serial_manager/component_serial_manager_uart_MIMXRT1052.cmake
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@ -1,28 +0,0 @@
if(NOT COMPONENT_SERIAL_MANAGER_UART_MIMXRT1052_INCLUDED)
set(COMPONENT_SERIAL_MANAGER_UART_MIMXRT1052_INCLUDED true CACHE BOOL "component_serial_manager_uart component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_component_serial_port_uart.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
#OR Logic component
if(CONFIG_USE_driver_lpuart_MIMXRT1052)
include(driver_lpuart_MIMXRT1052)
endif()
if(NOT (CONFIG_USE_driver_lpuart_MIMXRT1052))
message(WARNING "Since driver_lpuart_MIMXRT1052 is not included at first or config in config.cmake file, use driver_uart_MIMXRT1052 by default.")
include(driver_uart_MIMXRT1052)
endif()
include(component_lpuart_adapter_MIMXRT1052)
include(component_serial_manager_MIMXRT1052)
endif()

19
component/uart/component_lpuart_adapter_MIMXRT1052.cmake
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@ -1,19 +0,0 @@
if(NOT COMPONENT_LPUART_ADAPTER_MIMXRT1052_INCLUDED)
set(COMPONENT_LPUART_ADAPTER_MIMXRT1052_INCLUDED true CACHE BOOL "component_lpuart_adapter component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_adapter_lpuart.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_common_MIMXRT1052)
include(driver_lpuart_MIMXRT1052)
endif()

3
config.cmake
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@ -1,3 +0,0 @@
# config to select component, the format is CONFIG_USE_${component}
set(CONFIG_USE_component_serial_manager_uart_MIMXRT1052 true)
set(CONFIG_USE_driver_lpuart_MIMXRT1052 true)

6
device/MIMXRT1052_features.h
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@ -380,11 +380,11 @@
/* IGPIO module features */
/* @brief Has data register set DR_SET. */
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
#define FSL_FEATURE_IGPIO_HAS_DR_SET (0)
/* @brief Has data register clear DR_CLEAR. */
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (0)
/* @brief Has data register toggle DR_TOGGLE. */
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (0)
/* LCDIF module features */

12
device/device_MIMXRT1052_CMSIS_MIMXRT1052.cmake
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@ -1,12 +0,0 @@
if(NOT DEVICE_MIMXRT1052_CMSIS_MIMXRT1052_INCLUDED)
set(DEVICE_MIMXRT1052_CMSIS_MIMXRT1052_INCLUDED true CACHE BOOL "device_MIMXRT1052_CMSIS component is included.")
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(CMSIS_Include_core_cm7_MIMXRT1052)
endif()

17
device/device_MIMXRT1052_system_MIMXRT1052.cmake
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@ -1,17 +0,0 @@
if(NOT DEVICE_MIMXRT1052_SYSTEM_MIMXRT1052_INCLUDED)
set(DEVICE_MIMXRT1052_SYSTEM_MIMXRT1052_INCLUDED true CACHE BOOL "device_MIMXRT1052_system component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/system_MIMXRT1052.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(device_MIMXRT1052_CMSIS_MIMXRT1052)
endif()

46
doc/readme.txt
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@ -1,46 +0,0 @@
Overview
========
The Hello World project is a simple demonstration program that uses the SDK UART drivere in
combination with FreeRTOS. The purpose of this demo is to show how to use the debug console and to
provide a simple project for debugging and further development.
The example application creates one task called hello_task. This task print "Hello world." message
via debug console utility and suspend itself.
Toolchain supported
===================
- IAR embedded Workbench 8.50.9
- Keil MDK 5.33
- GCC ARM Embedded 9.3.1
- MCUXpresso 11.3.0
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
After the board is flashed the Tera Term will print "Hello world" message on terminal.
Example output:
Hello world.

17
drivers/driver_clock_MIMXRT1052.cmake
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@ -1,17 +0,0 @@
if(NOT DRIVER_CLOCK_MIMXRT1052_INCLUDED)
set(DRIVER_CLOCK_MIMXRT1052_INCLUDED true CACHE BOOL "driver_clock component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_common_MIMXRT1052)
endif()

19
drivers/driver_common_MIMXRT1052.cmake
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@ -1,19 +0,0 @@
if(NOT DRIVER_COMMON_MIMXRT1052_INCLUDED)
set(DRIVER_COMMON_MIMXRT1052_INCLUDED true CACHE BOOL "driver_common component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_common.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_clock_MIMXRT1052)
include(device_MIMXRT1052_CMSIS_MIMXRT1052)
endif()

17
drivers/driver_igpio_MIMXRT1052.cmake
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@ -1,17 +0,0 @@
if(NOT DRIVER_IGPIO_MIMXRT1052_INCLUDED)
set(DRIVER_IGPIO_MIMXRT1052_INCLUDED true CACHE BOOL "driver_igpio component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_gpio.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_common_MIMXRT1052)
endif()

12
drivers/driver_iomuxc_MIMXRT1052.cmake
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@ -1,12 +0,0 @@
if(NOT DRIVER_IOMUXC_MIMXRT1052_INCLUDED)
set(DRIVER_IOMUXC_MIMXRT1052_INCLUDED true CACHE BOOL "driver_iomuxc component is included.")
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_common_MIMXRT1052)
endif()

17
drivers/driver_lpuart_MIMXRT1052.cmake
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@ -1,17 +0,0 @@
if(NOT DRIVER_LPUART_MIMXRT1052_INCLUDED)
set(DRIVER_LPUART_MIMXRT1052_INCLUDED true CACHE BOOL "driver_lpuart component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_lpuart.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/
)
include(driver_common_MIMXRT1052)
endif()

602
drivers/fsl_cache.c Normal file
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@ -0,0 +1,602 @@
/*
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cache.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
#endif
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
#define L2CACHE_8WAYS_MASK 0xFFU
#define L2CACHE_16WAYS_MASK 0xFFFFU
#define L2CACHE_SMALLWAYS_NUM 8U
#define L2CACHE_1KBCOVERTOB 1024U
#define L2CACHE_SAMLLWAYS_SIZE 16U
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Set for all ways and waiting for the operation finished.
* This is provided for all the background operations.
*
* @param auxCtlReg The auxiliary control register.
* @param regAddr The register address to be operated.
*/
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
/*!
* @brief Invalidates the Level 2 cache line by physical address.
* This function invalidates a cache line by physcial address.
*
* @param address The physical addderss of the cache.
* The format of the address shall be :
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
* Tag | index | 0
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
* If the input address is not aligned, it will be changed to 32-byte aligned address.
* The n is varies according to the index width.
* @return The actual 32-byte aligned physical address be operated.
*/
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
/*!
* @brief Cleans the Level 2 cache line based on the physical address.
* This function cleans a cache line based on a physcial address.
*
* @param address The physical addderss of the cache.
* The format of the address shall be :
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
* Tag | index | 0
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
* If the input address is not aligned, it will be changed to 32-byte aligned address.
* The n is varies according to the index width.
* @return The actual 32-byte aligned physical address be operated.
*/
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
/*!
* @brief Cleans and invalidates the Level 2 cache line based on the physical address.
* This function cleans and invalidates a cache line based on a physcial address.
*
* @param address The physical addderss of the cache.
* The format of the address shall be :
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
* Tag | index | 0
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
* If the input address is not aligned, it will be changed to 32-byte aligned address.
* The n is varies according to the index width.
* @return The actual 32-byte aligned physical address be operated.
*/
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
/*!
* @brief Gets the number of the Level 2 cache and the way size.
* This function cleans and invalidates a cache line based on a physcial address.
*
* @param num_ways The number of the cache way.
* @param size_way The way size.
*/
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
/*******************************************************************************
* Code
******************************************************************************/
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
{
uint16_t mask = L2CACHE_8WAYS_MASK;
uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
/* Check the ways used at first. */
if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
{
mask = L2CACHE_16WAYS_MASK;
}
/* Set the opeartion for all ways/entries of the cache. */
*(uint32_t *)regAddr = mask;
/* Waiting for until the operation is complete. */
while ((*(volatile uint32_t *)regAddr & mask) && timeout)
{
__ASM("nop");
timeout--;
}
}
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
{
/* Align the address first. */
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
/* Invalidate the cache line by physical address. */
L2CACHEC->REG7_INV_PA = address;
return address;
}
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
{
/* Align the address first. */
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
/* Invalidate the cache line by physical address. */
L2CACHEC->REG7_CLEAN_PA = address;
return address;
}
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
{
/* Align the address first. */
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
/* Clean and invalidate the cache line by physical address. */
L2CACHEC->REG7_CLEAN_INV_PA = address;
return address;
}
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
{
assert(num_ways);
assert(size_way);
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
*num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
if (!size)
{
/* 0 internally mapped to the same size as 1 - 16KB.*/
size += 1;
}
*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
}
/*!
* brief Initializes the level 2 cache controller module.
*
* param config Pointer to configuration structure. See "l2cache_config_t".
*/
void L2CACHE_Init(l2cache_config_t *config)
{
assert(config);
uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
uint8_t count;
uint32_t auxReg = 0;
/*The aux register must be configured when the cachec is disabled
* So disable first if the cache controller is enabled.
*/
if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
{
L2CACHE_Disable();
}
/* Unlock all entries. */
if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
{
waysNum = 0xFFFFU;
}
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
{
L2CACHE_LockdownByWayEnable(count, waysNum, false);
}
/* Set the ways and way-size etc. */
auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
L2CACHEC->REG1_AUX_CONTROL = auxReg;
/* Set the tag/data ram latency. */
if (config->lateConfig)
{
uint32_t data = 0;
/* Tag latency. */
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
L2CACHEC->REG1_TAG_RAM_CONTROL = data;
/* Data latency. */
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
L2CACHEC->REG1_DATA_RAM_CONTROL = data;
}
}
/*!
* brief Gets an available default settings for the cache controller.
*
* This function initializes the cache controller configuration structure with default settings.
* The default values are:
* code
* config->waysNum = kL2CACHE_8ways;
* config->waySize = kL2CACHE_32KbSize;
* config->repacePolicy = kL2CACHE_Roundrobin;
* config->lateConfig = NULL;
* config->istrPrefetchEnable = false;
* config->dataPrefetchEnable = false;
* config->nsLockdownEnable = false;
* config->writeAlloc = kL2CACHE_UseAwcache;
* endcode
* param config Pointer to the configuration structure.
*/
void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
/* Get the default value */
config->wayNum = (l2cache_way_num_t)number;
config->waySize = (l2cache_way_size)size;
config->repacePolicy = kL2CACHE_Roundrobin;
config->lateConfig = NULL;
config->istrPrefetchEnable = false;
config->dataPrefetchEnable = false;
config->nsLockdownEnable = false;
config->writeAlloc = kL2CACHE_UseAwcache;
}
/*!
* brief Enables the level 2 cache controller.
* This function enables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Enable(void)
{
/* Invalidate first. */
L2CACHE_Invalidate();
/* Enable the level 2 cache controller. */
L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
}
/*!
* brief Disables the level 2 cache controller.
* This function disables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Disable(void)
{
/* First CleanInvalidate all enties in the cache. */
L2CACHE_CleanInvalidate();
/* Disable the level 2 cache controller. */
L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
/* DSB - data sync barrier.*/
__DSB();
}
/*!
* brief Invalidates the Level 2 cache.
* This function invalidates all entries in cache.
*
*/
void L2CACHE_Invalidate(void)
{
/* Invalidate all entries in cache. */
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
/* Cache sync. */
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans the level 2 cache controller.
* This function cleans all entries in the level 2 cache controller.
*
*/
void L2CACHE_Clean(void)
{
/* Clean all entries of the cache. */
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
/* Cache sync. */
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans and invalidates the level 2 cache controller.
* This function cleans and invalidates all entries in the level 2 cache controller.
*
*/
void L2CACHE_CleanInvalidate(void)
{
/* Clean all entries of the cache. */
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
/* Cache sync. */
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Invalidates the Level 2 cache lines in the range of two physical addresses.
* This function invalidates all cache lines between two physical addresses.
*
* param address The start address of the memory to be invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte;
/* Invalidate addresses in the range. */
while (address < endAddr)
{
address = L2CACHE_InvalidateLineByAddr(address);
/* Update the size. */
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
}
/* Cache sync. */
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans the Level 2 cache lines in the range of two physical addresses.
* This function cleans all cache lines between two physical addresses.
*
* param address The start address of the memory to be cleaned.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
uint32_t num_ways = 0;
uint32_t size_way = 0;
uint32_t endAddr = address + size_byte;
/* Get the number and size of the cache way. */
L2CACHE_GetWayNumSize(&num_ways, &size_way);
/* Check if the clean size is over the cache size. */
if ((endAddr - address) > num_ways * size_way)
{
L2CACHE_Clean();
return;
}
/* Clean addresses in the range. */
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
{
/* Clean the address in the range. */
address = L2CACHE_CleanLineByAddr(address);
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
}
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
* This function cleans and invalidates all cache lines between two physical addresses.
*
* param address The start address of the memory to be cleaned and invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
uint32_t num_ways = 0;
uint32_t size_way = 0;
uint32_t endAddr = address + size_byte;
/* Get the number and size of the cache way. */
L2CACHE_GetWayNumSize(&num_ways, &size_way);
/* Check if the clean size is over the cache size. */
if ((endAddr - address) > num_ways * size_way)
{
L2CACHE_CleanInvalidate();
return;
}
/* Clean addresses in the range. */
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
{
/* Clean the address in the range. */
address = L2CACHE_CleanInvalidateLineByAddr(address);
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
}
L2CACHEC->REG7_CACHE_SYNC = 0;
}
/*!
* brief Enables or disables to lock down the data and instruction by way.
* This function locks down the cached instruction/data by way and prevent the adresses from
* being allocated and prevent dara from being evicted out of the level 2 cache.
* But the normal cache maintenance operations that invalidate, clean or clean
* and validate cache contents affect the locked-down cache lines as normal.
*
* param masterId The master id, range from 0 ~ 7.
* param mask The ways to be enabled or disabled to lockdown.
* each bit in value is related to each way of the cache. for example:
* value: bit 0 ------ way 0.
* value: bit 1 ------ way 1.
* --------------------------
* value: bit 15 ------ way 15.
* Note: please make sure the value setting is align with your supported ways.
* param enable True enable the lockdown, false to disable the lockdown.
*/
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
{
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
assert(mask < (1U << num_ways));
assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
if (enable)
{
/* Data lockdown. */
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
/* Instruction lockdown. */
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
}
else
{
/* Data lockdown. */
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
/* Instruction lockdown. */
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
}
}
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*!
* brief Invalidate cortex-m7 L1 instruction cache by range.
*
* param address The start address of the memory to be invalidated.
* param size_byte The memory size.
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 I-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t addr = address & ~((uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1U);
uint32_t align_len = address - addr;
int32_t size = (int32_t)size_byte + (int32_t)align_len;
__DSB();
while (size > 0)
{
SCB->ICIMVAU = addr;
addr += (uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
size -= (int32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
}
__DSB();
__ISB();
#endif
}
/*!
* brief Invalidates all instruction caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_InvalidateByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
L1CACHE_InvalidateICacheByRange(address, size_byte);
}
/*!
* brief Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_InvalidateByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
L1CACHE_InvalidateDCacheByRange(address, size_byte);
}
/*!
* brief Cleans all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be cleaned.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanDCacheByRange(address, size_byte);
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_CleanByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
}
/*!
* brief Cleans and Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* param address The physical address.
* param size_byte size of the memory to be cleaned and invalidated.
* note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
L2CACHE_CleanInvalidateByRange(address, size_byte);
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
}

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/*
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_H_
#define _FSL_CACHE_H_
#include "fsl_common.h"
/*!
* @addtogroup cache
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief cache driver version 2.0.3. */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
#endif
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
* Definitions
******************************************************************************/
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
/*! @brief Number of level 2 cache controller ways. */
typedef enum _l2cache_way_num
{
kL2CACHE_8ways = 0, /*!< 8 ways. */
#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
kL2CACHE_16ways /*!< 16 ways. */
#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
} l2cache_way_num_t;
/*! @brief Level 2 cache controller way size. */
typedef enum _l2cache_way_size
{
kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
} l2cache_way_size;
/*! @brief Level 2 cache controller replacement policy. */
typedef enum _l2cache_replacement
{
kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
} l2cache_replacement_t;
/*! @brief Level 2 cache controller force write allocate options. */
typedef enum _l2cache_writealloc
{
kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
} l2cache_writealloc_t;
/*! @brief Level 2 cache controller tag/data ram latency. */
typedef enum _l2cache_latency
{
kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
} l2cache_latency_t;
/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
typedef struct _l2cache_latency_config
{
l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
l2cache_latency_t dataWriteLate; /*!< Data write latency. */
l2cache_latency_t dataReadLate; /*!< Data Read latency. */
l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
} L2cache_latency_config_t;
/*! @brief Level 2 cache controller configure structure. */
typedef struct _l2cache_config
{
/* ------------------------ l2 cachec basic settings ---------------------------- */
l2cache_way_num_t wayNum; /*!< The number of ways. */
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
/* ------------------------ tag/data ram latency settings ----------------------- */
L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
/* ------------------------ Prefetch enable settings ---------------------------- */
bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
bool dataPrefetchEnable; /*!< Data prefetch enable. */
/* ------------------------ Non-secure access settings -------------------------- */
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
/* ------------------------ other settings -------------------------------------- */
l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
} l2cache_config_t;
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Control for cortex-m7 L1 cache
*@{
*/
/*!
* @brief Enables cortex-m7 L1 instruction cache.
*
*/
static inline void L1CACHE_EnableICache(void)
{
SCB_EnableICache();
}
/*!
* @brief Disables cortex-m7 L1 instruction cache.
*
*/
static inline void L1CACHE_DisableICache(void)
{
SCB_DisableICache();
}
/*!
* @brief Invalidate cortex-m7 L1 instruction cache.
*
*/
static inline void L1CACHE_InvalidateICache(void)
{
SCB_InvalidateICache();
}
/*!
* @brief Invalidate cortex-m7 L1 instruction cache by range.
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 I-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Enables cortex-m7 L1 data cache.
*
*/
static inline void L1CACHE_EnableDCache(void)
{
SCB_EnableDCache();
}
/*!
* @brief Disables cortex-m7 L1 data cache.
*
*/
static inline void L1CACHE_DisableDCache(void)
{
SCB_DisableDCache();
}
/*!
* @brief Invalidates cortex-m7 L1 data cache.
*
*/
static inline void L1CACHE_InvalidateDCache(void)
{
SCB_InvalidateDCache();
}
/*!
* @brief Cleans cortex-m7 L1 data cache.
*
*/
static inline void L1CACHE_CleanDCache(void)
{
SCB_CleanDCache();
}
/*!
* @brief Cleans and Invalidates cortex-m7 L1 data cache.
*
*/
static inline void L1CACHE_CleanInvalidateDCache(void)
{
SCB_CleanInvalidateDCache();
}
/*!
* @brief Invalidates cortex-m7 L1 data cache by range.
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 D-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
{
SCB_InvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
}
/*!
* @brief Cleans cortex-m7 L1 data cache by range.
*
* @param address The start address of the memory to be cleaned.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 D-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
{
SCB_CleanDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
}
/*!
* @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
*
* @param address The start address of the memory to be clean and invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L1 D-cache line size if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
{
SCB_CleanInvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
}
/*@}*/
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
/*!
* @name Control for L2 pl310 cache
*@{
*/
/*!
* @brief Initializes the level 2 cache controller module.
*
* @param config Pointer to configuration structure. See "l2cache_config_t".
*/
void L2CACHE_Init(l2cache_config_t *config);
/*!
* @brief Gets an available default settings for the cache controller.
*
* This function initializes the cache controller configuration structure with default settings.
* The default values are:
* @code
* config->waysNum = kL2CACHE_8ways;
* config->waySize = kL2CACHE_32KbSize;
* config->repacePolicy = kL2CACHE_Roundrobin;
* config->lateConfig = NULL;
* config->istrPrefetchEnable = false;
* config->dataPrefetchEnable = false;
* config->nsLockdownEnable = false;
* config->writeAlloc = kL2CACHE_UseAwcache;
* @endcode
* @param config Pointer to the configuration structure.
*/
void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
/*!
* @brief Enables the level 2 cache controller.
* This function enables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Enable(void);
/*!
* @brief Disables the level 2 cache controller.
* This function disables the cache controller. Must be written using a secure access.
* If write with a Non-secure access will cause a DECERR response.
*
*/
void L2CACHE_Disable(void);
/*!
* @brief Invalidates the Level 2 cache.
* This function invalidates all entries in cache.
*
*/
void L2CACHE_Invalidate(void);
/*!
* @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
* This function invalidates all cache lines between two physical addresses.
*
* @param address The start address of the memory to be invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Cleans the level 2 cache controller.
* This function cleans all entries in the level 2 cache controller.
*
*/
void L2CACHE_Clean(void);
/*!
* @brief Cleans the Level 2 cache lines in the range of two physical addresses.
* This function cleans all cache lines between two physical addresses.
*
* @param address The start address of the memory to be cleaned.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Cleans and invalidates the level 2 cache controller.
* This function cleans and invalidates all entries in the level 2 cache controller.
*
*/
void L2CACHE_CleanInvalidate(void);
/*!
* @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
* This function cleans and invalidates all cache lines between two physical addresses.
*
* @param address The start address of the memory to be cleaned and invalidated.
* @param size_byte The memory size.
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
* The startAddr here will be forced to align to L2 line size if startAddr
* is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Enables or disables to lock down the data and instruction by way.
* This function locks down the cached instruction/data by way and prevent the adresses from
* being allocated and prevent dara from being evicted out of the level 2 cache.
* But the normal cache maintenance operations that invalidate, clean or clean
* and validate cache contents affect the locked-down cache lines as normal.
*
* @param masterId The master id, range from 0 ~ 7.
* @param mask The ways to be enabled or disabled to lockdown.
* each bit in value is related to each way of the cache. for example:
* value: bit 0 ------ way 0.
* value: bit 1 ------ way 1.
* --------------------------
* value: bit 15 ------ way 15.
* Note: please make sure the value setting is align with your supported ways.
* @param enable True enable the lockdown, false to disable the lockdown.
*/
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
/*@}*/
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
/*!
* @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
* Mainly used for many drivers for easy cache operation.
*@{
*/
/*!
* @brief Invalidates all instruction caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Cleans all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* @param address The physical address.
* @param size_byte size of the memory to be cleaned.
* @note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Cleans and Invalidates all data caches by range.
*
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
*
* @param address The physical address.
* @param size_byte size of the memory to be cleaned and invalidated.
* @note address and size should be aligned to cache line size
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
*/
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_CACHE_H_*/

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/*
* Copyright 2017-2019 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_elcdif.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.elcdif"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for ELCDIF module.
*
* @param base ELCDIF peripheral base address
*/
static uint32_t ELCDIF_GetInstance(LCDIF_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to ELCDIF bases for each instance. */
static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to eLCDIF apb_clk for each instance. */
static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS;
#if defined(LCDIF_PERIPH_CLOCKS)
/*! @brief Pointers to eLCDIF pix_clk for each instance. */
static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS;
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief The control register value to select different pixel format. */
static const elcdif_pixel_format_reg_t s_pixelFormatReg[] = {
/* kELCDIF_PixelFormatRAW8 */
{/* Register CTRL. */
LCDIF_CTRL_WORD_LENGTH(1U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
/* kELCDIF_PixelFormatRGB565 */
{/* Register CTRL. */
LCDIF_CTRL_WORD_LENGTH(0U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
/* kELCDIF_PixelFormatRGB666 */
{/* Register CTRL. */
LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
/* kELCDIF_PixelFormatXRGB8888 */
{/* Register CTRL. 24-bit. */
LCDIF_CTRL_WORD_LENGTH(3U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)},
/* kELCDIF_PixelFormatRGB888 */
{/* Register CTRL. 24-bit. */
LCDIF_CTRL_WORD_LENGTH(3U),
/* Register CTRL1. */
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)},
};
/*******************************************************************************
* Codes
******************************************************************************/
static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++)
{
if (s_elcdifBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_elcdifBases));
return instance;
}
/*!
* brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
*
* This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
* to the configuration structure.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
{
assert(NULL != config);
assert((uint32_t)config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = ELCDIF_GetInstance(base);
/* Enable the clock. */
CLOCK_EnableClock(s_elcdifApbClocks[instance]);
#if defined(LCDIF_PERIPH_CLOCKS)
CLOCK_EnableClock(s_elcdifPixClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset. */
ELCDIF_Reset(base);
base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) |
LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */
LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */
LCDIF_CTRL_MASTER_MASK;
base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1;
base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) |
((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT);
base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */
(uint32_t)config->polarityFlags | (uint32_t)config->vsw;
base->VDCTRL1 =
(uint32_t)config->vsw + (uint32_t)config->panelHeight + (uint32_t)config->vfp + (uint32_t)config->vbp;
base->VDCTRL2 =
((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) |
(((uint32_t)config->hfp + (uint32_t)config->hbp + (uint32_t)config->panelWidth + (uint32_t)config->hsw))
<< LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT;
base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) |
(((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT);
base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT);
base->CUR_BUF = config->bufferAddr;
base->NEXT_BUF = config->bufferAddr;
}
/*!
* brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* code
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow |
kELCDIF_HsyncActiveLow |
kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
code
*
* param config Pointer to the eLCDIF configuration structure.
*/
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = (uint32_t)kELCDIF_VsyncActiveLow | (uint32_t)kELCDIF_HsyncActiveLow |
(uint32_t)kELCDIF_DataEnableActiveLow | (uint32_t)kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
}
/*!
* brief Set the pixel format in RGB (DOTCLK) mode.
*
* param base eLCDIF peripheral base address.
* param pixelFormat The pixel format.
*/
void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat)
{
assert((uint32_t)pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
base->CTRL = (base->CTRL & ~(LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK |
LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)) |
s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl;
base->CTRL1 = s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl1;
}
/*!
* brief Deinitializes the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Deinit(LCDIF_Type *base)
{
ELCDIF_Reset(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = ELCDIF_GetInstance(base);
/* Disable the clock. */
#if defined(LCDIF_PERIPH_CLOCKS)
CLOCK_DisableClock(s_elcdifPixClocks[instance]);
#endif
CLOCK_DisableClock(s_elcdifApbClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Stop display in RGB (DOTCLK) mode and wait until finished.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_RgbModeStop(LCDIF_Type *base)
{
base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
/* Wait for data transfer finished. */
while (0U != (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK))
{
}
}
/*!
* brief Reset the eLCDIF peripheral.
*
* param base eLCDIF peripheral base address.
*/
void ELCDIF_Reset(LCDIF_Type *base)
{
/*
* ELCDIF reset workflow:
*
* 1. Ungate clock.
* 2. Trigger the software reset.
* 3. The software reset finished when clk_gate bit is set.
* 4. Ungate the clock.
* 5. Release the reset.
*/
/* Ungate clock. */
base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
/*
* If already in reset state, release the reset.
* If not, trigger reset.
*/
if (0U == (base->CTRL & LCDIF_CTRL_SFTRST_MASK))
{
/* Trigger reset. */
base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK;
/* Reset is not finished until CLK_GATE is set. */
while (0U == (base->CTRL & LCDIF_CTRL_CLKGATE_MASK))
{
}
/* Ungate the clock. */
base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK;
}
/* Release the reset. */
base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK;
}
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
/*!
* brief Set the configuration for alpha surface buffer.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
{
assert(NULL != config);
base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
base->AS_BUF = config->bufferAddr;
base->AS_NEXT_BUF = config->bufferAddr;
}
/*!
* brief Set the alpha surface blending configuration.
*
* param base eLCDIF peripheral base address.
* param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
{
assert(NULL != config);
uint32_t reg;
reg = base->AS_CTRL;
reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK |
LCDIF_AS_CTRL_ALPHA_CTRL_MASK);
reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) |
LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode));
if (config->invertAlpha)
{
reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK;
}
base->AS_CTRL = reg;
}
#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
/*!
* brief Load the LUT value.
*
* This function loads the LUT value to the specific LUT memory, user can
* specify the start entry index.
*
* param base eLCDIF peripheral base address.
* param lut Which LUT to load.
* param startIndex The start index of the LUT entry to update.
* param lutData The LUT data to load.
* param count Count of p lutData.
* retval kStatus_Success Initialization success.
* retval kStatus_InvalidArgument Wrong argument.
*/
status_t ELCDIF_UpdateLut(
LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
{
volatile uint32_t *regLutAddr;
volatile uint32_t *regLutData;
uint32_t i;
status_t status;
/* Only has 256 entries. */
if (startIndex + count > ELCDIF_LUT_ENTRY_NUM)
{
status = kStatus_InvalidArgument;
}
else
{
if (kELCDIF_Lut0 == lut)
{
regLutAddr = &(base->LUT0_ADDR);
regLutData = &(base->LUT0_DATA);
}
else
{
regLutAddr = &(base->LUT1_ADDR);
regLutData = &(base->LUT1_DATA);
}
*regLutAddr = startIndex;
for (i = 0; i < count; i++)
{
*regLutData = lutData[i];
}
status = kStatus_Success;
}
return status;
}
#endif /* FSL_FEATURE_LCDIF_HAS_LUT */

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/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ELCDIF_H_
#define _FSL_ELCDIF_H_
#include "fsl_common.h"
/*!
* @addtogroup elcdif
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief eLCDIF driver version */
#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/* All IRQ flags in CTRL1 register. */
#define ELCDIF_CTRL1_IRQ_MASK \
(LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
/* All IRQ enable control bits in CTRL1 register. */
#define ELCDIF_CTRL1_IRQ_EN_MASK \
(LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
/* All IRQ flags in AS_CTRL register. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
#else
#define ELCDIF_AS_CTRL_IRQ_MASK 0U
#endif
/* All IRQ enable control bits in AS_CTRL register. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
#else
#define ELCDIF_AS_CTRL_IRQ_EN_MASK 0U
#endif
#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK))
#error Interrupt bits overlap, need to update the interrupt functions.
#endif
/* LUT memory entery number. */
#define ELCDIF_LUT_ENTRY_NUM 256U
/*!
* @brief eLCDIF signal polarity flags
*/
enum _elcdif_polarity_flags
{
kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */
kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */
kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */
kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */
kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */
kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data
on rising clock edge. */
kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling
clock edge, capture data
on rising clock edge. */
};
/*!
* @brief The eLCDIF interrupts to enable.
*/
enum _elcdif_interrupt_enable
{
kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */
kELCDIF_CurFrameDoneInterruptEnable =
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
kELCDIF_VsyncEdgeInterruptEnable =
LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
kELCDIF_SciSyncOnInterruptEnable =
LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */
#endif
};
/*!
* @brief The eLCDIF interrupt status flags.
*/
enum _elcdif_interrupt_flags
{
kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */
kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */
kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */
kELCDIF_CurFrameDone =
LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */
#if defined(LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */
#endif
};
/*!
* @brief eLCDIF status flags
*/
enum _elcdif_status_flags
{
kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */
kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */
kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */
kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */
#if defined(LCDIF_STAT_BUSY_MASK)
kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */
#endif
#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2,
otherwise current filed is 1. */
#endif
};
/*!
* @brief The pixel format.
*
* This enumerator should be defined together with the array s_pixelFormatReg.
* To support new pixel format, enhance this enumerator and s_pixelFormatReg.
*/
typedef enum _elcdif_pixel_format
{
kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */
kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */
kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused,
upper 2 bits of other bytes unused. */
kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */
kELCDIF_PixelFormatRGB888 = 4, /*!< RGB888 packed, one pixel uses 24 bits. */
} elcdif_pixel_format_t;
/*! @brief The LCD data bus type. */
typedef enum _elcdif_lcd_data_bus
{
kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */
kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */
kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */
kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */
} elcdif_lcd_data_bus_t;
/*!
* @brief The register value when using different pixel format.
*
* These register bits control the pixel format:
* - CTRL[DATA_FORMAT_24_BIT]
* - CTRL[DATA_FORMAT_18_BIT]
* - CTRL[DATA_FORMAT_16_BIT]
* - CTRL[WORD_LENGTH]
* - CTRL1[BYTE_PACKING_FORMAT]
*/
typedef struct _elcdif_pixel_format_reg
{
uint32_t regCtrl; /*!< Value of register CTRL. */
uint32_t regCtrl1; /*!< Value of register CTRL1. */
} elcdif_pixel_format_reg_t;
/*!
* @brief eLCDIF configure structure for RGB mode (DOTCLK mode).
*/
typedef struct _elcdif_rgb_mode_config
{
uint16_t panelWidth; /*!< Display panel width, pixels per line. */
uint16_t panelHeight; /*!< Display panel height, how many lines per panel. */
uint8_t hsw; /*!< HSYNC pulse width. */
uint8_t hfp; /*!< Horizontal front porch. */
uint8_t hbp; /*!< Horizontal back porch. */
uint8_t vsw; /*!< VSYNC pulse width. */
uint8_t vfp; /*!< Vrtical front porch. */
uint8_t vbp; /*!< Vertical back porch. */
uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */
uint32_t bufferAddr; /*!< Frame buffer address. */
elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */
elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */
} elcdif_rgb_mode_config_t;
/*!
* @brief eLCDIF alpha surface pixel format.
*/
typedef enum _elcdif_as_pixel_format
{
kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
} elcdif_as_pixel_format_t;
/*!
* @brief eLCDIF alpha surface buffer configuration.
*/
typedef struct _elcdif_as_buffer_config
{
uint32_t bufferAddr; /*!< Buffer address. */
elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */
} elcdif_as_buffer_config_t;
/*!
* @brief eLCDIF alpha mode during blending.
*/
typedef enum _elcdif_alpha_mode
{
kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
alpha value will be used for blend, for example, pixel alpha set
set to 200, user defined alpha set to 100, then the reault alpha
is 200 * 100 / 255. */
kELCDIF_AlphaRop /*!< Raster operation. */
} elcdif_alpha_mode_t;
/*!
* @brief eLCDIF ROP mode during blending.
*
* Explanation:
* - AS: Alpha surface
* - PS: Process surface
* - nAS: Alpha surface NOT value
* - nPS: Process surface NOT value
*/
typedef enum _elcdif_rop_mode
{
kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */
kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */
kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */
kELCDIF_RopNot = 0x7, /*!< nPS. */
kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */
kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */
} elcdif_rop_mode_t;
/*!
* @brief eLCDIF alpha surface blending configuration.
*/
typedef struct _elcdif_as_blend_config
{
uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref
kELCDIF_AlphaRop. */
bool invertAlpha; /*!< Set true to invert the alpha. */
elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */
elcdif_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */
} elcdif_as_blend_config_t;
/*!
* @brief eLCDIF LUT
*
* The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel
* before output to external displayer.
*
* There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address
* determins which memory to use.
*/
typedef enum _elcdif_lut
{
kELCDIF_Lut0 = 0, /*!< LUT 0. */
kELCDIF_Lut1, /*!< LUT 1. */
} elcdif_lut_t;
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @name eLCDIF initialization and de-initialization
* @{
*/
/*!
* @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
*
* This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
* to the configuration structure.
*
* @param base eLCDIF peripheral base address.
* @param config Pointer to the configuration structure.
*/
void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config);
/*!
* @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
*
* This function sets the configuration structure to default values.
* The default configuration is set to the following values.
* @code
config->panelWidth = 480U;
config->panelHeight = 272U;
config->hsw = 41;
config->hfp = 4;
config->hbp = 8;
config->vsw = 10;
config->vfp = 4;
config->vbp = 2;
config->polarityFlags = kELCDIF_VsyncActiveLow |
kELCDIF_HsyncActiveLow |
kELCDIF_DataEnableActiveLow |
kELCDIF_DriveDataOnFallingClkEdge;
config->bufferAddr = 0U;
config->pixelFormat = kELCDIF_PixelFormatRGB888;
config->dataBus = kELCDIF_DataBus24Bit;
@endcode
*
* @param config Pointer to the eLCDIF configuration structure.
*/
void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config);
/*!
* @brief Deinitializes the eLCDIF peripheral.
*
* @param base eLCDIF peripheral base address.
*/
void ELCDIF_Deinit(LCDIF_Type *base);
/* @} */
/*!
* @name Module operation
* @{
*/
/*!
* @brief Set the pixel format in RGB (DOTCLK) mode.
*
* @param base eLCDIF peripheral base address.
* @param pixelFormat The pixel format.
*/
void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat);
/*!
* @brief Start to display in RGB (DOTCLK) mode.
*
* @param base eLCDIF peripheral base address.
*/
static inline void ELCDIF_RgbModeStart(LCDIF_Type *base)
{
base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK;
}
/*!
* @brief Stop display in RGB (DOTCLK) mode and wait until finished.
*
* @param base eLCDIF peripheral base address.
*/
void ELCDIF_RgbModeStop(LCDIF_Type *base);
/*!
* @brief Set the next frame buffer address to display.
*
* @param base eLCDIF peripheral base address.
* @param bufferAddr The frame buffer address to set.
*/
static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)
{
base->NEXT_BUF = bufferAddr;
}
/*!
* @brief Reset the eLCDIF peripheral.
*
* @param base eLCDIF peripheral base address.
*/
void ELCDIF_Reset(LCDIF_Type *base);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN) && FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN)
/*!
* @brief Pull up or down the reset pin for the externel LCD controller.
*
* @param base eLCDIF peripheral base address.
* @param pullUp True to pull up reset pin, false to pull down.
*/
static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp)
{
if (pullUp)
{
base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK;
}
else
{
base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK;
}
}
#endif
/*!
* @brief Enable or disable the hand shake with PXP.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK;
}
else
{
base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK;
}
}
/* @} */
/*!
* @name Status
* @{
*/
/*!
* @brief Get the CRC value of the frame sent out.
*
* When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function
* can be used to get the CRC value of the frame sent.
*
* @param base eLCDIF peripheral base address.
* @return The CRC value.
*
* @note The CRC value is dependent on the LCD_DATABUS_WIDTH.
*/
static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base)
{
return base->CRC_STAT;
}
/*!
* @brief Get the bus master error virtual address.
*
* When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function
* can get the virtual address at which the AXI master received an error
* response from the slave.
*
* @param base eLCDIF peripheral base address.
* @return The error virtual address.
*/
static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base)
{
return base->BM_ERROR_STAT;
}
/*!
* @brief Get the eLCDIF status.
*
* The status flags are returned as a mask value, application could check the
* corresponding bit. Example:
*
* @code
uint32_t statusFlags;
statusFlags = ELCDIF_GetStatus(LCDIF);
if (kELCDIF_LFifoFull & statusFlags)
{
}
if (kELCDIF_TxFifoEmpty & statusFlags)
{
}
@endcode
*
* @param base eLCDIF peripheral base address.
* @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags.
*/
static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base)
{
return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK |
LCDIF_STAT_TXFIFO_EMPTY_MASK
#if defined(LCDIF_STAT_BUSY_MASK)
| LCDIF_STAT_BUSY_MASK
#endif
#if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
| LCDIF_STAT_DVI_CURRENT_FIELD_MASK
#endif
);
}
/*!
* @brief Get current count in Latency buffer (LFIFO).
*
* @param base eLCDIF peripheral base address.
* @return The LFIFO current count
*/
static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base)
{
return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT;
}
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enables eLCDIF interrupt requests.
*
* @param base eLCDIF peripheral base address.
* @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable.
*/
static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask)
{
base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK);
#endif
}
/*!
* @brief Disables eLCDIF interrupt requests.
*
* @param base eLCDIF peripheral base address.
* @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable.
*/
static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask)
{
base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK);
#endif
}
/*!
* @brief Get eLCDIF interrupt peding status.
*
* @param base eLCDIF peripheral base address.
* @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags.
*/
static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base)
{
uint32_t flags;
flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK);
#endif
return flags;
}
/*!
* @brief Clear eLCDIF interrupt peding status.
*
* @param base eLCDIF peripheral base address.
* @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags.
*/
static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask)
{
base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK);
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK);
#endif
}
/* @} */
#if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
/*!
* @name Alpha surface
* @{
*/
/*!
* @brief Set the configuration for alpha surface buffer.
*
* @param base eLCDIF peripheral base address.
* @param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config);
/*!
* @brief Set the alpha surface blending configuration.
*
* @param base eLCDIF peripheral base address.
* @param config Pointer to the configuration structure.
*/
void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config);
/*!
* @brief Set the next alpha surface buffer address.
*
* @param base eLCDIF peripheral base address.
* @param bufferAddr Alpha surface buffer address.
*/
static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr)
{
base->AS_NEXT_BUF = bufferAddr;
}
/*!
* @brief Set the overlay color key.
*
* If a pixel in the current overlay image with a color that falls in the range
* from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface
* pixel value for that location.
*
* @param base eLCDIF peripheral base address.
* @param colorKeyLow Color key low range.
* @param colorKeyHigh Color key high range.
*
* @note Colorkey operations are higher priority than alpha or ROP operations
*/
static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
{
base->AS_CLRKEYLOW = colorKeyLow;
base->AS_CLRKEYHIGH = colorKeyHigh;
}
/*!
* @brief Enable or disable the color key.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK;
}
else
{
base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK;
}
}
/*!
* @brief Enable or disable the alpha surface.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK;
}
else
{
base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK;
}
}
/*!
* @brief Enable or disable the process surface.
*
* Process surface is the normal frame buffer. The process surface content
* is controlled by ::ELCDIF_SetNextBufferAddr.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK;
}
else
{
base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK;
}
}
/* @} */
#endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
#if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
/*!
* @name LUT
*
* The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits pixel
* before output to external displayer.
*
* There are two 256x24 bits LUT memory in LCDIF, the LSB of frame buffer address
* determins which memory to use.
*
* @{
*/
/*!
* @brief Enable or disable the LUT.
*
* @param base eLCDIF peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void ELCDIF_EnableLut(LCDIF_Type *base, bool enable)
{
if (enable)
{
base->LUT_CTRL &= ~LCDIF_LUT_CTRL_LUT_BYPASS_MASK;
}
else
{
base->LUT_CTRL |= LCDIF_LUT_CTRL_LUT_BYPASS_MASK;
}
}
/*!
* @brief Load the LUT value.
*
* This function loads the LUT value to the specific LUT memory, user can
* specify the start entry index.
*
* @param base eLCDIF peripheral base address.
* @param lut Which LUT to load.
* @param startIndex The start index of the LUT entry to update.
* @param lutData The LUT data to load.
* @param count Count of @p lutData.
* @retval kStatus_Success Initialization success.
* @retval kStatus_InvalidArgument Wrong argument.
*/
status_t ELCDIF_UpdateLut(
LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count);
/* @} */
#endif /* FSL_FEATURE_LCDIF_HAS_LUT */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/* @} */
#endif /*_FSL_ELCDIF_H_*/

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/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_SEMC_H_
#define _FSL_SEMC_H_
#include "fsl_common.h"
/*!
* @addtogroup semc
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief SEMC driver version 2.3.1. */
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
/*@}*/
/*! @brief SEMC status, _semc_status. */
enum
{
kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */
kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */
kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */
kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */
kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */
kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */
kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */
kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */
kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */
/*! Invalid column address bit width. */
kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */
kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */
};
/*! @brief SEMC memory device type. */
typedef enum _semc_mem_type
{
kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
kSEMC_MemType_SRAM, /*!< SRAM */
kSEMC_MemType_NOR, /*!< NOR */
kSEMC_MemType_NAND, /*!< NAND */
kSEMC_MemType_8080 /*!< 8080. */
} semc_mem_type_t;
/*! @brief SEMC WAIT/RDY polarity. */
typedef enum _semc_waitready_polarity
{
kSEMC_LowActive = 0, /*!< Low active. */
kSEMC_HighActive, /*!< High active. */
} semc_waitready_polarity_t;
/*! @brief SEMC SDRAM Chip selection . */
typedef enum _semc_sdram_cs
{
kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
} semc_sdram_cs_t;
/*! @brief SEMC SRAM Chip selection . */
typedef enum _semc_sram_cs
{
#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U)
kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */
kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */
kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */
#else
kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
} semc_sram_cs_t;
/*! @brief SEMC NAND device type. */
typedef enum _semc_nand_access_type
{
kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */
kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */
} semc_nand_access_type_t;
/*! @brief SEMC interrupts . */
typedef enum _semc_interrupt_enable
{
kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
} semc_interrupt_enable_t;
/*! @brief SEMC IP command data size in bytes. */
typedef enum _semc_ipcmd_datasize
{
kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
} semc_ipcmd_datasize_t;
/*! @brief SEMC auto-refresh timing. */
typedef enum _semc_refresh_time
{
kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
} semc_refresh_time_t;
/*! @brief CAS latency */
typedef enum _semc_caslatency
{
kSEMC_LatencyOne = 1, /*!< Latency 1. */
kSEMC_LatencyTwo, /*!< Latency 2. */
kSEMC_LatencyThree, /*!< Latency 3. */
} semc_caslatency_t;
/*! @brief SEMC sdram column address bit number. */
typedef enum _semc_sdram_column_bit_num
{
kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
kSEMC_SdramColunm_11bit, /*!< 11 bit. */
kSEMC_SdramColunm_10bit, /*!< 10 bit. */
kSEMC_SdramColunm_9bit, /*!< 9 bit. */
#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT)
kSEMC_SdramColunm_8bit, /*!< 8 bit. */
#endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */
} semc_sdram_column_bit_num_t;
/*! @brief SEMC sdram burst length. */
typedef enum _semc_sdram_burst_len
{
/*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during
long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */
#if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U)
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
#else
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
#endif /* FSL_FEATURE_SEMC_ERRATA_050577 */
} sem_sdram_burst_len_t;
/*! @brief SEMC nand column address bit number. */
typedef enum _semc_nand_column_bit_num
{
kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
kSEMC_NandColum_15bit, /*!< 15 bit. */
kSEMC_NandColum_14bit, /*!< 14 bit. */
kSEMC_NandColum_13bit, /*!< 13 bit. */
kSEMC_NandColum_12bit, /*!< 12 bit. */
kSEMC_NandColum_11bit, /*!< 11 bit. */
kSEMC_NandColum_10bit, /*!< 10 bit. */
kSEMC_NandColum_9bit, /*!< 9 bit. */
} semc_nand_column_bit_num_t;
/*! @brief SEMC nand burst length. */
typedef enum _semc_nand_burst_len
{
kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
} sem_nand_burst_len_t;
/*! @brief SEMC nor/sram column address bit number. */
typedef enum _semc_norsram_column_bit_num
{
kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
kSEMC_NorColum_11bit, /*!< 11 bit. */
kSEMC_NorColum_10bit, /*!< 10 bit. */
kSEMC_NorColum_9bit, /*!< 9 bit. */
kSEMC_NorColum_8bit, /*!< 8 bit. */
kSEMC_NorColum_7bit, /*!< 7 bit. */
kSEMC_NorColum_6bit, /*!< 6 bit. */
kSEMC_NorColum_5bit, /*!< 5 bit. */
kSEMC_NorColum_4bit, /*!< 4 bit. */
kSEMC_NorColum_3bit, /*!< 3 bit. */
kSEMC_NorColum_2bit /*!< 2 bit. */
} semc_norsram_column_bit_num_t;
/*! @brief SEMC nor/sram burst length. */
typedef enum _semc_norsram_burst_len
{
kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
} sem_norsram_burst_len_t;
/*! @brief SEMC dbi column address bit number. */
typedef enum _semc_dbi_column_bit_num
{
kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
} semc_dbi_column_bit_num_t;
/*! @brief SEMC dbi burst length. */
typedef enum _semc_dbi_burst_len
{
kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
} sem_dbi_burst_len_t;
/*! @brief SEMC IOMUXC. */
typedef enum _semc_iomux_pin
{
kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
} semc_iomux_pin;
/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
typedef enum _semc_iomux_nora27_pin
{
kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
} semc_iomux_nora27_pin;
/*! @brief SEMC port size. */
typedef enum _semc_port_size
{
kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
kSEMC_PortSize16Bit, /*!< 16-Bit port size. */
#if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U)
kSEMC_PortSize32Bit /*!< 32-Bit port size. */
#endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */
} smec_port_size_t;
/*! @brief SEMC address mode. */
typedef enum _semc_addr_mode
{
kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
} semc_addr_mode_t;
/*! @brief SEMC DQS read strobe mode. */
typedef enum _semc_dqs_mode
{
kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
} semc_dqs_mode_t;
/*! @brief SEMC ADV signal active polarity. */
typedef enum _semc_adv_polarity
{
kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
kSEMC_AdvActiveHigh, /*!< Adv active high. */
} semc_adv_polarity_t;
/*! @brief SEMC sync mode. */
typedef enum _semc_sync_mode
{
kSEMC_AsyncMode = 0, /*!< Async mode. */
kSEMC_SyncMode, /*!< Sync mode. */
} semc_sync_mode_t;
/*! @brief SEMC ADV signal level control. */
typedef enum _semc_adv_level_control
{
kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */
kSEMC_AdvLow, /*!< Adv is low during address hold state. */
} semc_adv_level_control_t;
/*! @brief SEMC RDY signal active polarity. */
typedef enum _semc_rdy_polarity
{
kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
kSEMC_RdyActivehigh, /*!< Adv active low. */
} semc_rdy_polarity_t;
/*! @brief SEMC IP command for NAND: address mode. */
typedef enum _semc_ipcmd_nand_addrmode
{
kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
} semc_ipcmd_nand_addrmode_t;
/*! @brief SEMC IP command for NAND： command mode. */
typedef enum _semc_ipcmd_nand_cmdmode
{
kSEMC_NANDCM_Command = 0x2U, /*!< command. */
kSEMC_NANDCM_CommandHold, /*!< Command hold. */
kSEMC_NANDCM_CommandAddress, /*!< Command address. */
kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
kSEMC_NANDCM_CommandRead, /*!< Command read. */
kSEMC_NANDCM_CommandWrite, /*!< Command write. */
kSEMC_NANDCM_Read, /*!< Read. */
kSEMC_NANDCM_Write /*!< Write. */
} semc_ipcmd_nand_cmdmode_t;
/*! @brief SEMC NAND address option. */
typedef enum _semc_nand_address_option
{
kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
} semc_nand_address_option_t;
/*! @brief SEMC IP command for NOR. */
typedef enum _semc_ipcmd_nor_dbi
{
kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
kSEMC_NORDBICM_Write /*!< NOR write. */
} semc_ipcmd_nor_dbi_t;
/*! @brief SEMC IP command for SRAM. */
typedef enum _semc_ipcmd_sram
{
kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
} semc_ipcmd_sram_t;
/*! @brief SEMC IP command for SDARM. */
typedef enum _semc_ipcmd_sdram
{
kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
} semc_ipcmd_sdram_t;
/*! @brief SEMC SDRAM configuration structure.
*
* 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
* should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
* Take refer to BR0~BR3 register in RM for details.
* 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
* it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
* The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
* idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
* similar to prescalePeriod_N16Cycle.
*
*/
typedef struct _semc_sdram_config
{
semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
smec_port_size_t portSize; /*!< Port size. */
sem_sdram_burst_len_t burstLen; /*!< Burst length. */
semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_caslatency_t casLatency; /*!< CAS latency. */
uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
uint8_t refreshBurstLen; /*!< Refresh burst length. */
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
read data. */
#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_sdram_config_t;
/*! @brief SEMC NAND device timing configuration structure. */
typedef struct _semc_nand_timing_config
{
uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
uint8_t tReLow_Ns; /*!< RE low time: tRP. */
uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
} semc_nand_timing_config_t;
/*! @brief SEMC NAND configuration structure. */
typedef struct _semc_nand_config
{
semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
uint32_t axiAddress; /*!< The base address for AXI nand. */
uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
uint32_t ipgAddress; /*!< The base address for IPG nand . */
uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
bool edoModeEnabled; /*!< EDO mode enabled. */
semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
sem_nand_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
} semc_nand_config_t;
/*! @brief SEMC NOR configuration structure. */
typedef struct _semc_nor_config
{
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
uint8_t addrPortWidth; /*!< The address port width. */
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
semc_addr_mode_t addrMode; /*!< Address mode. */
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
uint8_t tCeHold_Ns; /*!< The CE hold time. */
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
uint8_t tAddrHold_Ns; /*!< The address hold time. */
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
#endif
uint8_t latencyCount; /*!< Latency count for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
read data. */
#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_nor_config_t;
/*! @brief SEMC SRAM configuration structure. */
typedef struct _semc_sram_config
{
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
uint8_t addrPortWidth; /*!< The address port width. */
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
semc_addr_mode_t addrMode; /*!< Address mode. */
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
semc_sync_mode_t syncMode; /*!< Sync mode. */
#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK)
bool waitEnable; /*!< Wait enable. */
#endif /* SEMC_SRAMCR0_WAITEN_MASK */
#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK)
uint8_t waitSample; /*!< Wait sample. */
#endif /* SEMC_SRAMCR0_WAITSP_MASK */
#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */
#endif /* SEMC_SRAMCR4_ADVH_MASK */
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
uint8_t tCeHold_Ns; /*!< The CE hold time. */
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
uint8_t readHoldTime_Ns; /*!< read hold time. */
#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
uint8_t tAddrHold_Ns; /*!< The address hold time. */
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
uint8_t latencyCount; /*!< Latency count for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
read data. */
#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
} semc_sram_config_t;
/*! @brief SEMC DBI configuration structure. */
typedef struct _semc_dbi_config
{
semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
uint32_t address; /*!< The base address. */
uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
sem_dbi_burst_len_t burstLen; /*!< Burst length. */
smec_port_size_t portSize; /*!< Port size. */
uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
uint8_t tWexLow_Ns; /*!< WEX low time. */
uint8_t tWexHigh_Ns; /*!< WEX high time. */
uint8_t tRdxLow_Ns; /*!< RDX low time. */
uint8_t tRdxHigh_Ns; /*!< RDX high time. */
uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
} semc_dbi_config_t;
/*! @brief SEMC AXI queue a weight setting structure. */
typedef struct _semc_queuea_weight_struct
{
uint32_t qos : 4; /*!< weight of qos for queue 0 . */
uint32_t aging : 4; /*!< weight of aging for queue 0.*/
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
} semc_queuea_weight_struct_t;
/*! @brief SEMC AXI queue a weight setting union. */
typedef union _semc_queuea_weight
{
semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
} semc_queuea_weight_t;
/*! @brief SEMC AXI queue b weight setting structure. */
typedef struct _semc_queueb_weight_struct
{
uint32_t qos : 4; /*!< weight of qos for queue 1. */
uint32_t aging : 4; /*!< weight of aging for queue 1.*/
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
} semc_queueb_weight_struct_t;
/*! @brief SEMC AXI queue b weight setting union. */
typedef union _semc_queueb_weight
{
semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
} semc_queueb_weight_t;
/*! @brief SEMC AXI queue weight setting. */
typedef struct _semc_axi_queueweight
{
bool queueaEnable; /*!< Enable queue a. */
semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
bool queuebEnable; /*!< Enable queue b. */
semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
} semc_axi_queueweight_t;
/*!
* @brief SEMC configuration structure.
*
* busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
* 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
* cmdTimeoutCycles: is used for command execution timeout cycles. it's
* similar to the busTimeoutCycles.
*/
typedef struct _semc_config_t
{
semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
} semc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name SEMC Initialization and De-initialization
* @{
*/
/*!
* @brief Gets the SEMC default basic configuration structure.
*
* The purpose of this API is to get the default SEMC
* configure structure for SEMC_Init(). User may use the initialized
* structure unchanged in SEMC_Init(), or modify some fields of the
* structure before calling SEMC_Init().
* Example:
@code
semc_config_t config;
SEMC_GetDefaultConfig(&config);
@endcode
* @param config The SEMC configuration structure pointer.
*/
void SEMC_GetDefaultConfig(semc_config_t *config);
/*!
* @brief Initializes SEMC.
* This function ungates the SEMC clock and initializes SEMC.
* This function must be called before calling any other SEMC driver functions.
*
* @param base SEMC peripheral base address.
* @param configure The SEMC configuration structure pointer.
*/
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
/*!
* @brief Deinitializes the SEMC module and gates the clock.
*
* This function gates the SEMC clock. As a result, the SEMC module doesn't work after
* calling this function, for some IDE, calling this API may cause the next downloading
* operation failed. so, please call this API cautiously. Additional, users can
* using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
* operation in drivers.
*
* @param base SEMC peripheral base address.
*/
void SEMC_Deinit(SEMC_Type *base);
/* @} */
/*!
* @name SEMC Configuration Operation For Each Memory Type
* @{
*/
/*!
* @brief Configures SDRAM controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param cs The chip selection.
* @param config The sdram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures NAND controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The nand configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures NOR controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The nor configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures SRAM controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param cs The chip selection.
* @param config The sram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
semc_sram_cs_t cs,
semc_sram_config_t *config,
uint32_t clkSrc_Hz);
/*!
* @brief Configures SRAM controller in SEMC.
* @deprecated Do not use this function. It has been superceded by @ref SEMC_ConfigureSRAMWithChipSelection.
* @param base SEMC peripheral base address.
* @param config The sram configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
/*!
* @brief Configures DBI controller in SEMC.
*
* @param base SEMC peripheral base address.
* @param config The dbi configuration.
* @param clkSrc_Hz The SEMC clock frequency.
*/
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
/* @} */
/*!
* @name SEMC Interrupt Operation
* @{
*/
/*!
* @brief Enables the SEMC interrupt.
*
* This function enables the SEMC interrupts according to the provided mask. The mask
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
* For example, to enable the IP command done and error interrupt, do the following.
* @code
* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
* @endcode
*
* @param base SEMC peripheral base address.
* @param mask SEMC interrupts to enable. This is a logical OR of the
* enumeration :: semc_interrupt_enable_t.
*/
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
{
base->INTEN |= mask;
}
/*!
* @brief Disables the SEMC interrupt.
*
* This function disables the SEMC interrupts according to the provided mask. The mask
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
* For example, to disable the IP command done and error interrupt, do the following.
* @code
* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
* @endcode
*
* @param base SEMC peripheral base address.
* @param mask SEMC interrupts to disable. This is a logical OR of the
* enumeration :: semc_interrupt_enable_t.
*/
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
{
base->INTEN &= ~mask;
}
/*!
* @brief Gets the SEMC status.
*
* This function gets the SEMC interrupts event status.
* User can use the a logical OR of enumeration member as a mask.
* See @ref semc_interrupt_enable_t.
*
* @param base SEMC peripheral base address.
* @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
*/
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
{
return (base->INTR != 0x00U) ? true : false;
}
/*!
* @brief Clears the SEMC status flag state.
*
* The following status register flags can be cleared SEMC interrupt status.
*
* @param base SEMC base pointer
* @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
*/
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
{
base->INTR |= mask;
}
/* @} */
/*!
* @name SEMC Memory Access Operation
* @{
*/
/*!
* @brief Check if SEMC is in idle.
*
* @param base SEMC peripheral base address.
* @return True SEMC is in idle, false is not in idle.
*/
static inline bool SEMC_IsInIdle(SEMC_Type *base)
{
return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false;
}
/*!
* @brief SEMC IP command access.
*
* @param base SEMC peripheral base address.
* @param type SEMC memory type. refer to "semc_mem_type_t"
* @param address SEMC device address.
* @param command SEMC IP command.
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
* For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
* For SRAM device, take refer to "semc_ipcmd_sram_t".
* For SDRAM device, take refer to "semc_ipcmd_sdram_t".
* @param write Data for write access.
* @param read Data pointer for read data out.
*/
status_t SEMC_SendIPCommand(
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
/*!
* @brief Build SEMC IP command for NAND.
*
* This function build SEMC NAND IP command. The command is build of user command code,
* SEMC address mode and SEMC command mode.
*
* @param userCommand NAND device normal command.
* @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
* @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
*/
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
semc_ipcmd_nand_addrmode_t addrMode,
semc_ipcmd_nand_cmdmode_t cmdMode)
{
return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU);
}
/*!
* @brief Check if the NAND device is ready.
*
* @param base SEMC peripheral base address.
* @return True NAND is ready, false NAND is not ready.
*/
static inline bool SEMC_IsNandReady(SEMC_Type *base)
{
return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false;
}
/*!
* @brief SEMC NAND device memory write through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NAND device address.
* @param data Data for write access.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NAND device memory read through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NAND device address.
* @param data Data pointer for data read out.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NOR device memory write through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NOR device address.
* @param data Data for write access.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/*!
* @brief SEMC NOR device memory read through IP command.
*
* @param base SEMC peripheral base address.
* @param address SEMC NOR device address.
* @param data Data pointer for data read out.
* @param size_bytes Data length.
*/
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_SEMC_H_*/

2427
drivers/fsl_usdhc.c Normal file
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1676
drivers/fsl_usdhc.h Normal file
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524
flags.cmake
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@ -1,524 +0,0 @@
SET(CMAKE_ASM_FLAGS_DEBUG " \
-DDEBUG \
-D__STARTUP_CLEAR_BSS \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_ASM_FLAGS_RELEASE " \
-DNDEBUG \
-D__STARTUP_CLEAR_BSS \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_ASM_FLAGS_SDRAM_DEBUG " \
-D__STARTUP_CLEAR_BSS \
-DDEBUG \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_ASM_FLAGS_SDRAM_RELEASE " \
-D__STARTUP_CLEAR_BSS \
-DNDEBUG \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_DEBUG " \
-D__STARTUP_CLEAR_BSS \
-DDEBUG \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_RELEASE " \
-D__STARTUP_CLEAR_BSS \
-DNDEBUG \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_DEBUG " \
-DDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DFSL_RTOS_FREE_RTOS \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_RELEASE " \
-DNDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DFSL_RTOS_FREE_RTOS \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_SDRAM_DEBUG " \
-DSKIP_SYSCLK_INIT \
-DDATA_SECTION_IS_CACHEABLE=1 \
-DDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DFSL_RTOS_FREE_RTOS \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_SDRAM_RELEASE " \
-DSKIP_SYSCLK_INIT \
-DDATA_SECTION_IS_CACHEABLE=1 \
-DNDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DFSL_RTOS_FREE_RTOS \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG " \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DFSL_RTOS_FREE_RTOS \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE " \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DNDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DFSL_RTOS_FREE_RTOS \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_CXX_FLAGS_DEBUG " \
-DDEBUG \
-DSERIAL_PORT_TYPE_UART=1 \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_CXX_FLAGS_RELEASE " \
-DNDEBUG \
-DSERIAL_PORT_TYPE_UART=1 \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_CXX_FLAGS_SDRAM_DEBUG " \
-DDEBUG \
-DSERIAL_PORT_TYPE_UART=1 \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_CXX_FLAGS_SDRAM_RELEASE " \
-DNDEBUG \
-DSERIAL_PORT_TYPE_UART=1 \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_DEBUG " \
-DDEBUG \
-DSERIAL_PORT_TYPE_UART=1 \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_RELEASE " \
-DNDEBUG \
-DSERIAL_PORT_TYPE_UART=1 \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld -static \
")
SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld -static \
")
SET(CMAKE_EXE_LINKER_FLAGS_SDRAM_DEBUG " \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld -static \
")
SET(CMAKE_EXE_LINKER_FLAGS_SDRAM_RELEASE " \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_sdram.ld -static \
")
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_DEBUG " \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld -static \
")
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_RELEASE " \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-T${ProjDirPath}/MIMXRT1052/gcc/MIMXRT1052xxxxx_flexspi_nor.ld -static \
")

25
freertos/middleware_freertos-kernel_MIMXRT1052.cmake
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@ -1,25 +0,0 @@
if(NOT MIDDLEWARE_FREERTOS-KERNEL_MIMXRT1052_INCLUDED)
set(MIDDLEWARE_FREERTOS-KERNEL_MIMXRT1052_INCLUDED true CACHE BOOL "middleware_freertos-kernel component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/croutine.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/event_groups.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/list.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/GCC/ARM_CM4F/port.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/queue.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/stream_buffer.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/tasks.c
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/timers.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/include
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/GCC/ARM_CM4F
)
include(middleware_freertos-kernel_extension_MIMXRT1052)
endif()

10
freertos/middleware_freertos-kernel_extension_MIMXRT1052.cmake
View File

@ -1,10 +0,0 @@
if(NOT MIDDLEWARE_FREERTOS-KERNEL_EXTENSION_MIMXRT1052_INCLUDED)
set(MIDDLEWARE_FREERTOS-KERNEL_EXTENSION_MIMXRT1052_INCLUDED true CACHE BOOL "middleware_freertos-kernel_extension component is included.")
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/include
)
endif()

12
freertos/middleware_freertos-kernel_heap_4_MIMXRT1052.cmake
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@ -1,12 +0,0 @@
if(NOT MIDDLEWARE_FREERTOS-KERNEL_HEAP_4_MIMXRT1052_INCLUDED)
set(MIDDLEWARE_FREERTOS-KERNEL_HEAP_4_MIMXRT1052_INCLUDED true CACHE BOOL "middleware_freertos-kernel_heap_4 component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/freertos_kernel/portable/MemMang/heap_4.c
)
include(middleware_freertos-kernel_MIMXRT1052)
endif()

36
imxrt1050.cfg Normal file
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@ -0,0 +1,36 @@
# NXP i.MX RT1050 family (Arm Cortex-M7 @ 600 MHz)
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imxrt1050
}
source [find target/swj-dp.tcl]
if { [info exists CPU_SWD_TAPID] } {
set _CPU_SWD_TAPID $CPU_SWD_TAPID
} else {
set _CPU_SWD_TAPID 0x0bd11477
}
if { [using_jtag] } {
set _CPU_TAPID 0
} else {
set _CPU_TAPID $_CPU_SWD_TAPID
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
set _TARGETNAME $_CHIPNAME
dap create $_TARGETNAME.dap -chain-position $_TARGETNAME.cpu
target create $_TARGETNAME cortex_m -dap $_TARGETNAME.dap
# $_TARGETNAME configure -rtos auto
cortex_m reset_config sysresetreq
gdb_breakpoint_override hard
adapter speed 8000

24
middleware/fatfs/LICENSE.txt Normal file
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@ -0,0 +1,24 @@
FatFs License
FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files.
/*----------------------------------------------------------------------------/
/ FatFs - Generic FAT Filesystem Module Rx.xx /
/-----------------------------------------------------------------------------/
/
/ Copyright (C) 20xx, ChaN, all right reserved.
/
/ FatFs module is an open source software. Redistribution and use of FatFs in
/ source and binary forms, with or without modification, are permitted provided
/ that the following condition is met:
/
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/----------------------------------------------------------------------------*/
Therefore FatFs license is one of the BSD-style licenses but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, does not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses including GNU GPL. When you redistribute the FatFs source code with any changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license.

340
middleware/fatfs/source/00history.txt Normal file
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@ -0,0 +1,340 @@
----------------------------------------------------------------------------
Revision history of FatFs module
----------------------------------------------------------------------------
R0.00 (February 26, 2006)
Prototype.
R0.01 (April 29, 2006)
The first release.
R0.02 (June 01, 2006)
Added FAT12 support.
Removed unbuffered mode.
Fixed a problem on small (<32M) partition.
R0.02a (June 10, 2006)
Added a configuration option (_FS_MINIMUM).
R0.03 (September 22, 2006)
Added f_rename().
Changed option _FS_MINIMUM to _FS_MINIMIZE.
R0.03a (December 11, 2006)
Improved cluster scan algorithm to write files fast.
Fixed f_mkdir() creates incorrect directory on FAT32.
R0.04 (February 04, 2007)
Added f_mkfs().
Supported multiple drive system.
Changed some interfaces for multiple drive system.
Changed f_mountdrv() to f_mount().
R0.04a (April 01, 2007)
Supported multiple partitions on a physical drive.
Added a capability of extending file size to f_lseek().
Added minimization level 3.
Fixed an endian sensitive code in f_mkfs().
R0.04b (May 05, 2007)
Added a configuration option _USE_NTFLAG.
Added FSINFO support.
Fixed DBCS name can result FR_INVALID_NAME.
Fixed short seek (<= csize) collapses the file object.
R0.05 (August 25, 2007)
Changed arguments of f_read(), f_write() and f_mkfs().
Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
Fixed f_mkdir() on FAT32 creates incorrect directory.
R0.05a (February 03, 2008)
Added f_truncate() and f_utime().
Fixed off by one error at FAT sub-type determination.
Fixed btr in f_read() can be mistruncated.
Fixed cached sector is not flushed when create and close without write.
R0.06 (April 01, 2008)
Added fputc(), fputs(), fprintf() and fgets().
Improved performance of f_lseek() on moving to the same or following cluster.
R0.07 (April 01, 2009)
Merged Tiny-FatFs as a configuration option. (_FS_TINY)
Added long file name feature. (_USE_LFN)
Added multiple code page feature. (_CODE_PAGE)
Added re-entrancy for multitask operation. (_FS_REENTRANT)
Added auto cluster size selection to f_mkfs().
Added rewind option to f_readdir().
Changed result code of critical errors.
Renamed string functions to avoid name collision.
R0.07a (April 14, 2009)
Septemberarated out OS dependent code on reentrant cfg.
Added multiple sector size feature.
R0.07c (June 21, 2009)
Fixed f_unlink() can return FR_OK on error.
Fixed wrong cache control in f_lseek().
Added relative path feature.
Added f_chdir() and f_chdrive().
Added proper case conversion to extended character.
R0.07e (November 03, 2009)
Septemberarated out configuration options from ff.h to ffconf.h.
Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
Fixed name matching error on the 13 character boundary.
Added a configuration option, _LFN_UNICODE.
Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
R0.08 (May 15, 2010)
Added a memory configuration option. (_USE_LFN = 3)
Added file lock feature. (_FS_SHARE)
Added fast seek feature. (_USE_FASTSEEK)
Changed some types on the API, XCHAR->TCHAR.
Changed .fname in the FILINFO structure on Unicode cfg.
String functions support UTF-8 encoding files on Unicode cfg.
R0.08a (August 16, 2010)
Added f_getcwd(). (_FS_RPATH = 2)
Added sector erase feature. (_USE_ERASE)
Moved file lock semaphore table from fs object to the bss.
Fixed f_mkfs() creates wrong FAT32 volume.
R0.08b (January 15, 2011)
Fast seek feature is also applied to f_read() and f_write().
f_lseek() reports required table size on creating CLMP.
Extended format syntax of f_printf().
Ignores duplicated directory separators in given path name.
R0.09 (September 06, 2011)
f_mkfs() supports multiple partition to complete the multiple partition feature.
Added f_fdisk().
R0.09a (August 27, 2012)
Changed f_open() and f_opendir() reject null object pointer to avoid crash.
Changed option name _FS_SHARE to _FS_LOCK.
Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
R0.09b (January 24, 2013)
Added f_setlabel() and f_getlabel().
R0.10 (October 02, 2013)
Added selection of character encoding on the file. (_STRF_ENCODE)
Added f_closedir().
Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
Added forced mount feature with changes of f_mount().
Improved behavior of volume auto detection.
Improved write throughput of f_puts() and f_printf().
Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
Fixed f_write() can be truncated when the file size is close to 4GB.
Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error.
R0.10a (January 15, 2014)
Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
Added a configuration option of minimum sector size. (_MIN_SS)
2nd argument of f_rename() can have a drive number and it will be ignored.
Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10)
Fixed f_close() invalidates the file object without volume lock.
Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10)
Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07)
R0.10b (May 19, 2014)
Fixed a hard error in the disk I/O layer can collapse the directory entry.
Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07)
R0.10c (November 09, 2014)
Added a configuration option for the platforms without RTC. (_FS_NORTC)
Changed option name _USE_ERASE to _USE_TRIM.
Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
Fixed a potential problem of FAT access that can appear on disk error.
Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
R0.11 (February 09, 2015)
Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND)
Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
R0.11a (September 05, 2015)
Fixed wrong media change can lead a deadlock at thread-safe configuration.
Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
Fixed errors in the case conversion teble of Unicode (cc*.c).
R0.12 (April 12, 2016)
Added support for exFAT file system. (_FS_EXFAT)
Added f_expand(). (_USE_EXPAND)
Changed some members in FINFO structure and behavior of f_readdir().
Added an option _USE_CHMOD.
Removed an option _WORD_ACCESS.
Fixed errors in the case conversion table of Unicode (cc*.c).
R0.12a (July 10, 2016)
Added support for creating exFAT volume with some changes of f_mkfs().
Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed.
f_forward() is available regardless of _FS_TINY.
Fixed f_mkfs() creates wrong volume. (appeared at R0.12)
Fixed wrong memory read in create_name(). (appeared at R0.12)
Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
R0.12b (September 04, 2016)
Made f_rename() be able to rename objects with the same name but case.
Fixed an error in the case conversion teble of code page 866. (ff.c)
Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12)
Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12)
R0.12c (March 04, 2017)
Improved write throughput at the fragmented file on the exFAT volume.
Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12)
Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
R0.13 (May 21, 2017)
Changed heading character of configuration keywords "_" to "FF_".
Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead.
Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0)
Improved cluster allocation time on stretch a deep buried cluster chain.
Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3.
Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
R0.13a (October 14, 2017)
Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF).
Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk().
Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09)
Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12)
R0.13b (April 07, 2018)
Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2)
Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b)
R0.13c (October 14, 2018)
Supported stdint.h for C99 and later. (integer.h was included in ff.h)
Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)
Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
R0.14 (October 14, 2019)
Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1)
Changed some API functions, f_mkfs() and f_fdisk().
Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters.
Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12)
Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12)

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FatFs Module Source Files R0.14
FILES
00readme.txt This file.
00history.txt Revision history.
ff.c FatFs module.
ffconf.h Configuration file of FatFs module.
ff.h Common include file for FatFs and application module.
diskio.h Common include file for FatFs and disk I/O module.
diskio.c An example of glue function to attach existing disk I/O module to FatFs.
ffunicode.c Optional Unicode utility functions.
ffsystem.c An example of optional O/S related functions.
Low level disk I/O module is not included in this archive because the FatFs
module is only a generic file system layer and it does not depend on any specific
storage device. You need to provide a low level disk I/O module written to
control the storage device that attached to the target system.

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*-----------------------------------------------------------------------*/
/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2019 */
/*-----------------------------------------------------------------------*/
/* If a working storage control module is available, it should be */
/* attached to the FatFs via a glue function rather than modifying it. */
/* This is an example of glue functions to attach various exsisting */
/* storage control modules to the FatFs module with a defined API. */
/*-----------------------------------------------------------------------*/
#include "ffconf.h" /* FatFs configuration options */
#include "ff.h" /* Obtains integer types */
#include "diskio.h" /* Declarations of disk functions */
#ifdef RAM_DISK_ENABLE
#include "fsl_ram_disk.h"
#endif
#ifdef USB_DISK_ENABLE
#include "fsl_usb_disk.h"
#endif
#ifdef SD_DISK_ENABLE
#include "fsl_sd_disk.h"
#endif
#ifdef MMC_DISK_ENABLE
#include "fsl_mmc_disk.h"
#endif
#ifdef SDSPI_DISK_ENABLE
#include "fsl_sdspi_disk.h"
#endif
#ifdef NAND_DISK_ENABLE
#include "fsl_nand_disk.h"
#endif
/*-----------------------------------------------------------------------*/
/* Get Drive Status */
/*-----------------------------------------------------------------------*/
DSTATUS disk_status (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
DSTATUS stat;
switch (pdrv)
{
#ifdef RAM_DISK_ENABLE
case RAMDISK:
stat = ram_disk_status(pdrv);
return stat;
#endif
#ifdef USB_DISK_ENABLE
case USBDISK:
stat = USB_HostMsdGetDiskStatus(pdrv);
return stat;
#endif
#ifdef SD_DISK_ENABLE
case SDDISK:
stat = sd_disk_status(pdrv);
return stat;
#endif
#ifdef MMC_DISK_ENABLE
case MMCDISK:
stat = mmc_disk_status(pdrv);
return stat;
#endif
#ifdef SDSPI_DISK_ENABLE
case SDSPIDISK:
stat = sdspi_disk_status(pdrv);
return stat;
#endif
#ifdef NAND_DISK_ENABLE
case NANDDISK:
stat = nand_disk_status(pdrv);
return stat;
#endif
default:
break;
}
return STA_NOINIT;
}
/*-----------------------------------------------------------------------*/
/* Inidialize a Drive */
/*-----------------------------------------------------------------------*/
DSTATUS disk_initialize (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
DSTATUS stat;
switch (pdrv)
{
#ifdef RAM_DISK_ENABLE
case RAMDISK:
stat = ram_disk_initialize(pdrv);
return stat;
#endif
#ifdef USB_DISK_ENABLE
case USBDISK:
stat = USB_HostMsdInitializeDisk(pdrv);
return stat;
#endif
#ifdef SD_DISK_ENABLE
case SDDISK:
stat = sd_disk_initialize(pdrv);
return stat;
#endif
#ifdef MMC_DISK_ENABLE
case MMCDISK:
stat = mmc_disk_initialize(pdrv);
return stat;
#endif
#ifdef SDSPI_DISK_ENABLE
case SDSPIDISK:
stat = sdspi_disk_initialize(pdrv);
return stat;
#endif
#ifdef NAND_DISK_ENABLE
case NANDDISK:
stat = nand_disk_initialize(pdrv);
return stat;
#endif
default:
break;
}
return STA_NOINIT;
}
/*-----------------------------------------------------------------------*/
/* Read Sector(s) */
/*-----------------------------------------------------------------------*/
DRESULT disk_read (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
BYTE *buff, /* Data buffer to store read data */
LBA_t sector, /* Start sector in LBA */
UINT count /* Number of sectors to read */
)
{
DRESULT res;
switch (pdrv)
{
#ifdef RAM_DISK_ENABLE
case RAMDISK:
res = ram_disk_read(pdrv, buff, sector, count);
return res;
#endif
#ifdef USB_DISK_ENABLE
case USBDISK:
res = USB_HostMsdReadDisk(pdrv, buff, sector, count);
return res;
#endif
#ifdef SD_DISK_ENABLE
case SDDISK:
res = sd_disk_read(pdrv, buff, sector, count);
return res;
#endif
#ifdef MMC_DISK_ENABLE
case MMCDISK:
res = mmc_disk_read(pdrv, buff, sector, count);
return res;
#endif
#ifdef SDSPI_DISK_ENABLE
case SDSPIDISK:
res = sdspi_disk_read(pdrv, buff, sector, count);
return res;
#endif
#ifdef NAND_DISK_ENABLE
case NANDDISK:
res = nand_disk_read(pdrv, buff, sector, count);
return res;
#endif
default:
break;
}
return RES_PARERR;
}
/*-----------------------------------------------------------------------*/
/* Write Sector(s) */
/*-----------------------------------------------------------------------*/
#if FF_FS_READONLY == 0
DRESULT disk_write (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
const BYTE *buff, /* Data to be written */
LBA_t sector, /* Start sector in LBA */
UINT count /* Number of sectors to write */
)
{
DRESULT res;
switch (pdrv)
{
#ifdef RAM_DISK_ENABLE
case RAMDISK:
res = ram_disk_write(pdrv, buff, sector, count);
return res;
#endif
#ifdef USB_DISK_ENABLE
case USBDISK:
res = USB_HostMsdWriteDisk(pdrv, buff, sector, count);
return res;
#endif
#ifdef SD_DISK_ENABLE
case SDDISK:
res = sd_disk_write(pdrv, buff, sector, count);
return res;
#endif
#ifdef MMC_DISK_ENABLE
case MMCDISK:
res = mmc_disk_write(pdrv, buff, sector, count);
return res;
#endif
#ifdef SDSPI_DISK_ENABLE
case SDSPIDISK:
res = sdspi_disk_write(pdrv, buff, sector, count);
return res;
#endif
#ifdef NAND_DISK_ENABLE
case NANDDISK:
res = nand_disk_write(pdrv, buff, sector, count);
return res;
#endif
default:
break;
}
return RES_PARERR;
}
#endif
/*-----------------------------------------------------------------------*/
/* Miscellaneous Functions */
/*-----------------------------------------------------------------------*/
DRESULT disk_ioctl (
BYTE pdrv, /* Physical drive nmuber (0..) */
BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive control data */
)
{
DRESULT res;
switch (pdrv)
{
#ifdef RAM_DISK_ENABLE
case RAMDISK:
res = ram_disk_ioctl(pdrv, cmd, buff);
return res;
#endif
#ifdef USB_DISK_ENABLE
case USBDISK:
res = USB_HostMsdIoctlDisk(pdrv, cmd, buff);
return res;
#endif
#ifdef SD_DISK_ENABLE
case SDDISK:
res = sd_disk_ioctl(pdrv, cmd, buff);
return res;
#endif
#ifdef MMC_DISK_ENABLE
case MMCDISK:
res = mmc_disk_ioctl(pdrv, cmd, buff);
return res;
#endif
#ifdef SDSPI_DISK_ENABLE
case SDSPIDISK:
res = sdspi_disk_ioctl(pdrv, cmd, buff);
return res;
#endif
#ifdef NAND_DISK_ENABLE
case NANDDISK:
res = nand_disk_ioctl(pdrv, cmd, buff);
return res;
#endif
default:
break;
}
return RES_PARERR;
}

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/*-----------------------------------------------------------------------/
/ Low level disk interface modlue include file (C)ChaN, 2019 /
/-----------------------------------------------------------------------*/
#ifndef _DISKIO_DEFINED
#define _DISKIO_DEFINED
#ifdef __cplusplus
extern "C" {
#endif
/* Definitions of physical drive number for each drive */
#define RAMDISK 0 /* Example: ram disk to physical drive 0 */
#define USBDISK 1 /* usb disk to physical drive 1 */
#define SDDISK 2 /* sd disk to physical drive 2 */
#define MMCDISK 3 /* mmc disk to physical drive 3 */
#define SDSPIDISK 4 /* sdspi disk to physical drive 4 */
#define NANDDISK 5 /* nand disk to physical drive 5 */
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*---------------------------------------*/
/* Prototypes for disk control functions */
DSTATUS disk_initialize (BYTE pdrv);
DSTATUS disk_status (BYTE pdrv);
DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (Used by FatFs) */
#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
/* Generic command (Not used by FatFs) */
#define CTRL_POWER 5 /* Get/Set power status */
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
#define CTRL_EJECT 7 /* Eject media */
#define CTRL_FORMAT 8 /* Create physical format on the media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10 /* Get card type */
#define MMC_GET_CSD 11 /* Get CSD */
#define MMC_GET_CID 12 /* Get CID */
#define MMC_GET_OCR 13 /* Get OCR */
#define MMC_GET_SDSTAT 14 /* Get SD status */
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20 /* Get F/W revision */
#define ATA_GET_MODEL 21 /* Get model name */
#define ATA_GET_SN 22 /* Get serial number */
#ifdef __cplusplus
}
#endif
#endif

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/*----------------------------------------------------------------------------/
/ FatFs - Generic FAT Filesystem module R0.14 /
/-----------------------------------------------------------------------------/
/
/ Copyright (C) 2019, ChaN, all right reserved.
/
/ FatFs module is an open source software. Redistribution and use of FatFs in
/ source and binary forms, with or without modification, are permitted provided
/ that the following condition is met:
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/
/----------------------------------------------------------------------------*/
#ifndef FF_DEFINED
#define FF_DEFINED 86606 /* Revision ID */
#ifdef __cplusplus
extern "C" {
#endif
#include "ffconf.h" /* FatFs configuration options */
#if FF_DEFINED != FFCONF_DEF
#error Wrong configuration file (ffconf.h).
#endif
/* Integer types used for FatFs API */
#if defined(_WIN32) /* Main development platform */
#define FF_INTDEF 2
#include <windows.h>
typedef unsigned __int64 QWORD;
#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */
#define FF_INTDEF 2
#include <stdint.h>
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */
typedef uint16_t WORD; /* 16-bit unsigned integer */
typedef uint32_t DWORD; /* 32-bit unsigned integer */
typedef uint64_t QWORD; /* 64-bit unsigned integer */
typedef WORD WCHAR; /* UTF-16 character type */
#else /* Earlier than C99 */
#define FF_INTDEF 1
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */
typedef unsigned short WORD; /* 16-bit unsigned integer */
typedef unsigned long DWORD; /* 32-bit unsigned integer */
typedef WORD WCHAR; /* UTF-16 character type */
#endif
/* Definitions of volume management */
#if FF_MULTI_PARTITION /* Multiple partition configuration */
typedef struct {
BYTE pd; /* Physical drive number */
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
} PARTITION;
extern PARTITION VolToPart[]; /* Volume - Partition mapping table */
#endif
#if FF_STR_VOLUME_ID
#ifndef FF_VOLUME_STRS
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
#endif
#endif
/* Type of path name strings on FatFs API */
#ifndef _INC_TCHAR
#define _INC_TCHAR
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
typedef WCHAR TCHAR;
#define _T(x) L ## x
#define _TEXT(x) L ## x
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
typedef char TCHAR;
#define _T(x) u8 ## x
#define _TEXT(x) u8 ## x
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
typedef DWORD TCHAR;
#define _T(x) U ## x
#define _TEXT(x) U ## x
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
#error Wrong FF_LFN_UNICODE setting
#else /* ANSI/OEM code in SBCS/DBCS */
typedef char TCHAR;
#define _T(x) x
#define _TEXT(x) x
#endif
#endif
/* Type of file size and LBA variables */
#if FF_FS_EXFAT
#if FF_INTDEF != 2
#error exFAT feature wants C99 or later
#endif
typedef QWORD FSIZE_t;
#if FF_LBA64
typedef QWORD LBA_t;
#else
typedef DWORD LBA_t;
#endif
#else
#if FF_LBA64
#error exFAT needs to be enabled when enable 64-bit LBA
#endif
typedef DWORD FSIZE_t;
typedef DWORD LBA_t;
#endif
/* Filesystem object structure (FATFS) */
typedef struct {
BYTE fs_type; /* Filesystem type (0:not mounted) */
BYTE pdrv; /* Associated physical drive */
BYTE n_fats; /* Number of FATs (1 or 2) */
BYTE wflag; /* win[] flag (b0:dirty) */
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
WORD id; /* Volume mount ID */
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
WORD csize; /* Cluster size [sectors] */
#if FF_MAX_SS != FF_MIN_SS
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
#endif
#if FF_USE_LFN
WCHAR* lfnbuf; /* LFN working buffer */
#endif
#if FF_FS_EXFAT
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
#endif
#if FF_FS_REENTRANT
FF_SYNC_t sobj; /* Identifier of sync object */
#endif
#if !FF_FS_READONLY
DWORD last_clst; /* Last allocated cluster */
DWORD free_clst; /* Number of free clusters */
#endif
#if FF_FS_RPATH
DWORD cdir; /* Current directory start cluster (0:root) */
#if FF_FS_EXFAT
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
#endif
#endif
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
DWORD fsize; /* Size of an FAT [sectors] */
LBA_t volbase; /* Volume base sector */
LBA_t fatbase; /* FAT base sector */
LBA_t dirbase; /* Root directory base sector/cluster */
LBA_t database; /* Data base sector */
#if FF_FS_EXFAT
LBA_t bitbase; /* Allocation bitmap base sector */
#endif
LBA_t winsect; /* Current sector appearing in the win[] */
BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
} FATFS;
/* Object ID and allocation information (FFOBJID) */
typedef struct {
FATFS* fs; /* Pointer to the hosting volume of this object */
WORD id; /* Hosting volume mount ID */
BYTE attr; /* Object attribute */
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
#if FF_FS_EXFAT
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
#endif
#if FF_FS_LOCK
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
#endif
} FFOBJID;
/* File object structure (FIL) */
typedef struct {
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
BYTE flag; /* File status flags */
BYTE err; /* Abort flag (error code) */
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */
#if !FF_FS_READONLY
LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
#endif
#if FF_USE_FASTSEEK
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
#endif
#if !FF_FS_TINY
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
#endif
} FIL;
/* Directory object structure (DIR) */
typedef struct {
FFOBJID obj; /* Object identifier */
DWORD dptr; /* Current read/write offset */
DWORD clust; /* Current cluster */
LBA_t sect; /* Current sector (0:Read operation has terminated) */
BYTE* dir; /* Pointer to the directory item in the win[] */
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
#if FF_USE_LFN
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
#endif
#if FF_USE_FIND
const TCHAR* pat; /* Pointer to the name matching pattern */
#endif
} DIR;
/* File information structure (FILINFO) */
typedef struct {
FSIZE_t fsize; /* File size */
WORD fdate; /* Modified date */
WORD ftime; /* Modified time */
BYTE fattrib; /* File attribute */
#if FF_USE_LFN
TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
#else
TCHAR fname[12 + 1]; /* File name */
#endif
} FILINFO;
/* Format parameter structure (MKFS_PARM) */
typedef struct {
BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
BYTE n_fat; /* Number of FATs */
UINT align; /* Data area alignment (sector) */
UINT n_root; /* Number of root directory entries */
DWORD au_size; /* Cluster size (byte) */
} MKFS_PARM;
/* File function return code (FRESULT) */
typedef enum {
FR_OK = 0, /* (0) Succeeded */
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
FR_INT_ERR, /* (2) Assertion failed */
FR_NOT_READY, /* (3) The physical drive cannot work */
FR_NO_FILE, /* (4) Could not find the file */
FR_NO_PATH, /* (5) Could not find the path */
FR_INVALID_NAME, /* (6) The path name format is invalid */
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
FR_EXIST, /* (8) Access denied due to prohibited access */
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
FR_NOT_ENABLED, /* (12) The volume has no work area */
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
} FRESULT;
/*--------------------------------------------------------------*/
/* FatFs module application interface */
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
FRESULT f_close (FIL* fp); /* Close an open file object */
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
FRESULT f_truncate (FIL* fp); /* Truncate the file */
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
FRESULT f_closedir (DIR* dp); /* Close an open directory */
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */
FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */
FRESULT f_setcp (WORD cp); /* Set current code page */
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
#define f_error(fp) ((fp)->err)
#define f_tell(fp) ((fp)->fptr)
#define f_size(fp) ((fp)->obj.objsize)
#define f_rewind(fp) f_lseek((fp), 0)
#define f_rewinddir(dp) f_readdir((dp), 0)
#define f_rmdir(path) f_unlink(path)
#define f_unmount(path) f_mount(0, path, 0)
#ifndef EOF
#define EOF (-1)
#endif
/*--------------------------------------------------------------*/
/* Additional user defined functions */
/* RTC function */
#if !FF_FS_READONLY && !FF_FS_NORTC
DWORD get_fattime (void);
#endif
/* LFN support functions */
#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
#endif
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
void* ff_memalloc (UINT msize); /* Allocate memory block */
void ff_memfree (void* mblock); /* Free memory block */
#endif
/* Sync functions */
#if FF_FS_REENTRANT
int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
#endif
/*--------------------------------------------------------------*/
/* Flags and offset address */
/* File access mode and open method flags (3rd argument of f_open) */
#define FA_READ 0x01
#define FA_WRITE 0x02
#define FA_OPEN_EXISTING 0x00
#define FA_CREATE_NEW 0x04
#define FA_CREATE_ALWAYS 0x08
#define FA_OPEN_ALWAYS 0x10
#define FA_OPEN_APPEND 0x30
/* Fast seek controls (2nd argument of f_lseek) */
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
/* Format options (2nd argument of f_mkfs) */
#define FM_FAT 0x01
#define FM_FAT32 0x02
#define FM_EXFAT 0x04
#define FM_ANY 0x07
#define FM_SFD 0x08
/* Filesystem type (FATFS.fs_type) */
#define FS_FAT12 1
#define FS_FAT16 2
#define FS_FAT32 3
#define FS_EXFAT 4
/* File attribute bits for directory entry (FILINFO.fattrib) */
#define AM_RDO 0x01 /* Read only */
#define AM_HID 0x02 /* Hidden */
#define AM_SYS 0x04 /* System */
#define AM_DIR 0x10 /* Directory */
#define AM_ARC 0x20 /* Archive */
#ifdef __cplusplus
}
#endif
#endif /* FF_DEFINED */

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/*---------------------------------------------------------------------------/
/ FatFs Functional Configurations
/---------------------------------------------------------------------------*/
#define FFCONF_DEF 86606 /* Revision ID */
/*---------------------------------------------------------------------------/
/ Function Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_READONLY 0
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: Basic functions are fully enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
/ are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define FF_USE_STRFUNC 0
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
/
/ 0: Disable string functions.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion. */
#define FF_USE_FIND 0
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#define FF_USE_MKFS 0
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define FF_USE_FASTSEEK 0
/* This option switches fast seek function. (0:Disable or 1:Enable) */
#define FF_USE_EXPAND 0
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#define FF_USE_CHMOD 0
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
#define FF_USE_LABEL 0
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define FF_USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define FF_CODE_PAGE 932
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect code page setting can cause a file open failure.
/
/ 437 - U.S.
/ 720 - Arabic
/ 737 - Greek
/ 771 - KBL
/ 775 - Baltic
/ 850 - Latin 1
/ 852 - Latin 2
/ 855 - Cyrillic
/ 857 - Turkish
/ 860 - Portuguese
/ 861 - Icelandic
/ 862 - Hebrew
/ 863 - Canadian French
/ 864 - Arabic
/ 865 - Nordic
/ 866 - Russian
/ 869 - Greek 2
/ 932 - Japanese (DBCS)
/ 936 - Simplified Chinese (DBCS)
/ 949 - Korean (DBCS)
/ 950 - Traditional Chinese (DBCS)
/ 0 - Include all code pages above and configured by f_setcp()
*/
#define FF_USE_LFN 0
#define FF_MAX_LFN 255
/* The FF_USE_LFN switches the support for LFN (long file name).
/
/ 0: Disable LFN. FF_MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
/ specification.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
#define FF_LFN_UNICODE 0
/* This option switches the character encoding on the API when LFN is enabled.
/
/ 0: ANSI/OEM in current CP (TCHAR = char)
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
/ 2: Unicode in UTF-8 (TCHAR = char)
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
/
/ Also behavior of string I/O functions will be affected by this option.
/ When LFN is not enabled, this option has no effect. */
#define FF_LFN_BUF 255
#define FF_SFN_BUF 12
/* This set of options defines size of file name members in the FILINFO structure
/ which is used to read out directory items. These values should be suffcient for
/ the file names to read. The maximum possible length of the read file name depends
/ on character encoding. When LFN is not enabled, these options have no effect. */
#define FF_STRF_ENCODE 3
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
/ This option selects assumption of character encoding ON THE FILE to be
/ read/written via those functions.
/
/ 0: ANSI/OEM in current CP
/ 1: Unicode in UTF-16LE
/ 2: Unicode in UTF-16BE
/ 3: Unicode in UTF-8
*/
#define FF_FS_RPATH 0
/* This option configures support for relative path.
/
/ 0: Disable relative path and remove related functions.
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
*/
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#define FF_VOLUMES 1
/* Number of volumes (logical drives) to be used. (1-10) */
#define FF_STR_VOLUME_ID 0
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
/ not defined, a user defined volume string table needs to be defined as:
/
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
*/
#define FF_MULTI_PARTITION 0
/* This option switches support for multiple volumes on the physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
/ When this function is enabled (1), each logical drive number can be bound to
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
/ funciton will be available. */
#define FF_MIN_SS 512
#define FF_MAX_SS 512
/* This set of options configures the range of sector size to be supported. (512,
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
/ harddisk. But a larger value may be required for on-board flash memory and some
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
/ for variable sector size mode and disk_ioctl() function needs to implement
/ GET_SECTOR_SIZE command. */
#define FF_LBA64 0
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
#define FF_MIN_GPT 0x100000000
/* Minimum number of sectors to switch GPT format to create partition in f_mkfs and
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
#define FF_USE_TRIM 0
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
#define FF_FS_EXFAT 0
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
#define FF_FS_NORTC 0
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2019
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_NOFSINFO 0
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
#define FF_FS_LOCK 0
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
/ is 1.
/
/ 0: Disable file lock function. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock function. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock control is independent of re-entrancy. */
/* #include <somertos.h> // O/S definitions */
#define FF_FS_REENTRANT 0
#define FF_FS_TIMEOUT 1000
#define FF_SYNC_t HANDLE
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this function.
/
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function, must be added to the project. Samples are available in
/ option/syscall.c.
/
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
/ included somewhere in the scope of ff.h. */
/*--- End of configuration options ---*/

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/*------------------------------------------------------------------------*/
/* Sample Code of OS Dependent Functions for FatFs */
/* (C)ChaN, 2018 */
/*------------------------------------------------------------------------*/
#include "ff.h"
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
#ifdef FSL_RTOS_FREE_RTOS
#include "FreeRTOS.h"
#endif
/*------------------------------------------------------------------------*/
/* Allocate a memory block */
/*------------------------------------------------------------------------*/
void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */
UINT msize /* Number of bytes to allocate */
)
{
#ifdef FSL_RTOS_FREE_RTOS
return pvPortMalloc(msize);
#else
return malloc(msize); /* Allocate a new memory block with POSIX API */
#endif
}
/*------------------------------------------------------------------------*/
/* Free a memory block */
/*------------------------------------------------------------------------*/
void ff_memfree (
void* mblock /* Pointer to the memory block to free (nothing to do if null) */
)
{
#ifdef FSL_RTOS_FREE_RTOS
vPortFree(mblock);
#else
free(mblock); /* Free the memory block with POSIX API */
#endif
}
#endif
#if FF_FS_REENTRANT /* Mutal exclusion */
/*------------------------------------------------------------------------*/
/* Create a Synchronization Object */
/*------------------------------------------------------------------------*/
/* This function is called in f_mount() function to create a new
/ synchronization object for the volume, such as semaphore and mutex.
/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
*/
//const osMutexDef_t Mutex[FF_VOLUMES]; /* Table of CMSIS-RTOS mutex */
int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
BYTE vol, /* Corresponding volume (logical drive number) */
FF_SYNC_t* sobj /* Pointer to return the created sync object */
)
{
/* Win32 */
// *sobj = CreateMutex(NULL, FALSE, NULL);
// return (int)(*sobj != INVALID_HANDLE_VALUE);
/* uITRON */
// T_CSEM csem = {TA_TPRI,1,1};
// *sobj = acre_sem(&csem);
// return (int)(*sobj > 0);
/* uC/OS-II */
// OS_ERR err;
// *sobj = OSMutexCreate(0, &err);
// return (int)(err == OS_NO_ERR);
/* FreeRTOS */
*sobj = xSemaphoreCreateMutex();
return (int)(*sobj != NULL);
/* CMSIS-RTOS */
// *sobj = osMutexCreate(&Mutex[vol]);
// return (int)(*sobj != NULL);
}
/*------------------------------------------------------------------------*/
/* Delete a Synchronization Object */
/*------------------------------------------------------------------------*/
/* This function is called in f_mount() function to delete a synchronization
/ object that created with ff_cre_syncobj() function. When a 0 is returned,
/ the f_mount() function fails with FR_INT_ERR.
*/
int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
)
{
/* Win32 */
// return (int)CloseHandle(sobj);
/* uITRON */
// return (int)(del_sem(sobj) == E_OK);
/* uC/OS-II */
// OS_ERR err;
// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
// return (int)(err == OS_NO_ERR);
/* FreeRTOS */
vSemaphoreDelete(sobj);
return 1;
/* CMSIS-RTOS */
// return (int)(osMutexDelete(sobj) == osOK);
}
/*------------------------------------------------------------------------*/
/* Request Grant to Access the Volume */
/*------------------------------------------------------------------------*/
/* This function is called on entering file functions to lock the volume.
/ When a 0 is returned, the file function fails with FR_TIMEOUT.
*/
int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
FF_SYNC_t sobj /* Sync object to wait */
)
{
/* Win32 */
// return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
/* uITRON */
// return (int)(wai_sem(sobj) == E_OK);
/* uC/OS-II */
// OS_ERR err;
// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
// return (int)(err == OS_NO_ERR);
/* FreeRTOS */
return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
/* CMSIS-RTOS */
// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
}
/*------------------------------------------------------------------------*/
/* Release Grant to Access the Volume */
/*------------------------------------------------------------------------*/
/* This function is called on leaving file functions to unlock the volume.
*/
void ff_rel_grant (
FF_SYNC_t sobj /* Sync object to be signaled */
)
{
/* Win32 */
// ReleaseMutex(sobj);
/* uITRON */
// sig_sem(sobj);
/* uC/OS-II */
// OSMutexPost(sobj);
/* FreeRTOS */
xSemaphoreGive(sobj);
/* CMSIS-RTOS */
// osMutexRelease(sobj);
}
#endif

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "ffconf.h"
/* This fatfs subcomponent is disabled by default
* To enable it, define following macro in ffconf.h */
#ifdef SD_DISK_ENABLE
#include <assert.h>
#include <stdio.h>
#include <string.h>
#include "fsl_sd_disk.h"
/*******************************************************************************
* Definitons
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Card descriptor */
sd_card_t g_sd;
/*******************************************************************************
* Code
******************************************************************************/
DRESULT sd_disk_write(BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count)
{
if (pdrv != SDDISK)
{
return RES_PARERR;
}
if (kStatus_Success != SD_WriteBlocks(&g_sd, buff, sector, count))
{
return RES_ERROR;
}
return RES_OK;
}
DRESULT sd_disk_read(BYTE pdrv, BYTE* buff, LBA_t sector, UINT count)
{
if (pdrv != SDDISK)
{
return RES_PARERR;
}
if (kStatus_Success != SD_ReadBlocks(&g_sd, buff, sector, count))
{
return RES_ERROR;
}
return RES_OK;
}
DRESULT sd_disk_ioctl(BYTE pdrv, BYTE cmd, void* buff)
{
DRESULT result = RES_OK;
if (pdrv != SDDISK)
{
return RES_PARERR;
}
switch (cmd)
{
case GET_SECTOR_COUNT:
if (buff)
{
*(uint32_t *)buff = g_sd.blockCount;
}
else
{
result = RES_PARERR;
}
break;
case GET_SECTOR_SIZE:
if (buff)
{
*(uint32_t *)buff = g_sd.blockSize;
}
else
{
result = RES_PARERR;
}
break;
case GET_BLOCK_SIZE:
if (buff)
{
*(uint32_t *)buff = g_sd.csd.eraseSectorSize;
}
else
{
result = RES_PARERR;
}
break;
case CTRL_SYNC:
result = RES_OK;
break;
default:
result = RES_PARERR;
break;
}
return result;
}
DSTATUS sd_disk_status(BYTE pdrv)
{
if (pdrv != SDDISK)
{
return STA_NOINIT;
}
return 0;
}
DSTATUS sd_disk_initialize(BYTE pdrv)
{
if (pdrv != SDDISK)
{
return STA_NOINIT;
}
if (kStatus_Success != SD_Init(&g_sd))
{
SD_Deinit(&g_sd);
memset(&g_sd, 0U, sizeof(g_sd));
return STA_NOINIT;
}
return RES_OK;
}
#endif /* SD_DISK_ENABLE */

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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_SD_DISK_H_
#define _FSL_SD_DISK_H_
#include <stdint.h>
#include "ff.h"
#include "diskio.h"
#include "fsl_sd.h"
/*!
* @addtogroup SD Disk
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
#define CD_USING_GPIO
/*******************************************************************************
* Variables
******************************************************************************/
extern sd_card_t g_sd; /* sd card descriptor */
/*************************************************************************************************
* API
************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name SD Disk Function
* @{
*/
/*!
* @brief Initializes SD disk.
*
* @param pdrv Physical drive number.
* @retval STA_NOINIT Failed.
* @retval RES_OK Success.
*/
DSTATUS sd_disk_initialize(BYTE pdrv);
/*!
* Gets SD disk status
*
* @param pdrv Physical drive number.
* @retval STA_NOINIT Failed.
* @retval RES_OK Success.
*/
DSTATUS sd_disk_status(BYTE pdrv);
/*!
* @brief Reads SD disk.
*
* @param pdrv Physical drive number.
* @param buff The data buffer pointer to store read content.
* @param sector The start sector number to be read.
* @param count The sector count to be read.
* @retval RES_PARERR Failed.
* @retval RES_OK Success.
*/
DRESULT sd_disk_read(BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
/*!
* @brief Writes SD disk.
*
* @param pdrv Physical drive number.
* @param buff The data buffer pointer to store write content.
* @param sector The start sector number to be written.
* @param count The sector count to be written.
* @retval RES_PARERR Failed.
* @retval RES_OK Success.
*/
DRESULT sd_disk_write(BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
/*!
* @brief SD disk IO operation.
*
* @param pdrv Physical drive number.
* @param cmd The command to be set.
* @param buff The buffer to store command result.
* @retval RES_PARERR Failed.
* @retval RES_OK Success.
*/
DRESULT sd_disk_ioctl(BYTE pdrv, BYTE cmd, void* buff);
/* @} */
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_SD_DISK_H_ */

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Building lwIP
=============
lwIP uses a CMake based build system.
The CMake files in this project are designed to
be included into your own CMake files. They are
mainly variable definitions containing a list of
source files and predefined static libraries to
be linked against application code.
1) lwIP sources:
src/Filelists.cmake provides file lists containing
the lwIP core library.
The file also contains two static libraries, lwipcore
and lwipallapps, where you can link your app against.
This is the file that is useful to all lwIP users.
2) Example applications:
contrib/Filelists.cmake provides several file lists
containing the example applications.
The file also contains several static libraries
for these example apps.
This file is only useful for you, if you can use one
of the examples in your application, which is normally
not the case.
3) OS/platform port:
Usually the OS port needs to be provided by the user.
If a port to Linux, Windows or MacOS is useful for
you, you can use
contrib/ports/{win32, unix}/Filelists.cmake
that contains file lists and libraries for
these operating systems.
VARIABLES
=========
In all cases, you need to provide two variables.
"LWIP_DIR" pointing to the lwIP directory
Example:
set(LWIP_DIR ${CMAKE_CURRENT_SOURCE_DIR}/externals/lwip)
"LWIP_INCLUDE_DIRS" that contains the include base paths
- for lwIP itself (${LWIP_DIR}/src/include)
- for lwIP contrib if you use it (${LWIP_DIR}/contrib)
- to a directory containing an OS port
- to a directory containing lwipopts.h
Example:
set (LWIP_INCLUDE_DIRS
"${LWIP_DIR}/src/include"
"${LWIP_DIR}/contrib"
"${LWIP_DIR}/contrib/ports/unix/port/include"
"${LWIP_DIR}/contrib/examples/example_app"
)
Putting it all together
=======================
To get a working application, your CMake system
needs to provide the variables described above, e.g.
set (LWIP_DIR <path to lwip sources>)
set (LWIP_INCLUDE_DIRS
"${LWIP_DIR}/src/include"
"${LWIP_DIR}/contrib"
"<path to my port>/include"
"<path to lwipopts.h>"
)
You may add some defines:
set (LWIP_DEFINITIONS LWIP_DEBUG=1)
Then include the filelists you need:
include(${LWIP_DIR}/src/Filelists.cmake)
include(${LWIP_DIR}/contrib/Filelists.cmake)
Then, declare you executable:
add_executable(my_app <my source files> <my lwip port files>)
Add lwIP include dirs to your app:
target_include_directories(my_app PRIVATE ${LWIP_INCLUDE_DIRS})
Link your app against the lwIP libs from the filelists you need:
target_link_libraries(my_app lwipcontribapps lwipallapps lwipcore)
Working example
===============
Working build examples can be found in the
contrib/ports/{win32, unix}/example_app
subdirectory.
To use them, create a build directory and call cmake with
the lwIP root dir:
- mkdir build
- cd build
- cmake ..
- cmake --build .
The CMakeLists.txt will autoselect the correct port
for your system (supported: Linux, Windows, Darwin).
Makefile based build system
===========================
lwIP also maintains file lists for Makefile-based
build systems. Look for Filelists.mk files
in the source tree. We try to maintain them,
but lwIP's mainly focused build system is CMake.

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cmake_minimum_required(VERSION 3.10)
set (CMAKE_CONFIGURATION_TYPES "Debug;Release")
project(lwIP)
# Example lwIP application
set(LWIP_DIR ${CMAKE_CURRENT_SOURCE_DIR})
set (LWIP_DEFINITIONS LWIP_DEBUG=1)
if (${CMAKE_SYSTEM_NAME} STREQUAL "Windows")
add_subdirectory(${LWIP_DIR}/contrib/ports/win32/example_app)
elseif(${CMAKE_SYSTEM_NAME} STREQUAL "Linux" OR ${CMAKE_SYSTEM_NAME} STREQUAL "Darwin")
add_subdirectory(${LWIP_DIR}/contrib/ports/unix/example_app)
else()
message(WARNING "Host ${CMAKE_SYSTEM_NAME} is not supported to build example_app")
endif()
# Source package generation
set(CPACK_SOURCE_GENERATOR "ZIP")
set(CPACK_SOURCE_PACKAGE_DESCRIPTION_SUMMARY "lwIP lightweight IP stack")
set(CPACK_PACKAGE_VERSION_MAJOR "${LWIP_VERSION_MAJOR}")
set(CPACK_PACKAGE_VERSION_MINOR "${LWIP_VERSION_MINOR}")
set(CPACK_PACKAGE_VERSION_PATCH "${LWIP_VERSION_REVISION}")
set(CPACK_SOURCE_IGNORE_FILES "/build/;${CPACK_SOURCE_IGNORE_FILES};.git")
set(CPACK_SOURCE_PACKAGE_FILE_NAME "lwip-${LWIP_VERSION_MAJOR}.${LWIP_VERSION_MINOR}.${LWIP_VERSION_REVISION}")
include(CPack)
# Generate docs before creating source package
include(src/Filelists.cmake)
add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source)
if (TARGET lwipdocs)
add_dependencies(dist lwipdocs)
endif()

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/*
* Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/

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/*!
@page middleware_log Middleware Change Log
@section lwip lwIP for MCUXpresso SDK
The current version of lwIP is based on lwIP 2.2.0.dev.
- 2.2.0_rev3
- New features:
- Ported lwIP 2.2.0.dev (2020-07-07, branch: master, SHA-1: c385f31076b27efb8ee37f00cb5568783a58f299) to KSDK 2.0.0.
- 2.2.0_rev2
- New features:
- Kinetis ENET adaptation layer - implemented zero-copy on receive.
- lwiperf - counter of transferred bytes extended from 32 to 64 bit
- Bug fixes:
- Fixed restarting Auto IP from DHCP.
- 2.2.0_rev1
- New features:
- Ported lwIP 2.2.0.dev (2019-12-12, branch: master, SHA-1: 555812dcec38c9a2ef1ef9b31816291549fbf9f8) to KSDK 2.0.0.
- Implemented LWIP_ASSERT_CORE_LOCKED related functions in sys_arch.c. It can be enabled in lwipopts.h:
- <tt>\#define LWIP_ASSERT_CORE_LOCKED() sys_check_core_locking()</tt>
- <tt>\#define LWIP_MARK_TCPIP_THREAD() sys_mark_tcpip_thread() // if NO_SYS == 0</tt>
- <tt>\#define LOCK_TCPIP_CORE() sys_lock_tcpip_core() // if NO_SYS == 0 and LWIP_TCPIP_CORE_LOCKING == 1</tt>
- <tt>\#define UNLOCK_TCPIP_CORE() sys_unlock_tcpip_core() // if NO_SYS == 0 and LWIP_TCPIP_CORE_LOCKING == 1</tt>
- 2.1.2_rev5
- New features:
- Implemented TCP_USER_TIMEOUT socket option.
- Implemented SIOCOUTQ ioctl.
- 2.1.2_rev4
- New features:
- Ported lwIP 2.1.3.dev (2019-02-27, branch: STABLE-2_1_x, SHA-1: 1bb6e7f52de1cd86be0eed31e348431edc2cd01e) to KSDK 2.0.0.
- Updated sys_thread_new implementation and comment.
- Kinetis ENET adaptation layer - reading frames into a pbuf chain is conditionally compiled only when a single pbuf from pool
cannot hold maximum frame size (PBUF_POOL_BUFSIZE >= maximum frame size).
Avoiding this code also reduces stack size requirements by about 1.5 kilobytes.
- Bug fixes:
- Fixes in ethernetif_linkoutput() in enet_ethernetif_lpc.c:
- Removed access to possibly freed pbuf.
- Call pbuf_free() when transmit buffers not available.
- When copying pbuf chain, updating the number of necessary transmit buffers to wait for, which can be often smaller in the copy.
- When CGI script is reading POST data by chunks, the loop in httpsrv_read() may cause blocking in receive function waiting for more data at the end of the stream
- HTTPSRV_cgi_read() - added limiting of the last chunk length according to content length to avoid undesired blocking
- Applied AUTOIP patch https://savannah.nongnu.org/patch/?9847 - with modification to support multiple network interfaces.
- Fixed buffer overflow in httpsrv when application provided CGI script does not handle the whole content of POST request
- Removed LwipMibCompiler contrib application as it contained LGPL licensed files in SharpSnmpLib.
- 2.1.2_rev3
- New features:
- lwiperf updated with UDP client/server support from the patch 9751 (https://savannah.nongnu.org/patch/?9751)
- 2.1.2_rev2
- Bug fixes:
- Fixed lwiperf_abort() in lwiperf.c to correctly close connections and free resources
- 2.1.2_rev1
- New features:
- Ported lwIP 2.1.2 (2018-11-22, SHA-1: 159e31b689577dbf69cf0683bbaffbd71fa5ee10) to KSDK 2.0.0.
- Ported lwIP-contrib 2.1.0 (2018-09-24, SHA-1: 35b011d4cf4c4b480f8859c456587a884ec9d287) to KSDK 2.0.0.
- 2.0.3_rev1
- New features:
- Ported lwIP 2.0.3 (2017-09-15, SHA-1: 92f23d6ca0971a32f2085b9480e738d34174417b) to KSDK 2.0.0.
- 2.0.2_rev1
- New features:
- Ported lwIP 2.0.2 (2017-03-13, SHA-1: c0862d60746e2d1ceae69af4c6f24e469570ecef) to KSDK 2.0.0.
- 2.0.0_rev3
- New features:
- Ported lwIP 2.0.0 (2016-11-10, SHA-1: 216bf89491815029aa15463a18744afa04df58fe) to KSDK 2.0.0.
- 2.0.0_rev2
- New features:
- Ported lwIP 2.0.0 RC2 (2016-08-08, SHA-1: b1dfd00f9233d124514a36a8c8606990016f2ad4) to KSDK 2.0.0.
- 2.0.0_rev1
- New features:
- Ported lwIP 2.0.0 RC0 (2016-05-26) to KSDK 2.0.0.
- Changed lwIP bare-metal examples to use poll-driven approach instead of interrupt-driven one.
- 1.4.1_rev2
- New features:
- Enabled critical sections in lwIP.
- Bug fixes:
- Fixed default lwIP packet-buffer size to be able to accept a maximum size frame from the ENET driver.
- Fixed possible drop of multi-frame packets during transmission.
- 1.4.1_rev1
- New features:
- Ported lwIP 1.4.1 to KSDK 2.0.0.
*/

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lwIP is a small independent implementation of the TCP/IP protocol suite targeted at embedded systems.
The focus of the lwIP TCP/IP implementation is to reduce resource usage while still having a full scale TCP. This makes lwIP suitable for use in embedded systems with tens of kilobytes of free RAM and room for around 40 kilobytes of code ROM.
Main features include:
- Protocols: IP, IPv6, ICMP, ND, MLD, UDP, TCP, IGMP, ARP, PPPoS, PPPoE, 6LowPAN (via IEEE 802.15.4, BLE or ZEP; since v2.1.0)
- DHCP client, stateless DHCPv6 (since v2.1.0), DNS client (incl. mDNS hostname resolver), AutoIP/APIPA (Zeroconf), ACD (Address Conflict Detection), SNMP agent (v1, v2c, v3 (since v2.1.0), private MIB support & MIB compiler)
- APIs: specialized APIs for enhanced performance & zero copy, optional Berkeley-alike socket API
- Extended features: IP forwarding over multiple network interfaces
- Extended TCP features: congestion control, RTT estimation and fast recovery/fast retransmit, sending SACKs (since v2.1.0), "altcp": nearly transparent TLS for any tcp pcb (since v2.1.0)
- Addon applications: HTTP server (HTTPS via altcp), HTTP(S) client (since v2.1.0), SNTP client, SMTP client (SMTPS via altcp), ping, NetBIOS nameserver, mDNS responder, MQTT client (TLS support since v2.1.0), TFTP server, iPerf2 counterpart

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contrib/ - lwIP examples, ports, and small apps (formerly http://git.savannah.gnu.org/cgit/lwip/lwip-contrib.git/)
src/ - The source code for the lwIP TCP/IP stack.
doc/ - The documentation for lwIP.
test/ - Some code to test whether the sources do what they should.
See also the FILES file in each subdirectory.

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INTRODUCTION
lwIP is a small independent implementation of the TCP/IP protocol suite.
The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
while still having a full scale TCP. This making lwIP suitable for use
in embedded systems with tens of kilobytes of free RAM and room for
around 40 kilobytes of code ROM.
lwIP was originally developed by Adam Dunkels at the Computer and Networks
Architectures (CNA) lab at the Swedish Institute of Computer Science (SICS)
and is now developed and maintained by a worldwide network of developers.
FEATURES
* IP (Internet Protocol, IPv4 and IPv6) including packet forwarding over
multiple network interfaces
* ICMP (Internet Control Message Protocol) for network maintenance and debugging
* IGMP (Internet Group Management Protocol) for multicast traffic management
* MLD (Multicast listener discovery for IPv6). Aims to be compliant with
RFC 2710. No support for MLDv2
* ND (Neighbor discovery and stateless address autoconfiguration for IPv6).
Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
(Address autoconfiguration)
* DHCP, AutoIP/APIPA (Zeroconf), ACD (Address Conflict Detection)
and (stateless) DHCPv6
* UDP (User Datagram Protocol) including experimental UDP-lite extensions
* TCP (Transmission Control Protocol) with congestion control, RTT estimation
fast recovery/fast retransmit and sending SACKs
* raw/native API for enhanced performance
* Optional Berkeley-like socket API
* TLS: optional layered TCP ("altcp") for nearly transparent TLS for any
TCP-based protocol (ported to mbedTLS) (see changelog for more info)
* PPPoS and PPPoE (Point-to-point protocol over Serial/Ethernet)
* DNS (Domain name resolver incl. mDNS)
* 6LoWPAN (via IEEE 802.15.4, BLE or ZEP)
APPLICATIONS
* HTTP server with SSI and CGI (HTTPS via altcp)
* SNMPv2c agent with MIB compiler (Simple Network Management Protocol), v3 via altcp
* SNTP (Simple network time protocol)
* NetBIOS name service responder
* MDNS (Multicast DNS) responder
* iPerf server implementation
* MQTT client (TLS support via altcp)
LICENSE
lwIP is freely available under a BSD license.
DEVELOPMENT
lwIP has grown into an excellent TCP/IP stack for embedded devices,
and developers using the stack often submit bug fixes, improvements,
and additions to the stack to further increase its usefulness.
Development of lwIP is hosted on Savannah, a central point for
software development, maintenance and distribution. Everyone can
help improve lwIP by use of Savannah's interface, Git and the
mailing list. A core team of developers will commit changes to the
Git source tree.
The lwIP TCP/IP stack is maintained in the 'src' directory and
contributions (such as platform ports and applications) are in
the 'contrib' directory.
See doc/savannah.txt for details on Git server access for users and
developers.
The current Git tree is web-browsable:
https://git.savannah.gnu.org/cgit/lwip.git
Submit patches and bugs via the lwIP project page:
https://savannah.nongnu.org/projects/lwip/
Continuous integration builds (GCC, clang):
https://travis-ci.org/lwip-tcpip/lwip
DOCUMENTATION
Self documentation of the source code is regularly extracted from the current
Git sources and is available from this web page:
https://www.nongnu.org/lwip/
Also, there are mailing lists you can subscribe at
https://savannah.nongnu.org/mail/?group=lwip
plus searchable archives:
https://lists.nongnu.org/archive/html/lwip-users/
https://lists.nongnu.org/archive/html/lwip-devel/
There is a wiki about lwIP at
https://lwip.wikia.com/wiki/LwIP_Wiki
You might get questions answered there, but unfortunately, it is not as
well maintained as it should be.
lwIP was originally written by Adam Dunkels:
http://dunkels.com/adam/
Reading Adam's papers, the files in docs/, browsing the source code
documentation and browsing the mailing list archives is a good way to
become familiar with the design of lwIP.
Adam Dunkels <adam@sics.se>
Leon Woestenberg <leon.woestenberg@gmx.net>

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This file lists major changes between release versions that require
ports or applications to be changed. Use it to update a port or an
application written for an older version of lwIP to correctly work
with newer versions.
(git master)
* [Enter new changes just after this line - do not remove this line]
* The eth_addr_cmp and ip_addr_cmp set of functions have been renamed to eth_addr_eq, ip_addr_eq
and so on, since they return non-zero on equality. Macros for the old names exist.
(2.1.0)
++ Application changes:
* Use the new altcp API for seamless TLS integration into existing TCP applications (see changelog)
* TCP only kills existing connections with a LOWER priority than the one currently being opened.
Previous implementations also kill existing connections of the SAME priority.
* ip4_route_src: parameter order is reversed: ip4_route_src(dest, src) -> ip4_route_src(src, dest)
to make parameter order consistent with other ip*_route*() functions.
Same also applies to LWIP_HOOK_IP4_ROUTE_SRC() parameter order.
* pbuf API: pbuf->type (an u8_t holding the enum 'pbuf_type') has changed to only hold a
description of the pbuf (e.g. data following pbuf struct, data volatile, allocation
source heap/pool/etc.). As a consequence, applications can't test pbuf->type any more.
Use pbuf_match_type(pbuf, type) instead.
* socket API: according to the standard, SO_ERROR now only returns asynchronous errors.
All other/normal/synchronous errors are (and always were) available via 'errno'.
LWIP_SOCKET_SET_ERRNO has been removed - 'errno' is always set - and required!
* httpd LWIP_HTTPD_CGI_SSI: httpd_cgi_handler() has an additional parameter "struct fs_file *"
++ Port changes:
* tcpip_trycallback() was renamed to tcpip_callbackmsg_trycallback() to avoid confusion
with tcpip_try_callback()
* compatibility headers: moved from 'src/include/posix' to 'src/include/compat/posix',
'src/include/compat/stdc' etc.
* The IPv6 implementation now supports address scopes. (See LWIP_IPV6_SCOPES documentation
and ip6_zone.h for more documentation)
* LWIP_HOOK_DHCP_APPEND_OPTIONS() has changed, see description in opt.h (options_out_len is not
available in struct dhcp any more)
* Added debug helper asserts to ensure threading/locking requirements are met (define
LWIP_MARK_TCPIP_THREAD() and LWIP_ASSERT_CORE_LOCKED()).
* Added sys_mbox_trypost_fromisr() and tcpip_callbackmsg_trycallback_fromisr()
These can be used to post preallocated messages from an ISR to the tcpip thread
(e.g. when using FreeRTOS)
(2.0.2)
++ Application changes:
* slipif: The way to pass serial port number has changed. netif->num is not
supported any more, netif->state is interpreted as an u8_t port number now
(it's not a POINTER to an u8_t any more!)
(2.0.1)
++ Application changes:
* UDP does NOT receive multicast traffic from ALL netifs on an UDP PCB bound to a specific
netif any more. Users need to bind to IP_ADDR_ANY to receive multicast traffic and compare
ip_current_netif() to the desired netif for every packet.
See bug #49662 for an explanation.
(2.0.0)
++ Application changes:
* Changed netif "up" flag handling to be an administrative flag (as opposed to the previous meaning of
"ip4-address-valid", a netif will now not be used for transmission if not up) -> even a DHCP netif
has to be set "up" before starting the DHCP client
* Added IPv6 support (dual-stack or IPv4/IPv6 only)
* Changed ip_addr_t to be a union in dual-stack mode (use ip4_addr_t where referring to IPv4 only).
* Major rewrite of SNMP (added MIB parser that creates code stubs for custom MIBs);
supports SNMPv2c (experimental v3 support)
* Moved some core applications from contrib repository to src/apps (and include/lwip/apps)
+++ Raw API:
* Changed TCP listen backlog: removed tcp_accepted(), added the function pair tcp_backlog_delayed()/
tcp_backlog_accepted() to explicitly delay backlog handling on a connection pcb
+++ Socket API:
* Added an implementation for posix sendmsg()
* Added LWIP_FIONREAD_LINUXMODE that makes ioctl/FIONREAD return the size of the next pending datagram
++ Port changes
+++ new files:
* MANY new and moved files!
* Added src/Filelists.mk for use in Makefile projects
* Continued moving stack-internal parts from abc.h to abc_priv.h in sub-folder "priv"
to let abc.h only contain the actual application programmer's API
+++ sys layer:
* Made LWIP_TCPIP_CORE_LOCKING==1 the default as it usually performs better than
the traditional message passing (although with LWIP_COMPAT_MUTEX you are still
open to priority inversion, so this is not recommended any more)
* Added LWIP_NETCONN_SEM_PER_THREAD to use one "op_completed" semaphore per thread
instead of using one per netconn (these semaphores are used even with core locking
enabled as some longer lasting functions like big writes still need to delay)
* Added generalized abstraction for itoa(), strnicmp(), stricmp() and strnstr()
in def.h (to be overridden in cc.h) instead of config
options for netbiosns, httpd, dns, etc. ...
* New abstraction for hton* and ntoh* functions in def.h.
To override them, use the following in cc.h:
#define lwip_htons(x) <your_htons>
#define lwip_htonl(x) <your_htonl>
+++ new options:
* TODO
+++ new pools:
* Added LWIP_MEMPOOL_* (declare/init/alloc/free) to declare private memp pools
that share memp.c code but do not have to be made global via lwippools.h
* Added pools for IPv6, MPU_COMPATIBLE, dns-api, netif-api, etc.
* added hook LWIP_HOOK_MEMP_AVAILABLE() to get informed when a memp pool was empty and an item
is now available
* Signature of LWIP_HOOK_VLAN_SET macro was changed
* LWIP_DECLARE_MEMORY_ALIGNED() may be used to declare aligned memory buffers (mem/memp)
or to move buffers to dedicated memory using compiler attributes
* Standard C headers are used to define sized types and printf formatters
(disable by setting LWIP_NO_STDINT_H=1 or LWIP_NO_INTTYPES_H=1 if your compiler
does not support these)
++ Major bugfixes/improvements
* Added IPv6 support (dual-stack or IPv4/IPv6 only)
* Major rewrite of PPP (incl. keep-up with apache pppd)
see doc/ppp.txt for an upgrading how-to
* Major rewrite of SNMP (incl. MIB parser)
* Fixed timing issues that might have lead to losing a DHCP lease
* Made rx processing path more robust against crafted errors
* TCP window scaling support
* modification of api modules to support FreeRTOS-MPU (don't pass stack-pointers to other threads)
* made DNS client more robust
* support PBUF_REF for RX packets
* LWIP_NETCONN_FULLDUPLEX allows netconn/sockets to be used for reading/writing from separate
threads each (needs LWIP_NETCONN_SEM_PER_THREAD)
* Moved and reordered stats (mainly memp/mib2)
(1.4.0)
++ Application changes:
* Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for
compatibility to old applications, but will be removed in the future).
* Renamed mem_realloc() to mem_trim() to prevent confusion with realloc()
+++ Raw API:
* Changed the semantics of tcp_close() (since it was rather a
shutdown before): Now the application does *NOT* get any calls to the recv
callback (aside from NULL/closed) after calling tcp_close()
* When calling tcp_abort() from a raw API TCP callback function,
make sure you return ERR_ABRT to prevent accessing unallocated memory.
(ERR_ABRT now means the applicaiton has called tcp_abort!)
+++ Netconn API:
* Changed netconn_receive() and netconn_accept() to return
err_t, not a pointer to new data/netconn.
+++ Socket API:
* LWIP_SO_RCVTIMEO: when accept() or recv() time out, they
now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT.
* Added a minimal version of posix fctl() to have a
standardised way to set O_NONBLOCK for nonblocking sockets.
+++ all APIs:
* correctly implemented SO(F)_REUSEADDR
++ Port changes
+++ new files:
* Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h:
* Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains
the actual application programmer's API
* Separated timer implementation from sys.h/.c, moved to timers.h/.c;
Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you
still want to use your own timer implementation for NO_SYS==0 (as before).
+++ sys layer:
* Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/
sys_sem_t;
* Converted sys_mbox_new/sys_sem_new to take pointers and return err_t;
* Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use
binary semaphores instead of mutexes - as before)
+++ new options:
* Don't waste memory when chaining segments, added option TCP_OVERSIZE to
prevent creating many small pbufs when calling tcp_write with many small
blocks of data. Instead, pbufs are allocated larger than needed and the
space is used for later calls to tcp_write.
* Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs
in tcp_write/udp_send.
* Added an additional option LWIP_ETHERNET to support ethernet without ARP
(necessary for pure PPPoE)
* Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may
be used to place these pools into user-defined memory by using external
declaration.
* Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT
+++ new pools:
* Netdb uses a memp pool for allocating memory when getaddrinfo() is called,
so MEMP_NUM_NETDB has to be set accordingly.
* DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so
MEMP_NUM_LOCALHOSTLIST has to be set accordingly.
* Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have
to be set accordingly.
* PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES
has to be set accordingly
* Integrated loopif into netif.c - loopif does not have to be created by the
port any more, just define LWIP_HAVE_LOOPIF to 1.
* Added define LWIP_RAND() for lwip-wide randomization (needs to be defined
in cc.h, e.g. used by igmp)
* Added printf-formatter X8_F to printf u8_t as hex
* The heap now may be moved to user-defined memory by defining
LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address
* added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work
with user-allocated structs instead of calling mem_malloc
* Added const char* name to mem- and memp-stats for easier debugging.
* Calculate the TCP/UDP checksum while copying to only fetch data once:
Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum
* Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to
more than one pcb.
* Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned
off any more, if this is set to 0, only one packet (the most recent one) is
queued (like demanded by RFC 1122).
++ Major bugfixes/improvements
* Implemented tcp_shutdown() to only shut down one end of a connection
* Implemented shutdown() at socket- and netconn-level
* Added errorset support to select() + improved select speed overhead
* Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x)
* Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1
* Use macros defined in ip_addr.h to work with IP addresses
* Implemented many nonblocking socket/netconn functions
* Fixed ARP input processing: only add a new entry if a request was directed as us
* mem_realloc() to mem_trim() to prevent confusion with realloc()
* Some improvements for AutoIP (don't route/forward link-local addresses, don't break
existing connections when assigning a routable address)
* Correctly handle remote side overrunning our rcv_wnd in ooseq case
* Removed packing from ip_addr_t, the packed version is now only used in protocol headers
* Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0
* Added support for static ARP table entries
(STABLE-1.3.2)
* initial version of this file

106
middleware/lwip/contrib/Coverity/coverity.c Normal file
View File

@ -0,0 +1,106 @@
typedef unsigned char err_t;
typedef unsigned int u32_t;
typedef unsigned short u16_t;
typedef unsigned char u8_t;
typedef void sys_sem_t;
typedef void sys_mutex_t;
typedef size_t mem_size_t;
typedef size_t memp_t;
struct pbuf;
struct netif;
void* mem_malloc(mem_size_t size)
{
__coverity_alloc__(size);
}
void mem_free(void* mem)
{
__coverity_free__(mem);
}
void* memp_malloc(memp_t type)
{
__coverity_alloc_nosize__();
}
void memp_free(memp_t type, void* mem)
{
__coverity_free__(mem);
}
void sys_mutex_lock(sys_mutex_t* mutex)
{
__coverity_exclusive_lock_acquire__(mutex);
}
void sys_mutex_unlock(sys_mutex_t* mutex)
{
__coverity_exclusive_lock_release__(mutex);
}
u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout)
{
__coverity_recursive_lock_acquire__(sem);
}
void sys_sem_signal(sys_sem_t *sem)
{
__coverity_recursive_lock_release__(sem);
}
err_t ethernet_input(struct pbuf *p, struct netif *inp)
{
__coverity_tainted_string_sink_content__(p);
}
err_t tcpip_input(struct pbuf *p, struct netif *inp)
{
__coverity_tainted_string_sink_content__(p);
}
err_t ip_input(struct pbuf *p, struct netif *inp)
{
__coverity_tainted_string_sink_content__(p);
}
err_t ip4_input(struct pbuf *p, struct netif *inp)
{
__coverity_tainted_string_sink_content__(p);
}
err_t ip6_input(struct pbuf *p, struct netif *inp)
{
__coverity_tainted_string_sink_content__(p);
}
err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len)
{
__coverity_tainted_string_argument__(buf);
__coverity_tainted_data_argument__(buf);
}
err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset)
{
__coverity_tainted_string_argument__(buf);
__coverity_tainted_data_argument__(buf);
}
err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from)
{
__coverity_tainted_data_transitive__(p_to, p_from);
}
u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset)
{
__coverity_tainted_string_argument__(dataptr);
__coverity_tainted_data_argument__(dataptr);
}
u8_t pbuf_get_at(struct pbuf* p, u16_t offset)
{
__coverity_tainted_data_return__();
}
void abort(void)
{
__coverity_panic__();
}
int check_path(char* path, size_t size)
{
if (size) {
__coverity_tainted_data_sanitize__(path);
return 1;
} else {
return 0;
}
}

57
middleware/lwip/contrib/Filelists.mk Normal file
View File

@ -0,0 +1,57 @@
#
# Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
# 3. The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
# SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# This file is part of the lwIP TCP/IP stack.
#
# Author: Adam Dunkels <adam@sics.se>
#
# CONTRIBAPPFILES: Contrib Applications.
CONTRIBAPPFILES=$(CONTRIBDIR)/apps/httpserver/httpserver-netconn.c \
$(CONTRIBDIR)/apps/chargen/chargen.c \
$(CONTRIBDIR)/apps/udpecho/udpecho.c \
$(CONTRIBDIR)/apps/tcpecho/tcpecho.c \
$(CONTRIBDIR)/apps/shell/shell.c \
$(CONTRIBDIR)/apps/udpecho_raw/udpecho_raw.c \
$(CONTRIBDIR)/apps/tcpecho_raw/tcpecho_raw.c \
$(CONTRIBDIR)/apps/netio/netio.c \
$(CONTRIBDIR)/apps/ping/ping.c \
$(CONTRIBDIR)/apps/socket_examples/socket_examples.c \
$(CONTRIBDIR)/apps/rtp/rtp.c \
$(CONTRIBDIR)/examples/httpd/fs_example/fs_example.c \
$(CONTRIBDIR)/examples/httpd/https_example/https_example.c \
$(CONTRIBDIR)/examples/httpd/ssi_example/ssi_example.c \
$(CONTRIBDIR)/examples/lwiperf/lwiperf_example.c \
$(CONTRIBDIR)/examples/mdns/mdns_example.c \
$(CONTRIBDIR)/examples/mqtt/mqtt_example.c \
$(CONTRIBDIR)/examples/ppp/pppos_example.c \
$(CONTRIBDIR)/examples/snmp/snmp_private_mib/lwip_prvmib.c \
$(CONTRIBDIR)/examples/snmp/snmp_v3/snmpv3_dummy.c \
$(CONTRIBDIR)/examples/snmp/snmp_example.c \
$(CONTRIBDIR)/examples/sntp/sntp_example.c \
$(CONTRIBDIR)/examples/tftp/tftp_example.c \
$(CONTRIBDIR)/addons/tcp_isn/tcp_isn.c \
$(CONTRIBDIR)/addons/ipv6_static_routing/ip6_route_table.c

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