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Added Segger SystemView headers, and ITM trace, fixed tickless idle.

This commit is contained in:
imi415 2021-09-07 02:14:20 +08:00
parent 51e5fbce73
commit 16763c4fc2
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
21 changed files with 1261 additions and 209 deletions
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3
.gitmodules vendored
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@ -1,3 +1,6 @@
[submodule "Middlewares/Third_Party/printf"]
path = Middlewares/Third_Party/printf
url = https://github.com/mpaland/printf.git
[submodule "Middlewares/Third_Party/SystemView_Target"]
path = Middlewares/Third_Party/SystemView_Target
url = https://github.com/imi415/SystemView_Target.git

5
CMakeLists.txt
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@ -23,6 +23,7 @@ set(C_SOURCES
"Core/Src/stm32f4xx_hal_timebase_tim.c"
"Core/Src/user_power_mgmt.c"
"Core/Src/user_freertos_support.c"
"Core/Src/SystemView/SEGGER_SYSVIEW_Config_FreeRTOS.c"
)
# Copy them from Makefile
set(ASM_SOURCES
@ -33,6 +34,7 @@ set(C_LIBRARIES
"rtos"
"stm32_hal_driver"
"printf"
"systemview"
)
# Copy them from Makefile
@ -45,6 +47,7 @@ set(C_DEFINES
# Copy them from Makefile
set(C_INCLUDES
"Core/Inc"
"Core/Inc/SystemView"
"Drivers/STM32F4xx_HAL_Driver/Inc"
"Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"
"Drivers/CMSIS/Device/ST/STM32F4xx/Include"
@ -53,6 +56,8 @@ set(C_INCLUDES
"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"
"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
"Middlewares/Third_Party/printf"
"Middlewares/Third_Party/SystemView_Target/SEGGER"
"Middlewares/Third_Party/SystemView_Target/Sample/FreeRTOSV10"
)
# Final compiler flags

6
Core/Inc/FreeRTOSConfig.h
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@ -169,11 +169,13 @@ standard names. */
void vApplicationSleep(uint32_t xExpectedIdleTime);
/* Override CMSIS OS2 heap settings */
#define configAPPLICATION_ALLOCATED_HEAP 1
#define configAPPLICATION_ALLOCATED_HEAP 1
#define configUSE_TICKLESS_IDLE 2
#define configUSE_TICKLESS_IDLE 2
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vApplicationSleep(xExpectedIdleTime)
#include "SEGGER_SYSVIEW_FreeRTOS.h"
/* USER CODE END Defines */
#endif /* FREERTOS_CONFIG_H */

113
Core/Inc/SystemView/Global.h Normal file
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@ -0,0 +1,113 @@
/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 1995 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER SystemView * Real-time application analysis *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* SEGGER strongly recommends to not make any changes *
* to or modify the source code of this software in order to stay *
* compatible with the SystemView and RTT protocol, and J-Link. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* o Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* SystemView version: 3.30 *
* *
**********************************************************************
----------------------------------------------------------------------
File : Global.h
Purpose : Global types
In case your application already has a Global.h, you should
merge the files. In order to use Segger code, the types
U8, U16, U32, I8, I16, I32 need to be defined in Global.h;
additional definitions do not hurt.
Revision: $Rev: 12501 $
---------------------------END-OF-HEADER------------------------------
*/
#ifndef GLOBAL_H // Guard against multiple inclusion
#define GLOBAL_H
#define U8 unsigned char
#define I8 signed char
#define U16 unsigned short
#define I16 signed short
#ifdef __x86_64__
#define U32 unsigned
#define I32 int
#else
#define U32 unsigned long
#define I32 signed long
#endif
//
// CC_NO_LONG_SUPPORT can be defined to compile test
// without long support for compilers that do not
// support C99 and its long type.
//
#ifdef CC_NO_LONG_SUPPORT
#define PTR_ADDR U32
#else // Supports long type.
#if defined(_WIN32) && !defined(__clang__) && !defined(__MINGW32__)
//
// Microsoft VC6 compiler related
//
#define U64 unsigned __int64
#define U128 unsigned __int128
#define I64 __int64
#define I128 __int128
#if _MSC_VER <= 1200
#define U64_C(x) x##UI64
#else
#define U64_C(x) x##ULL
#endif
#else
//
// C99 compliant compiler
//
#define U64 unsigned long long
#define I64 signed long long
#define U64_C(x) x##ULL
#endif
#if (defined(_WIN64) || defined(__LP64__)) // 64-bit symbols used by Visual Studio and GCC, maybe others as well.
#define PTR_ADDR U64
#else
#define PTR_ADDR U32
#endif
#endif // Supports long type.
#endif // Avoid multiple inclusion
/*************************** End of file ****************************/

428
Core/Inc/SystemView/SEGGER_RTT_Conf.h Normal file
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@ -0,0 +1,428 @@
/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 1995 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER SystemView * Real-time application analysis *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* SEGGER strongly recommends to not make any changes *
* to or modify the source code of this software in order to stay *
* compatible with the SystemView and RTT protocol, and J-Link. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* o Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* SystemView version: 3.30 *
* *
**********************************************************************
---------------------------END-OF-HEADER------------------------------
File : SEGGER_RTT_Conf.h
Purpose : Implementation of SEGGER real-time transfer (RTT) which
allows real-time communication on targets which support
debugger memory accesses while the CPU is running.
Revision: $Rev: 21386 $
*/
#ifndef SEGGER_RTT_CONF_H
#define SEGGER_RTT_CONF_H
#ifdef __IAR_SYSTEMS_ICC__
#include <intrinsics.h>
#endif
/*********************************************************************
*
* Defines, configurable
*
**********************************************************************
*/
//
// Take in and set to correct values for Cortex-A systems with CPU cache
//
//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system
//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached
//
// Most common case:
// Up-channel 0: RTT
// Up-channel 1: SystemView
//
#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS
#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (8) // Max. number of up-buffers (T->H) available on this target (Default: 3)
#endif
//
// Most common case:
// Down-channel 0: RTT
// Down-channel 1: SystemView
//
#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3)
#endif
#ifndef BUFFER_SIZE_UP
#define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k)
#endif
#ifndef BUFFER_SIZE_DOWN
#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
#endif
#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
#endif
#ifndef SEGGER_RTT_MODE_DEFAULT
#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
#endif
/*********************************************************************
*
* RTT memcpy configuration
*
* memcpy() is good for large amounts of data,
* but the overhead is big for small amounts, which are usually stored via RTT.
* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
*
* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
* This is may be required with memory access restrictions,
* such as on Cortex-A devices with MMU.
*/
#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP
#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
#endif
//
// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
//
//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes))
//#endif
//
// Target is not allowed to perform other RTT operations while string still has not been stored completely.
// Otherwise we would probably end up with a mixed string in the buffer.
// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
//
// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
// (Higher priority = lower priority number)
// Default value for embOS: 128u
// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
// or define SEGGER_RTT_LOCK() to completely disable interrupts.
//
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
#endif
/*********************************************************************
*
* RTT lock configuration for SEGGER Embedded Studio,
* Rowley CrossStudio and GCC
*/
#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
#if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
__asm volatile ("mrs %0, primask \n\t" \
"movs r1, #1 \n\t" \
"msr primask, r1 \n\t" \
: "=r" (_SEGGER_RTT__LockState) \
: \
: "r1", "cc" \
);
#define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \
: \
: "r" (_SEGGER_RTT__LockState) \
: \
); \
}
#elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__))
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
#endif
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
__asm volatile ("mrs %0, basepri \n\t" \
"mov r1, %1 \n\t" \
"msr basepri, r1 \n\t" \
: "=r" (_SEGGER_RTT__LockState) \
: "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \
: "r1", "cc" \
);
#define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \
: \
: "r" (_SEGGER_RTT__LockState) \
: \
); \
}
#elif defined(__ARM_ARCH_7A__)
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
__asm volatile ("mrs r1, CPSR \n\t" \
"mov %0, r1 \n\t" \
"orr r1, r1, #0xC0 \n\t" \
"msr CPSR_c, r1 \n\t" \
: "=r" (_SEGGER_RTT__LockState) \
: \
: "r1", "cc" \
);
#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
"mrs r1, CPSR \n\t" \
"bic r1, r1, #0xC0 \n\t" \
"and r0, r0, #0xC0 \n\t" \
"orr r1, r1, r0 \n\t" \
"msr CPSR_c, r1 \n\t" \
: \
: "r" (_SEGGER_RTT__LockState) \
: "r0", "r1", "cc" \
); \
}
#elif defined(__riscv) || defined(__riscv_xlen)
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
__asm volatile ("csrr %0, mstatus \n\t" \
"csrci mstatus, 8 \n\t" \
"andi %0, %0, 8 \n\t" \
: "=r" (_SEGGER_RTT__LockState) \
: \
: \
);
#define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \
"or %0, %0, a1 \n\t" \
"csrs mstatus, %0 \n\t" \
: \
: "r" (_SEGGER_RTT__LockState) \
: "a1" \
); \
}
#else
#define SEGGER_RTT_LOCK()
#define SEGGER_RTT_UNLOCK()
#endif
#endif
/*********************************************************************
*
* RTT lock configuration for IAR EWARM
*/
#ifdef __ICCARM__
#if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \
(defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = __get_PRIMASK(); \
__set_PRIMASK(1);
#define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
}
#elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \
(defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \
(defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \
(defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
#endif
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = __get_BASEPRI(); \
__set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
#define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \
}
#elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \
(defined (__ARM7R__) && (__CORE__ == __ARM7R__))
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
__asm volatile ("mrs r1, CPSR \n\t" \
"mov %0, r1 \n\t" \
"orr r1, r1, #0xC0 \n\t" \
"msr CPSR_c, r1 \n\t" \
: "=r" (_SEGGER_RTT__LockState) \
: \
: "r1", "cc" \
);
#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
"mrs r1, CPSR \n\t" \
"bic r1, r1, #0xC0 \n\t" \
"and r0, r0, #0xC0 \n\t" \
"orr r1, r1, r0 \n\t" \
"msr CPSR_c, r1 \n\t" \
: \
: "r" (_SEGGER_RTT__LockState) \
: "r0", "r1", "cc" \
); \
}
#endif
#endif
/*********************************************************************
*
* RTT lock configuration for IAR RX
*/
#ifdef __ICCRX__
#define SEGGER_RTT_LOCK() { \
unsigned long _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = __get_interrupt_state(); \
__disable_interrupt();
#define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
}
#endif
/*********************************************************************
*
* RTT lock configuration for IAR RL78
*/
#ifdef __ICCRL78__
#define SEGGER_RTT_LOCK() { \
__istate_t _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = __get_interrupt_state(); \
__disable_interrupt();
#define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
}
#endif
/*********************************************************************
*
* RTT lock configuration for KEIL ARM
*/
#ifdef __CC_ARM
#if (defined __TARGET_ARCH_6S_M)
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \
_SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \
_SEGGER_RTT__PRIMASK = 1u; \
__schedule_barrier();
#define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \
__schedule_barrier(); \
}
#elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
#endif
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
register unsigned char BASEPRI __asm( "basepri"); \
_SEGGER_RTT__LockState = BASEPRI; \
BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \
__schedule_barrier();
#define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \
__schedule_barrier(); \
}
#endif
#endif
/*********************************************************************
*
* RTT lock configuration for TI ARM
*/
#ifdef __TI_ARM__
#if defined (__TI_ARM_V6M0__)
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = __get_PRIMASK(); \
__set_PRIMASK(1);
#define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
}
#elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
#endif
#define SEGGER_RTT_LOCK() { \
unsigned int _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
#define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \
}
#endif
#endif
/*********************************************************************
*
* RTT lock configuration for CCRX
*/
#ifdef __RX
#include <machine.h>
#define SEGGER_RTT_LOCK() { \
unsigned long _SEGGER_RTT__LockState; \
_SEGGER_RTT__LockState = get_psw() & 0x010000; \
clrpsw_i();
#define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \
}
#endif
/*********************************************************************
*
* RTT lock configuration for embOS Simulation on Windows
* (Can also be used for generic RTT locking with embOS)
*/
#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
void OS_SIM_EnterCriticalSection(void);
void OS_SIM_LeaveCriticalSection(void);
#define SEGGER_RTT_LOCK() { \
OS_SIM_EnterCriticalSection();
#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \
}
#endif
/*********************************************************************
*
* RTT lock configuration fallback
*/
#ifndef SEGGER_RTT_LOCK
#define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts)
#endif
#ifndef SEGGER_RTT_UNLOCK
#define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
#endif
#endif
/*************************** End of file ****************************/

85
Core/Inc/SystemView/SEGGER_SYSVIEW_Conf.h Normal file
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@ -0,0 +1,85 @@
/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 1995 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER SystemView * Real-time application analysis *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* SEGGER strongly recommends to not make any changes *
* to or modify the source code of this software in order to stay *
* compatible with the SystemView and RTT protocol, and J-Link. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* o Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* SystemView version: 3.30 *
* *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : SEGGER_SYSVIEW_Conf.h
Purpose : SEGGER SystemView configuration file.
Set defines which deviate from the defaults (see SEGGER_SYSVIEW_ConfDefaults.h) here.
Revision: $Rev: 21292 $
Additional information:
Required defines which must be set are:
SEGGER_SYSVIEW_GET_TIMESTAMP
SEGGER_SYSVIEW_GET_INTERRUPT_ID
For known compilers and cores, these might be set to good defaults
in SEGGER_SYSVIEW_ConfDefaults.h.
SystemView needs a (nestable) locking mechanism.
If not defined, the RTT locking mechanism is used,
which then needs to be properly configured.
*/
#ifndef SEGGER_SYSVIEW_CONF_H
#define SEGGER_SYSVIEW_CONF_H
/*********************************************************************
*
* Defines, configurable
*
**********************************************************************
*/
/*********************************************************************
* TODO: Add your defines here. *
**********************************************************************
*/
#endif // SEGGER_SYSVIEW_CONF_H
/*************************** End of file ****************************/

156
Core/Inc/arm_etm.h Normal file
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@ -0,0 +1,156 @@
/* 2015 Petteri Aimonen <jpa@git.mail.kapsi.fi>
* Public domain. */
#ifndef ARM_ETM_H
#define ARM_ETM_H
#include "core_cm4.h"
/* ETM Peripheral Register definitions.
* See here for register documentation:
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0014q/Chdfiagc.html
*
* Not all features are supported on Cortex-M3, see here for details:
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337i/CHDBGEED.html
*
* The ETM peripheral has a lot of registers, but these are the main ones:
* - LAR: Allow write access to other ETM registers
* - CR: Enable/disable tracing
* - TRIGGER: Select tracing trigger event
* - SR: Current status
* - TECR1 Select areas of code where to enable trace
* - TECR2 Select comparator for trace enable
* - TEEVR Select event for trace enable
*/
typedef struct
{
__IO uint32_t CR; /* Main Control Register */
__IO uint32_t CCR; /* Configuration Code Register */
__IO uint32_t TRIGGER; /* Trigger Event */
__IO uint32_t ASICCR; /* ASIC Control Register */
__IO uint32_t SR; /* ETM Status Register */
__IO uint32_t SCR; /* System Configuration Register */
__IO uint32_t TSSCR; /* TraceEnable Start/Stop Control Register */
__IO uint32_t TECR2; /* TraceEnable Control 2 */
__IO uint32_t TEEVR; /* TraceEnable Event Register */
__IO uint32_t TECR1; /* TraceEnable Control 1 */
__IO uint32_t FFRR; /* FIFOFULL Region Register */
__IO uint32_t FFLR; /* FIFOFULL Level Register */
__IO uint32_t VDEVR; /* ViewData Event Register */
__IO uint32_t VDCR1; /* ViewData Control 1 */
__IO uint32_t VDCR2; /* ViewData Control 2 */
__IO uint32_t VDCR3; /* ViewData Control 3 */
__IO uint32_t ACVR[16]; /* Address Comparator Value Registers */
__IO uint32_t ACTR[16]; /* Address Comparator Access Type Registers */
__IO uint32_t DCVR[16]; /* Data Comparator Value Registers */
__IO uint32_t DCMR[16]; /* Data Comparator Mask Registers */
__IO uint32_t CNTRLDVR[4]; /* Counter Reload Value Registers */
__IO uint32_t CNTENR[4]; /* Counter Enable Registers */
__IO uint32_t CNTRLDEVR[4]; /* Counter Reload Event Registers */
__IO uint32_t CNTVR[4]; /* Counter Value Registers */
__IO uint32_t SQabEVR[6]; /* Sequencer State Transition Event Registers */
__IO uint32_t RESERVED0;
__IO uint32_t SQR; /* Current Sequencer State Register */
__IO uint32_t EXTOUTEVR[4]; /* External Output Event Registers */
__IO uint32_t CIDCVR[3]; /* Context ID Comparator Value Registers */
__IO uint32_t CIDCMR; /* Context ID Comparator Mask Register */
__IO uint32_t IMPL[8]; /* Implementation specific registers */
__IO uint32_t SYNCFR; /* Synchronization Frequency Register */
__IO uint32_t IDR; /* ETM ID Register */
__IO uint32_t CCER; /* Configuration Code Extension Register */
__IO uint32_t EXTINSELR; /* Extended External Input Selection Register */
__IO uint32_t TESSEICR; /* TraceEnable Start/Stop EmbeddedICE Control Register */
__IO uint32_t EIBCR; /* EmbeddedICE Behavior Control Register */
__IO uint32_t TSEVR; /* Timestamp Event Register, ETMv3.5 */
__IO uint32_t AUXCR; /* Auxiliary Control Register, ETMv3.5 */
__IO uint32_t TRACEIDR; /* CoreSight Trace ID Register */
__IO uint32_t RESERVED1;
__IO uint32_t IDR2; /* ETM ID Register 2 */
__IO uint32_t RESERVED2[13];
__IO uint32_t VMIDCVR; /* VMID Comparator Value Register, ETMv3.5 */
__IO uint32_t RESERVED3[47];
__IO uint32_t OSLAR; /* OS Lock Access Register */
__IO uint32_t OSLSR; /* OS Lock Status Register */
__IO uint32_t OSSRR; /* OS Save and Restore Register */
__IO uint32_t RESERVED4;
__IO uint32_t PDCR; /* Power Down Control Register, ETMv3.5 */
__IO uint32_t PDSR; /* Device Power-Down Status Register */
__IO uint32_t RESERVED5[762];
__IO uint32_t ITCTRL; /* Integration Mode Control Register */
__IO uint32_t RESERVED6[39];
__IO uint32_t CLAIMSET; /* Claim Tag Set Register */
__IO uint32_t CLAIMCLR; /* Claim Tag Clear Register */
__IO uint32_t RESERVED7[2];
__IO uint32_t LAR; /* Lock Access Register */
__IO uint32_t LSR; /* Lock Status Register */
__IO uint32_t AUTHSTATUS; /* Authentication Status Register */
__IO uint32_t RESERVED8[3];
__IO uint32_t DEVID; /* CoreSight Device Configuration Register */
__IO uint32_t DEVTYPE; /* CoreSight Device Type Register */
__IO uint32_t PIDR4; /* Peripheral ID4 */
__IO uint32_t PIDR5; /* Peripheral ID5 */
__IO uint32_t PIDR6; /* Peripheral ID6 */
__IO uint32_t PIDR7; /* Peripheral ID7 */
__IO uint32_t PIDR0; /* Peripheral ID0 */
__IO uint32_t PIDR1; /* Peripheral ID1 */
__IO uint32_t PIDR2; /* Peripheral ID2 */
__IO uint32_t PIDR3; /* Peripheral ID3 */
__IO uint32_t CIDR0; /* Component ID0 */
__IO uint32_t CIDR1; /* Component ID1 */
__IO uint32_t CIDR2; /* Component ID2 */
__IO uint32_t CIDR3; /* Component ID3 */
} ETM_Type;
#define ETM_CR_POWERDOWN 0x00000001
#define ETM_CR_MONITORCPRT 0x00000002
#define ETM_CR_TRACE_DATA 0x00000004
#define ETM_CR_TRACE_ADDR 0x00000008
#define ETM_CR_PORTSIZE_1BIT 0x00200000
#define ETM_CR_PORTSIZE_2BIT 0x00200010
#define ETM_CR_PORTSIZE_4BIT 0x00000000
#define ETM_CR_PORTSIZE_8BIT 0x00000010
#define ETM_CR_PORTSIZE_16BIT 0x00000020
#define ETM_CR_STALL_PROCESSOR 0x00000080
#define ETM_CR_BRANCH_OUTPUT 0x00000100
#define ETM_CR_DEBUGREQ 0x00000200
#define ETM_CR_PROGRAMMING 0x00000400
#define ETM_CR_ETMEN 0x00000800
#define ETM_CR_CYCLETRACE 0x00001000
#define ETM_CR_CONTEXTID_8BIT 0x00004000
#define ETM_CR_CONTEXTID_16BIT 0x00008000
#define ETM_CR_CONTEXTID_32BIT 0x0000C000
#define ETM_CR_CONTEXTID_8BIT 0x00004000
#define ETM_CR_PORTMODE_ONCHIP 0x00000000
#define ETM_CR_PORTMODE_2_1 0x00010000
#define ETM_CR_PORTMODE_IMPL 0x00030000
#define ETM_CR_PORTMODE_1_1 0x00002000
#define ETM_CR_PORTMODE_1_2 0x00022000
#define ETM_CR_PORTMODE_1_3 0x00012000
#define ETM_CR_PORTMODE_1_4 0x00032000
#define ETM_CR_SUPPRESS_DATA 0x00040000
#define ETM_CR_FILTER_CPRT 0x00080000
#define ETM_CR_DATA_ONLY 0x00100000
#define ETM_CR_BLOCK_DEBUGGER 0x00400000
#define ETM_CR_BLOCK_SOFTWARE 0x00800000
#define ETM_CR_ACCESS 0x01000000
#define ETM_CR_PROCSEL_Pos 25
#define ETM_CR_TIMESTAMP 0x10000000
#define ETM_CR_VMID 0x40000000
#define ETM_SR_PROGSTATUS 0x00000002
#define ETM_SR_TRIGSTATUS 0x00000008
#define ETM_TECR1_EXCLUDE 0x01000000
#define ETM_TECR1_TSSEN 0x02000000
#define ETM_FFRR_EXCLUDE 0x01000000
#define ETM_LAR_KEY 0xC5ACCE55
#define ETM_TraceMode() ETM->CR &= ~ETM_CR_PROGRAMMING
#define ETM_SetupMode() ETM->CR |= ETM_CR_PROGRAMMING
#define ETM_BASE 0xE0041000
#define ETM ((ETM_Type*)ETM_BASE)
#endif

2
Core/Inc/main.h
View File

@ -60,6 +60,8 @@ void Error_Handler(void);
/* Private defines -----------------------------------------------------------*/
#define LED1_Pin GPIO_PIN_9
#define LED1_GPIO_Port GPIOF
#define LED2_Pin GPIO_PIN_10
#define LED2_GPIO_Port GPIOF
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */

2
Core/Inc/stm32f4xx_it.h
View File

@ -53,8 +53,8 @@ void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
void TIM4_IRQHandler(void);
void TIM6_DAC_IRQHandler(void);
void TIM7_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */

2
Core/Inc/user_power_mgmt_profiles.h
View File

@ -127,7 +127,7 @@ static user_pm_vfs_t s_user_vfs_table[] = {
.APB1CLKDivider = RCC_HCLK_DIV2,
.APB2CLKDivider = RCC_HCLK_DIV2,
},
.Flash_Latency = FLASH_LATENCY_2,
.Flash_Latency = FLASH_LATENCY_1,
.Voltage_Scale = PWR_REGULATOR_VOLTAGE_SCALE2,
},
{ // LOW_2 = 24MHz

104
Core/Src/SystemView/SEGGER_SYSVIEW_Config_FreeRTOS.c Normal file
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@ -0,0 +1,104 @@
/*********************************************************************
* SEGGER Microcontroller GmbH *
* The Embedded Experts *
**********************************************************************
* *
* (c) 1995 - 2021 SEGGER Microcontroller GmbH *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER SystemView * Real-time application analysis *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* SEGGER strongly recommends to not make any changes *
* to or modify the source code of this software in order to stay *
* compatible with the SystemView and RTT protocol, and J-Link. *
* *
* Redistribution and use in source and binary forms, with or *
* without modification, are permitted provided that the following *
* condition is met: *
* *
* o Redistributions of source code must retain the above copyright *
* notice, this condition and the following disclaimer. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* SystemView version: 3.30 *
* *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : SEGGER_SYSVIEW_Config_FreeRTOS.c
Purpose : Sample setup configuration of SystemView with FreeRTOS.
Revision: $Rev: 7745 $
*/
#include "FreeRTOS.h"
#include "SEGGER_SYSVIEW.h"
extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
/*********************************************************************
*
* Defines, configurable
*
**********************************************************************
*/
// The application name to be displayed in SystemViewer
#define SYSVIEW_APP_NAME "FreeRTOS Demo Application"
// The target device name
#define SYSVIEW_DEVICE_NAME "Cortex-M4"
// Frequency of the timestamp. Must match SEGGER_SYSVIEW_GET_TIMESTAMP in SEGGER_SYSVIEW_Conf.h
#define SYSVIEW_TIMESTAMP_FREQ (configCPU_CLOCK_HZ)
// System Frequency. SystemcoreClock is used in most CMSIS compatible projects.
#define SYSVIEW_CPU_FREQ configCPU_CLOCK_HZ
// The lowest RAM address used for IDs (pointers)
#define SYSVIEW_RAM_BASE (0x10000000)
/*********************************************************************
*
* _cbSendSystemDesc()
*
* Function description
* Sends SystemView description strings.
*/
static void _cbSendSystemDesc(void) {
SEGGER_SYSVIEW_SendSysDesc("N="SYSVIEW_APP_NAME",D="SYSVIEW_DEVICE_NAME",O=FreeRTOS");
SEGGER_SYSVIEW_SendSysDesc("I#15=SysTick,I#46=TIM4,I#70=TIM6_DAC");
}
/*********************************************************************
*
* Global functions
*
**********************************************************************
*/
void SEGGER_SYSVIEW_Conf(void) {
SEGGER_SYSVIEW_Init(SYSVIEW_TIMESTAMP_FREQ, SYSVIEW_CPU_FREQ,
&SYSVIEW_X_OS_TraceAPI, _cbSendSystemDesc);
SEGGER_SYSVIEW_SetRAMBase(SYSVIEW_RAM_BASE);
}
/*************************** End of file ****************************/

146
Core/Src/main.c
View File

@ -26,6 +26,9 @@
#include "printf.h"
#include "user_power_mgmt.h"
#include "SEGGER_SYSVIEW.h"
#include "arm_etm.h"
/* USER CODE END Includes */
@ -46,7 +49,7 @@
/* Private variables ---------------------------------------------------------*/
RTC_HandleTypeDef hrtc;
TIM_HandleTypeDef htim6;
TIM_HandleTypeDef htim4;
UART_HandleTypeDef huart1;
@ -77,7 +80,7 @@ static void MX_GPIO_Init(void);
static void MX_RTC_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_FSMC_Init(void);
static void MX_TIM6_Init(void);
static void MX_TIM4_Init(void);
void StartDefaultTask(void *argument);
/* USER CODE BEGIN PFP */
@ -87,6 +90,65 @@ void StartDefaultTask(void *argument);
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
static void configure_etm_trace(void) {
DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN; // Enable IO trace pins
if (!(DBGMCU->CR & DBGMCU_CR_TRACE_IOEN))
{
// Some (all?) STM32s don't allow writes to DBGMCU register until
// C_DEBUGEN in CoreDebug->DHCSR is set. This cannot be set by the
// CPU itself, so in practice you need to connect to the CPU with
// a debugger once before resetting it.
return;
}
/* Configure Trace Port Interface Unit */
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // Enable access to registers
TPI->ACPR = 0; // Trace clock = HCLK/(x+1) = 8MHz = UART 's baudrate
// The HCLK of F105 is 8MHz so x is 0, and the F103 is 72MHz so x is 8
TPI->SPPR = 2; // Pin protocol = NRZ/USART
TPI->FFCR = 0x102; // TPIU packet framing enabled when bit 2 is set.
// You can use 0x100 if you only need DWT/ITM and not ETM.
/* Configure PC sampling and exception trace */
DWT->CTRL = (0 << DWT_CTRL_CYCTAP_Pos) // Prescaler for PC sampling
// 0 = x32, 1 = x512
| (0 << DWT_CTRL_POSTPRESET_Pos) // Postscaler for PC sampling
// Divider = value + 1
| (1 << DWT_CTRL_PCSAMPLENA_Pos) // Enable PC sampling
| (1 << DWT_CTRL_SYNCTAP_Pos) // Sync packet interval
// 0 = Off, 1 = Every 2^23 cycles,
// 2 = Every 2^25, 3 = Every 2^27
| (1 << DWT_CTRL_EXCTRCENA_Pos) // Enable exception trace
| (1 << DWT_CTRL_CYCCNTENA_Pos); // Enable cycle counter
/* Configure instrumentation trace macroblock */
ITM->LAR = 0xC5ACCE55;
ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) // Trace bus ID for TPIU
| (1 << ITM_TCR_DWTENA_Pos) // Enable events from DWT
| (1 << ITM_TCR_SYNCENA_Pos) // Enable sync packets
| (1 << ITM_TCR_ITMENA_Pos); // Main enable for ITM
ITM->TER = 0xFFFFFFFF; // Enable all stimulus ports
/* Configure embedded trace macroblock */
ETM->LAR = 0xC5ACCE55;
ETM_SetupMode();
ETM->CR = ETM_CR_ETMEN // Enable ETM output port
| ETM_CR_STALL_PROCESSOR // Stall processor when fifo is full
| ETM_CR_BRANCH_OUTPUT; // Report all branches
// | ETM_CR_PORTSIZE_8BIT; // Add this code in F103 to set port_size 21, 6, 5, 4 as 0, 0, 0, 1 for 8Bit.
ETM->TRACEIDR = 2; // Trace bus ID for TPIU
ETM->TECR1 = ETM_TECR1_EXCLUDE; // Trace always enabled
ETM->FFRR = ETM_FFRR_EXCLUDE; // Stalling always enabled
ETM->FFLR = 24; // Stall when less than N bytes free in FIFO (range 1..24)
// Larger values mean less latency in trace, but more stalls.
// ETM->TRIGGER = 0x0000406F; // Add this code in F103 to define the trigger event
// ETM->TEEVR = 0x0000006F; // Add this code in F103 to define an event to start/stop
// Note: we do not enable ETM trace yet, only for specific parts of code.
ETM_TraceMode();
}
/* USER CODE END 0 */
/**
@ -97,6 +159,8 @@ int main(void)
{
/* USER CODE BEGIN 1 */
configure_etm_trace();
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
@ -120,12 +184,14 @@ int main(void)
MX_RTC_Init();
MX_USART1_UART_Init();
MX_FSMC_Init();
MX_TIM6_Init();
MX_TIM4_Init();
/* USER CODE BEGIN 2 */
// Define heap region for heap_5.
vPortDefineHeapRegions(xHeapRegions);
SEGGER_SYSVIEW_Conf();
/* USER CODE END 2 */
/* Init scheduler */
@ -186,19 +252,14 @@ void SystemClock_Config(void)
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 168;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
@ -207,12 +268,12 @@ void SystemClock_Config(void)
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
{
Error_Handler();
}
@ -284,40 +345,51 @@ static void MX_RTC_Init(void)
}
/**
* @brief TIM6 Initialization Function
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM6_Init(void)
static void MX_TIM4_Init(void)
{
/* USER CODE BEGIN TIM6_Init 0 */
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM6_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
htim6.Init.Prescaler = 4000 - 1;
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
htim6.Init.Period = 1000;
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
htim4.Init.Prescaler = 8000-1;
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
htim4.Init.Period = 5000;
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_OnePulse_Init(&htim4, TIM_OPMODE_SINGLE) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM6_Init 2 */
/* USER CODE END TIM4_Init 2 */
}
@ -371,16 +443,20 @@ static void MX_GPIO_Init(void)
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_8|LED1_Pin, GPIO_PIN_SET);
/*Configure GPIO pin : LED1_Pin */
GPIO_InitStruct.Pin = LED1_Pin;
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : PF8 LED1_Pin LED2_Pin */
GPIO_InitStruct.Pin = GPIO_PIN_8|LED1_Pin|LED2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(LED1_GPIO_Port, &GPIO_InitStruct);
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
}
@ -488,13 +564,11 @@ void StartDefaultTask(void *argument)
HeapStats_t stats;
vPortGetHeapStats(&stats);
printf("Heap available: %d bytes.\r\n", stats.xAvailableHeapSpaceInBytes);
update_frequency_profile(USER_PM_VFS_LOW_1);
/* Infinite loop */
for(;;)
{
report_system_frequencies();
HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
osDelay(1000);
}
/* USER CODE END 5 */
@ -502,7 +576,7 @@ void StartDefaultTask(void *argument)
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM7 interrupt took place, inside
* @note This function is called when TIM6 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
@ -513,7 +587,7 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM7) {
if (htim->Instance == TIM6) {
HAL_IncTick();
}
/* USER CODE BEGIN Callback 1 */

34
Core/Src/stm32f4xx_hal_msp.c
View File

@ -141,19 +141,19 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
if(htim_base->Instance==TIM6)
if(htim_base->Instance==TIM4)
{
/* USER CODE BEGIN TIM6_MspInit 0 */
/* USER CODE BEGIN TIM4_MspInit 0 */
/* USER CODE END TIM6_MspInit 0 */
/* USER CODE END TIM4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
/* TIM6 interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
/* USER CODE BEGIN TIM6_MspInit 1 */
__HAL_RCC_TIM4_CLK_ENABLE();
/* TIM4 interrupt Init */
HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM4_IRQn);
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
@ -166,19 +166,19 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
*/
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
{
if(htim_base->Instance==TIM6)
if(htim_base->Instance==TIM4)
{
/* USER CODE BEGIN TIM6_MspDeInit 0 */
/* USER CODE BEGIN TIM4_MspDeInit 0 */
/* USER CODE END TIM6_MspDeInit 0 */
/* USER CODE END TIM4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM6_CLK_DISABLE();
__HAL_RCC_TIM4_CLK_DISABLE();
/* TIM6 interrupt DeInit */
HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn);
/* USER CODE BEGIN TIM6_MspDeInit 1 */
/* TIM4 interrupt DeInit */
HAL_NVIC_DisableIRQ(TIM4_IRQn);
/* USER CODE BEGIN TIM4_MspDeInit 1 */
/* USER CODE END TIM6_MspDeInit 1 */
/* USER CODE END TIM4_MspDeInit 1 */
}
}

50
Core/Src/stm32f4xx_hal_timebase_tim.c
View File

@ -26,12 +26,12 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim7;
TIM_HandleTypeDef htim6;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the TIM7 as a time base source.
* @brief This function configures the TIM6 as a time base source.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
@ -45,41 +45,41 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
uint32_t uwTimclock = 0;
uint32_t uwPrescalerValue = 0;
uint32_t pFLatency;
/*Configure the TIM7 IRQ priority */
HAL_NVIC_SetPriority(TIM7_IRQn, TickPriority ,0);
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
/* Enable the TIM7 global Interrupt */
HAL_NVIC_EnableIRQ(TIM7_IRQn);
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
/* Enable TIM7 clock */
__HAL_RCC_TIM7_CLK_ENABLE();
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
/* Compute TIM7 clock */
/* Compute TIM6 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
/* Compute the prescaler value to have TIM7 counter clock equal to 1MHz */
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
/* Initialize TIM7 */
htim7.Instance = TIM7;
/* Initialize TIM6 */
htim6.Instance = TIM6;
/* Initialize TIMx peripheral as follow:
+ Period = [(TIM7CLK/1000) - 1]. to have a (1/1000) s time base.
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim7.Init.Period = (1000000U / 1000U) - 1U;
htim7.Init.Prescaler = uwPrescalerValue;
htim7.Init.ClockDivision = 0;
htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
htim6.Init.Period = (1000000U / 1000U) - 1U;
htim6.Init.Prescaler = uwPrescalerValue;
htim6.Init.ClockDivision = 0;
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
if(HAL_TIM_Base_Init(&htim7) == HAL_OK)
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim7);
return HAL_TIM_Base_Start_IT(&htim6);
}
/* Return function status */
@ -88,26 +88,26 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
/**
* @brief Suspend Tick increment.
* @note Disable the tick increment by disabling TIM7 update interrupt.
* @note Disable the tick increment by disabling TIM6 update interrupt.
* @param None
* @retval None
*/
void HAL_SuspendTick(void)
{
/* Disable TIM7 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim7, TIM_IT_UPDATE);
/* Disable TIM6 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);
}
/**
* @brief Resume Tick increment.
* @note Enable the tick increment by Enabling TIM7 update interrupt.
* @note Enable the tick increment by Enabling TIM6 update interrupt.
* @param None
* @retval None
*/
void HAL_ResumeTick(void)
{
/* Enable TIM7 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim7, TIM_IT_UPDATE);
/* Enable TIM6 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

45
Core/Src/stm32f4xx_it.c
View File

@ -23,6 +23,9 @@
#include "stm32f4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "SEGGER_SYSVIEW.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -56,8 +59,8 @@
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern TIM_HandleTypeDef htim4;
extern TIM_HandleTypeDef htim6;
extern TIM_HandleTypeDef htim7;
/* USER CODE BEGIN EV */
@ -162,6 +165,26 @@ void DebugMon_Handler(void)
/* please refer to the startup file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles TIM4 global interrupt.
*/
void TIM4_IRQHandler(void)
{
/* USER CODE BEGIN TIM4_IRQn 0 */
SEGGER_SYSVIEW_RecordEnterISR();
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_9, GPIO_PIN_SET);
/* USER CODE END TIM4_IRQn 0 */
HAL_TIM_IRQHandler(&htim4);
/* USER CODE BEGIN TIM4_IRQn 1 */
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_9, GPIO_PIN_RESET);
SEGGER_SYSVIEW_RecordExitISR();
/* USER CODE END TIM4_IRQn 1 */
}
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
@ -169,27 +192,19 @@ void TIM6_DAC_IRQHandler(void)
{
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
SEGGER_SYSVIEW_RecordEnterISR();
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_8, GPIO_PIN_SET);
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_8, GPIO_PIN_RESET);
SEGGER_SYSVIEW_RecordExitISR();
/* USER CODE END TIM6_DAC_IRQn 1 */
}
/**
* @brief This function handles TIM7 global interrupt.
*/
void TIM7_IRQHandler(void)
{
/* USER CODE BEGIN TIM7_IRQn 0 */
/* USER CODE END TIM7_IRQn 0 */
HAL_TIM_IRQHandler(&htim7);
/* USER CODE BEGIN TIM7_IRQn 1 */
/* USER CODE END TIM7_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

30
Core/Src/user_freertos_support.c
View File

@ -5,19 +5,37 @@
#include "user_power_mgmt.h"
void vApplicationSleep(uint32_t xExpectedIdleTime) {
// Enter a critical section
__disable_irq();
static void pre_enter_lpm(void) {
// FreeRTOS tick uses SysTick timer, disable it.
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
// HAL SysTick uses TIM6, disable TIM6 interrupt.
HAL_SuspendTick();
__disable_irq();
__DSB();
__ISB();
}
static void post_enter_lpm(void) {
__enable_irq();
__DSB();
__ISB();
HAL_ResumeTick();
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
void vApplicationSleep(uint32_t xExpectedIdleTime) {
pre_enter_lpm();
eSleepModeStatus eSleepStatus = eTaskConfirmSleepModeStatus();
if(eSleepStatus == eAbortSleep) {
// Do nothing, just return.
post_enter_lpm();
}
else {
uint32_t actual_ms = user_pm_idle_timeout(xExpectedIdleTime / portTICK_RATE_MS);
vTaskStepTick(actual_ms);
post_enter_lpm();
}
// Exit critical section
__enable_irq();
}

45
Core/Src/user_power_mgmt.c
View File

@ -1,7 +1,7 @@
#include "stm32f4xx_hal.h"
#include "user_power_mgmt.h"
extern TIM_HandleTypeDef htim6;
extern TIM_HandleTypeDef htim4;
void user_pm_frequency_update_callback(void);
@ -22,10 +22,6 @@ static void user_pm_error_handler(void) {
}
}
static void user_pm_tim_callback(TIM_HandleTypeDef *htim) {
// No idea for now, just keep it.
}
/**
* @brief Set VFS mode, bad things happens if wrong sequence applied.
*
@ -98,38 +94,43 @@ HAL_StatusTypeDef user_pm_scale_vfs(user_pm_vfs_preset_t preset) {
* @return Time actually in sleep mode
*/
uint32_t user_pm_idle_timeout(uint32_t sleep_msec) {
user_pm_vfs_preset_t prev_preset = s_current_preset;
// user_pm_vfs_preset_t prev_preset = s_current_preset;
if(user_pm_scale_vfs(USER_PM_VFS_XLOW_2) != HAL_OK) {
user_pm_error_handler();
}
// if(user_pm_scale_vfs(USER_PM_VFS_XLOW_2) != HAL_OK) {
// user_pm_error_handler();
// }
if(sleep_msec > 65535) sleep_msec = 65535; // Cap. Maximum to 65535ms.
if(sleep_msec == 0) sleep_msec = 1;
// Configure TIM6 period.
htim6.Init.Period = sleep_msec;
HAL_TIM_Base_Init(&htim6);
HAL_TIM_RegisterCallback(&htim6, HAL_TIM_PERIOD_ELAPSED_CB_ID, user_pm_tim_callback);
__HAL_TIM_SET_AUTORELOAD(&htim4, sleep_msec);
__HAL_TIM_SET_COUNTER(&htim4, 0UL);
// SysTick uses TIM7, disable TIM7 interrupt.
HAL_SuspendTick();
// We do not register any callbacks here since PRIMASK = 1 will cause no ISR be called.
HAL_TIM_Base_Start_IT(&htim6);
// For some yet UNKNOWN reason, TIM UPDATE IRQ flag will be
// pended even BEFORE start counting.
__HAL_TIM_CLEAR_IT(&htim4, TIM_IT_UPDATE);
__WFI();
HAL_TIM_Base_Start_IT(&htim4);
HAL_TIM_Base_Stop_IT(&htim6);
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_10, GPIO_PIN_RESET);
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_10, GPIO_PIN_SET);
HAL_ResumeTick();
HAL_TIM_Base_Stop_IT(&htim4);
// Restore previous VFS profile
if(user_pm_scale_vfs(prev_preset) != HAL_OK) {
user_pm_error_handler();
}
// if(user_pm_scale_vfs(prev_preset) != HAL_OK) {
// user_pm_error_handler();
// }
// In case we woken up by another interrupt, return actual sleep'd time.
return __HAL_TIM_GET_COUNTER(&htim6);
if(__HAL_TIM_GET_FLAG(&htim4, TIM_FLAG_UPDATE)) {
return sleep_msec;
}
return __HAL_TIM_GET_COUNTER(&htim4);
}
__weak void user_pm_frequency_update_callback(void) {

2
Makefile
View File

@ -1,5 +1,5 @@
##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [3.14.1] date: [Wed Aug 25 02:18:49 CST 2021]
# File automatically-generated by tool: [projectgenerator] version: [3.14.1] date: [Mon Sep 06 18:42:07 CST 2021]
##########################################################################################################################
# ------------------------------------------------

29
Middlewares/CMakeLists.txt
View File

@ -13,6 +13,7 @@ set(RTOS_SOURCES
set(RTOS_INCLUDES
"../Core/Inc"
"../Core/Inc/SystemView"
"../Drivers/CMSIS/Include"
"../Drivers/CMSIS/Device/ST/STM32F4xx/Include"
"../Drivers/STM32F4xx_HAL_Driver/Inc"
@ -20,6 +21,8 @@ set(RTOS_INCLUDES
"Third_Party/FreeRTOS/Source/include"
"Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"
"Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
"Third_Party/SystemView_Target/SEGGER"
"Third_Party/SystemView_Target/Sample/FreeRTOSV10"
)
set(RTOS_DEFINES
@ -36,4 +39,28 @@ set(PRINTF_SOURCES
"Third_Party/printf/printf.c"
)
add_library(printf STATIC ${PRINTF_SOURCES})
add_library(printf STATIC ${PRINTF_SOURCES})
set(SYSVIEW_SOURCES
"Third_Party/SystemView_Target/Sample/FreeRTOSV10/SEGGER_SYSVIEW_FreeRTOS.c"
"Third_Party/SystemView_Target/SEGGER/SEGGER_RTT.c"
"Third_Party/SystemView_Target/SEGGER/SEGGER_SYSVIEW.c"
"Third_Party/SystemView_Target/SEGGER/SEGGER_RTT_ASM_ARMv7M.S"
)
set(SYSVIEW_INCLUDES
"../Core/Inc"
"../Core/Inc/SystemView"
"../Drivers/CMSIS/Include"
"../Drivers/CMSIS/Device/ST/STM32F4xx/Include"
"../Drivers/STM32F4xx_HAL_Driver/Inc"
"../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"
"Third_Party/FreeRTOS/Source/include"
"Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"
"Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
"Third_Party/SystemView_Target/SEGGER"
"Third_Party/SystemView_Target/Sample/FreeRTOSV10"
)
add_library(systemview STATIC ${SYSVIEW_SOURCES})
target_include_directories(systemview PRIVATE ${SYSVIEW_INCLUDES})

1
Middlewares/Third_Party/SystemView_Target vendored Submodule

@ -0,0 +1 @@
Subproject commit 5a9aff1f4c7d183f5995599a8f6711315e6873e1

182
STM32F407ZE_MRB.ioc
View File

@ -20,66 +20,70 @@ Mcu.IP2=NVIC
Mcu.IP3=RCC
Mcu.IP4=RTC
Mcu.IP5=SYS
Mcu.IP6=TIM6
Mcu.IP6=TIM4
Mcu.IP7=USART1
Mcu.IPNb=8
Mcu.Name=STM32F407Z(E-G)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PC14-OSC32_IN
Mcu.Pin1=PC15-OSC32_OUT
Mcu.Pin10=PH1-OSC_OUT
Mcu.Pin11=PF12
Mcu.Pin12=PF13
Mcu.Pin13=PF14
Mcu.Pin14=PF15
Mcu.Pin15=PG0
Mcu.Pin16=PG1
Mcu.Pin17=PE7
Mcu.Pin18=PE8
Mcu.Pin19=PE9
Mcu.Pin10=PF10
Mcu.Pin11=PH0-OSC_IN
Mcu.Pin12=PH1-OSC_OUT
Mcu.Pin13=PF12
Mcu.Pin14=PF13
Mcu.Pin15=PF14
Mcu.Pin16=PF15
Mcu.Pin17=PG0
Mcu.Pin18=PG1
Mcu.Pin19=PE7
Mcu.Pin2=PF0
Mcu.Pin20=PE10
Mcu.Pin21=PE11
Mcu.Pin22=PE12
Mcu.Pin23=PE13
Mcu.Pin24=PE14
Mcu.Pin25=PE15
Mcu.Pin26=PD8
Mcu.Pin27=PD9
Mcu.Pin28=PD10
Mcu.Pin29=PD11
Mcu.Pin20=PE8
Mcu.Pin21=PE9
Mcu.Pin22=PE10
Mcu.Pin23=PE11
Mcu.Pin24=PE12
Mcu.Pin25=PE13
Mcu.Pin26=PE14
Mcu.Pin27=PE15
Mcu.Pin28=PD8
Mcu.Pin29=PD9
Mcu.Pin3=PF1
Mcu.Pin30=PD12
Mcu.Pin31=PD13
Mcu.Pin32=PD14
Mcu.Pin33=PD15
Mcu.Pin34=PG2
Mcu.Pin35=PG3
Mcu.Pin36=PG4
Mcu.Pin37=PG5
Mcu.Pin38=PA9
Mcu.Pin39=PA10
Mcu.Pin30=PD10
Mcu.Pin31=PD11
Mcu.Pin32=PD12
Mcu.Pin33=PD13
Mcu.Pin34=PD14
Mcu.Pin35=PD15
Mcu.Pin36=PG2
Mcu.Pin37=PG3
Mcu.Pin38=PG4
Mcu.Pin39=PG5
Mcu.Pin4=PF2
Mcu.Pin40=PA13
Mcu.Pin41=PA14
Mcu.Pin42=PD0
Mcu.Pin43=PD1
Mcu.Pin44=PD4
Mcu.Pin45=PD5
Mcu.Pin46=PG10
Mcu.Pin47=PE0
Mcu.Pin48=PE1
Mcu.Pin49=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin40=PA9
Mcu.Pin41=PA10
Mcu.Pin42=PA13
Mcu.Pin43=PA14
Mcu.Pin44=PD0
Mcu.Pin45=PD1
Mcu.Pin46=PD4
Mcu.Pin47=PD5
Mcu.Pin48=PG10
Mcu.Pin49=PB3
Mcu.Pin5=PF3
Mcu.Pin50=VP_RTC_VS_RTC_Activate
Mcu.Pin51=VP_RTC_VS_RTC_Calendar
Mcu.Pin52=VP_SYS_VS_tim7
Mcu.Pin53=VP_TIM6_VS_ClockSourceINT
Mcu.Pin50=PE0
Mcu.Pin51=PE1
Mcu.Pin52=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin53=VP_RTC_VS_RTC_Activate
Mcu.Pin54=VP_RTC_VS_RTC_Calendar
Mcu.Pin55=VP_SYS_VS_tim6
Mcu.Pin56=VP_TIM4_VS_ClockSourceINT
Mcu.Pin57=VP_TIM4_VS_OPM
Mcu.Pin6=PF4
Mcu.Pin7=PF5
Mcu.Pin8=PF9
Mcu.Pin9=PH0-OSC_IN
Mcu.PinsNb=54
Mcu.Pin8=PF8
Mcu.Pin9=PF9
Mcu.PinsNb=58
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F407ZETx
@ -98,19 +102,21 @@ NVIC.SavedPendsvIrqHandlerGenerated=true
NVIC.SavedSvcallIrqHandlerGenerated=true
NVIC.SavedSystickIrqHandlerGenerated=true
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
NVIC.TIM6_DAC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
NVIC.TIM7_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM7_IRQn
NVIC.TimeBaseIP=TIM7
NVIC.TIM4_IRQn=true\:0\:0\:true\:false\:true\:false\:true\:true
NVIC.TIM6_DAC_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
NVIC.TimeBase=TIM6_DAC_IRQn
NVIC.TimeBaseIP=TIM6
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
PA13.Mode=Serial_Wire
PA13.Mode=Trace_Asynchronous_SW
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
PA14.Mode=Trace_Asynchronous_SW
PA14.Signal=SYS_JTCK-SWCLK
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB3.Mode=Trace_Asynchronous_SW
PB3.Signal=SYS_JTDO-SWO
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
@ -298,6 +304,10 @@ PE8.Signal=FSMC_D5_DA5
PE9.Signal=FSMC_D6_DA6
PF0.Signal=FSMC_A0
PF1.Signal=FSMC_A1
PF10.GPIOParameters=GPIO_Label
PF10.GPIO_Label=LED2
PF10.Locked=true
PF10.Signal=GPIO_Output
PF12.Signal=FSMC_A6
PF13.Signal=FSMC_A7
PF14.Signal=FSMC_A8
@ -306,6 +316,10 @@ PF2.Signal=FSMC_A2
PF3.Signal=FSMC_A3
PF4.Signal=FSMC_A4
PF5.Signal=FSMC_A5
PF8.GPIOParameters=PinState
PF8.Locked=true
PF8.PinState=GPIO_PIN_SET
PF8.Signal=GPIO_Output
PF9.GPIOParameters=PinState,GPIO_Label
PF9.GPIO_Label=LED1
PF9.Locked=true
@ -351,43 +365,44 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=Makefile
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_RTC_Init-RTC-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_FSMC_Init-FSMC-false-HAL-true,6-MX_TIM6_Init-TIM6-false-HAL-true
RCC.48MHZClocksFreq_Value=84000000
RCC.AHBFreq_Value=168000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=42000000
RCC.APB1TimFreq_Value=84000000
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_RTC_Init-RTC-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_FSMC_Init-FSMC-false-HAL-true,6-MX_TIM4_Init-TIM4-false-HAL-true
RCC.48MHZClocksFreq_Value=32000000
RCC.AHBFreq_Value=8000000
RCC.APB1CLKDivider=RCC_HCLK_DIV2
RCC.APB1Freq_Value=4000000
RCC.APB1TimFreq_Value=8000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=84000000
RCC.APB2TimFreq_Value=168000000
RCC.CortexFreq_Value=168000000
RCC.APB2Freq_Value=4000000
RCC.APB2TimFreq_Value=8000000
RCC.CortexFreq_Value=8000000
RCC.EnbaleCSS=true
RCC.EthernetFreq_Value=168000000
RCC.FCLKCortexFreq_Value=168000000
RCC.EthernetFreq_Value=8000000
RCC.FCLKCortexFreq_Value=8000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=168000000
RCC.HCLKFreq_Value=8000000
RCC.HSE_VALUE=8000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=192000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EnbaleCSS,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,RCC_MCODiv2,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EnbaleCSS,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLP,PLLQCLKFreq_Value,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,RCC_MCODiv2,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=33600000
RCC.PLLCLKFreq_Value=168000000
RCC.MCO2PinFreq_Value=1600000
RCC.PLLCLKFreq_Value=32000000
RCC.PLLM=4
RCC.PLLN=168
RCC.PLLQCLKFreq_Value=84000000
RCC.PLLN=64
RCC.PLLP=RCC_PLLP_DIV4
RCC.PLLQCLKFreq_Value=32000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE2
RCC.RCC_MCODiv2=RCC_MCODIV_5
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=4000000
RCC.SYSCLKFreq_VALUE=168000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.SYSCLKFreq_VALUE=8000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSE
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=336000000
RCC.VCOOutputFreq_Value=128000000
RCC.VcooutputI2S=192000000
RTC.Format=RTC_FORMAT_BIN
RTC.IPParameters=Format
@ -469,9 +484,10 @@ SH.FSMC_NOE.0=FSMC_NOE,Sram1
SH.FSMC_NOE.ConfNb=1
SH.FSMC_NWE.0=FSMC_NWE,Sram1
SH.FSMC_NWE.ConfNb=1
TIM6.IPParameters=Prescaler,Period
TIM6.Period=1000
TIM6.Prescaler=4000 - 1
TIM4.CounterMode=TIM_COUNTERMODE_UP
TIM4.IPParameters=Prescaler,CounterMode,Period
TIM4.Period=5000
TIM4.Prescaler=8000-1
USART1.BaudRate=115200
USART1.IPParameters=VirtualMode,BaudRate
USART1.VirtualMode=VM_ASYNC
@ -481,8 +497,10 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
VP_SYS_VS_tim7.Mode=TIM7
VP_SYS_VS_tim7.Signal=SYS_VS_tim7
VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT
VP_SYS_VS_tim6.Mode=TIM6
VP_SYS_VS_tim6.Signal=SYS_VS_tim6
VP_TIM4_VS_ClockSourceINT.Mode=Internal
VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT
VP_TIM4_VS_OPM.Mode=OPM_bit
VP_TIM4_VS_OPM.Signal=TIM4_VS_OPM
board=custom