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Updated flexbus driver, changed file permission on SIM.

This commit is contained in:
imi415 2022-06-17 09:32:11 +08:00
parent ede33dcf05
commit ebf85f1dc6
4 changed files with 135 additions and 103 deletions
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168
devices/MK60D10/drivers/fsl_flexbus.c
View File

@ -1,35 +1,18 @@
/* /*
* Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2019 NXP
* All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without modification, * SPDX-License-Identifier: BSD-3-Clause
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#include "fsl_flexbus.h" #include "fsl_flexbus.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.flexbus"
#endif
/******************************************************************************* /*******************************************************************************
* Prototypes * Prototypes
******************************************************************************/ ******************************************************************************/
@ -77,13 +60,36 @@ static uint32_t FLEXBUS_GetInstance(FB_Type *base)
return instance; return instance;
} }
/*!
* brief Initializes and configures the FlexBus module.
*
* This function enables the clock gate for FlexBus module.
* Only chip 0 is validated and set to known values. Other chips are disabled.
* Note that in this function, certain parameters, depending on external memories, must
* be set before using the FLEXBUS_Init() function.
* This example shows how to set up the uart_state_t and the
* flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
* in these parameters.
code
flexbus_config_t flexbusConfig;
FLEXBUS_GetDefaultConfig(&flexbusConfig);
flexbusConfig.waitStates = 2U;
flexbusConfig.chipBaseAddress = 0x60000000U;
flexbusConfig.chipBaseAddressMask = 7U;
FLEXBUS_Init(FB, &flexbusConfig);
endcode
*
* param base FlexBus peripheral address.
* param config Pointer to the configuration structure
*/
void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config) void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
{ {
assert(config != NULL); assert(config != NULL);
assert(config->chip < FB_CSAR_COUNT); assert(config->chip < FB_CSAR_COUNT);
assert(config->waitStates <= 0x3FU); assert(config->waitStates <= 0x3FU);
assert(config->secondaryWaitStates <= 0x3FU);
uint32_t chip = config->chip; uint32_t chip = config->chip;
uint32_t reg_value = 0; uint32_t reg_value = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -91,8 +97,8 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the corresponding register to default state */ /* Reset the associated register to default state */
/* Reset CSMR register, all chips not valid (disabled) */ /* Set CSMR register, all chips not valid (disabled) */
base->CS[chip].CSMR = 0x0000U; base->CS[chip].CSMR = 0x0000U;
/* Set default base address */ /* Set default base address */
base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
@ -101,43 +107,42 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
/* Set FB_CSPMCR register */ /* Set FB_CSPMCR register */
/* FlexBus signal group 1 multiplex control */ /* FlexBus signal group 1 multiplex control */
reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT; reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
/* FlexBus signal group 2 multiplex control */ /* FlexBus signal group 2 multiplex control */
reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT; reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
/* FlexBus signal group 3 multiplex control */ /* FlexBus signal group 3 multiplex control */
reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT; reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
/* FlexBus signal group 4 multiplex control */ /* FlexBus signal group 4 multiplex control */
reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT; reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
/* FlexBus signal group 5 multiplex control */ /* FlexBus signal group 5 multiplex control */
reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT; reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
/* Write to CSPMCR register */ /* Write to CSPMCR register */
base->CSPMCR = reg_value; base->CSPMCR = reg_value;
/* Update chip value */
chip = config->chip;
/* Base address */ /* Base address */
reg_value = config->chipBaseAddress; reg_value = config->chipBaseAddress;
/* Write to CSAR register */ /* Write to CSAR register */
base->CS[chip].CSAR = reg_value; base->CS[chip].CSAR = reg_value;
/* Chip-select validation */ /* Chip-select validation */
reg_value = 0x1U << FB_CSMR_V_SHIFT; reg_value = 0x1U << FB_CSMR_V_SHIFT;
/* Write protect */ /* Write protect */
reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT; reg_value |= ((uint32_t)config->writeProtect) << FB_CSMR_WP_SHIFT;
/* Base address mask */ /* Base address mask */
reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT; reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;
/* Write to CSMR register */ /* Write to CSMR register */
base->CS[chip].CSMR = reg_value; base->CS[chip].CSMR = reg_value;
/* Burst write */ /* Burst write */
reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT; reg_value = ((uint32_t)config->burstWrite) << FB_CSCR_BSTW_SHIFT;
/* Burst read */ /* Burst read */
reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT; reg_value |= ((uint32_t)config->burstRead) << FB_CSCR_BSTR_SHIFT;
/* Byte-enable mode */ /* Byte-enable mode */
reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT; reg_value |= ((uint32_t)config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
/* Port size */ /* Port size */
reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT; reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;
/* The internal transfer acknowledge for accesses */ /* The internal transfer acknowledge for accesses */
reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT; reg_value |= ((uint32_t)config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
/* Byte-Lane shift */ /* Byte-Lane shift */
reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT; reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;
/* The number of wait states */ /* The number of wait states */
@ -149,11 +154,16 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
/* Address setup */ /* Address setup */
reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT; reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;
/* Extended transfer start/extended address latch */ /* Extended transfer start/extended address latch */
reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT; reg_value |= ((uint32_t)config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
/* Secondary wait state */ /* Secondary wait state */
reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT; if (config->secondaryWaitStatesEnable)
{
reg_value |= FB_CSCR_SWSEN_MASK;
reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWS_SHIFT;
}
/* Write to CSCR register */ /* Write to CSCR register */
base->CS[chip].CSCR = reg_value; base->CS[chip].CSCR = reg_value;
/* FlexBus signal group 1 multiplex control */ /* FlexBus signal group 1 multiplex control */
reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT; reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
/* FlexBus signal group 2 multiplex control */ /* FlexBus signal group 2 multiplex control */
@ -166,8 +176,21 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT; reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
/* Write to CSPMCR register */ /* Write to CSPMCR register */
base->CSPMCR = reg_value; base->CSPMCR = reg_value;
/* Enable CSPMCR0[V] to make all chip select registers take effect. */
if (chip != 0UL)
{
base->CS[0].CSMR |= FB_CSMR_V_MASK;
}
} }
/*!
* brief De-initializes a FlexBus instance.
*
* This function disables the clock gate of the FlexBus module clock.
*
* param base FlexBus peripheral address.
*/
void FLEXBUS_Deinit(FB_Type *base) void FLEXBUS_Deinit(FB_Type *base)
{ {
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -176,25 +199,56 @@ void FLEXBUS_Deinit(FB_Type *base)
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
} }
/*!
* brief Initializes the FlexBus configuration structure.
*
* This function initializes the FlexBus configuration structure to default value. The default
* values are.
code
fbConfig->chip = 0;
fbConfig->writeProtect = false;
fbConfig->burstWrite = false;
fbConfig->burstRead = false;
fbConfig->byteEnableMode = false;
fbConfig->autoAcknowledge = true;
fbConfig->extendTransferAddress = false;
fbConfig->secondaryWaitStatesEnable = false;
fbConfig->byteLaneShift = kFLEXBUS_NotShifted;
fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle;
fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles;
fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge;
fbConfig->portSize = kFLEXBUS_1Byte;
fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;
fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ;
fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;
fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST;
fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;
endcode
* param config Pointer to the initialization structure.
* see FLEXBUS_Init
*/
void FLEXBUS_GetDefaultConfig(flexbus_config_t *config) void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
{ {
config->chip = 0; /* Chip 0 FlexBus for validation */ /* Initializes the configure structure to zero. */
config->writeProtect = 0; /* Write accesses are allowed */ (void)memset(config, 0, sizeof(*config));
config->burstWrite = 0; /* Burst-Write disable */
config->burstRead = 0; /* Burst-Read disable */ config->chip = 0; /* Chip 0 FlexBus for validation */
config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */ config->writeProtect = false; /* Write accesses are allowed */
config->autoAcknowledge = true; /* Auto-Acknowledge enable */ config->burstWrite = false; /* Burst-Write disable */
config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */ config->burstRead = false; /* Burst-Read disable */
config->secondaryWaitStates = 0; /* Secondary wait state disable */ config->byteEnableMode = false; /* Byte-Enable mode is asserted for data write only */
config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */ config->autoAcknowledge = true; /* Auto-Acknowledge enable */
config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */ config->extendTransferAddress = false; /* Extend transfer start/extend address latch disable */
config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */ config->secondaryWaitStatesEnable = false; /* Secondary wait state disable */
config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
config->addressSetup = config->addressSetup =
kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */ kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */ config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */
config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */ config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */
config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */ config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */
config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */ config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */
config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */ config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */
config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */ config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */
} }

70
devices/MK60D10/drivers/fsl_flexbus.h
View File

@ -1,31 +1,9 @@
/* /*
* Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2019 NXP
* All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without modification, * SPDX-License-Identifier: BSD-3-Clause
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef _FSL_FLEXBUS_H_ #ifndef _FSL_FLEXBUS_H_
@ -38,15 +16,14 @@
* @{ * @{
*/ */
/******************************************************************************* /*******************************************************************************
* Definitions * Definitions
******************************************************************************/ ******************************************************************************/
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ #define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
/*@}*/ /*@}*/
/*! /*!
* @brief Defines port size for FlexBus peripheral. * @brief Defines port size for FlexBus peripheral.
@ -54,7 +31,7 @@
typedef enum _flexbus_port_size typedef enum _flexbus_port_size
{ {
kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */ kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */
kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */ kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */
kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */ kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */
} flexbus_port_size_t; } flexbus_port_size_t;
@ -63,7 +40,7 @@ typedef enum _flexbus_port_size
*/ */
typedef enum _flexbus_write_address_hold typedef enum _flexbus_write_address_hold
{ {
kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */ kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */
kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */ kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */
kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */ kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */
kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */ kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */
@ -76,8 +53,8 @@ typedef enum _flexbus_read_address_hold
{ {
kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */ kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */
kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */ kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */
kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */ kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */
kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */ kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */
} flexbus_read_address_hold_t; } flexbus_read_address_hold_t;
/*! /*!
@ -85,9 +62,9 @@ typedef enum _flexbus_read_address_hold
*/ */
typedef enum _flexbus_address_setup typedef enum _flexbus_address_setup
{ {
kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */ kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */
kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */ kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */
kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */ kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */
kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */ kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */
} flexbus_address_setup_t; } flexbus_address_setup_t;
@ -97,7 +74,7 @@ typedef enum _flexbus_address_setup
typedef enum _flexbus_bytelane_shift typedef enum _flexbus_bytelane_shift
{ {
kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */ kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */
kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */ kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */
} flexbus_bytelane_shift_t; } flexbus_bytelane_shift_t;
/*! /*!
@ -107,7 +84,7 @@ typedef enum _flexbus_multiplex_group1_signal
{ {
kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */ kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */
kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */ kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */
kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */ kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */
} flexbus_multiplex_group1_t; } flexbus_multiplex_group1_t;
/*! /*!
@ -115,8 +92,8 @@ typedef enum _flexbus_multiplex_group1_signal
*/ */
typedef enum _flexbus_multiplex_group2_signal typedef enum _flexbus_multiplex_group2_signal
{ {
kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */ kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */
kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */ kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */
kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */ kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */
} flexbus_multiplex_group2_t; } flexbus_multiplex_group2_t;
@ -125,8 +102,8 @@ typedef enum _flexbus_multiplex_group2_signal
*/ */
typedef enum _flexbus_multiplex_group3_signal typedef enum _flexbus_multiplex_group3_signal
{ {
kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */ kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */
kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */ kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */
kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */ kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */
} flexbus_multiplex_group3_t; } flexbus_multiplex_group3_t;
@ -135,8 +112,8 @@ typedef enum _flexbus_multiplex_group3_signal
*/ */
typedef enum _flexbus_multiplex_group4_signal typedef enum _flexbus_multiplex_group4_signal
{ {
kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */ kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */
kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */ kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */
kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */ kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */
} flexbus_multiplex_group4_t; } flexbus_multiplex_group4_t;
@ -145,8 +122,8 @@ typedef enum _flexbus_multiplex_group4_signal
*/ */
typedef enum _flexbus_multiplex_group5_signal typedef enum _flexbus_multiplex_group5_signal
{ {
kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */ kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */
kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */ kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */
kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */ kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */
} flexbus_multiplex_group5_t; } flexbus_multiplex_group5_t;
@ -157,6 +134,7 @@ typedef struct _flexbus_config
{ {
uint8_t chip; /*!< Chip FlexBus for validation */ uint8_t chip; /*!< Chip FlexBus for validation */
uint8_t waitStates; /*!< Value of wait states */ uint8_t waitStates; /*!< Value of wait states */
uint8_t secondaryWaitStates; /*!< Value of secondary wait states */
uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */ uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */
uint32_t chipBaseAddressMask; /*!< Chip base address mask */ uint32_t chipBaseAddressMask; /*!< Chip base address mask */
bool writeProtect; /*!< Write protected */ bool writeProtect; /*!< Write protected */
@ -165,7 +143,7 @@ typedef struct _flexbus_config
bool byteEnableMode; /*!< Byte-enable mode support */ bool byteEnableMode; /*!< Byte-enable mode support */
bool autoAcknowledge; /*!< Auto acknowledge setting */ bool autoAcknowledge; /*!< Auto acknowledge setting */
bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */ bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */
bool secondaryWaitStates; /*!< Secondary wait states number */ bool secondaryWaitStatesEnable; /*!< Enable secondary wait states */
flexbus_port_size_t portSize; /*!< Port size of transfer */ flexbus_port_size_t portSize; /*!< Port size of transfer */
flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */ flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */
flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */ flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */
@ -262,4 +240,4 @@ void FLEXBUS_GetDefaultConfig(flexbus_config_t *config);
/*! @}*/ /*! @}*/
#endif /* _FSL_FLEXBUS_H_ */ #endif /* _FSL_FLEXBUS_H_ */

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devices/MK60D10/drivers/fsl_sim.c Executable file → Normal file
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devices/MK60D10/drivers/fsl_sim.h Executable file → Normal file
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