Flexbus: Only resets necessary chip registers.
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d22b5f5974
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@ -83,7 +83,7 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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assert(config->chip < FB_CSAR_COUNT);
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assert(config->chip < FB_CSAR_COUNT);
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assert(config->waitStates <= 0x3FU);
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assert(config->waitStates <= 0x3FU);
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uint32_t chip = 0;
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uint32_t chip = config->chip;
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uint32_t reg_value = 0;
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uint32_t reg_value = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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@ -91,16 +91,14 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset all the register to default state */
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/* Reset the corresponding register to default state */
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for (chip = 0; chip < FB_CSAR_COUNT; chip++)
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/* Reset CSMR register, all chips not valid (disabled) */
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{
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base->CS[chip].CSMR = 0x0000U;
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/* Reset CSMR register, all chips not valid (disabled) */
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/* Set default base address */
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base->CS[chip].CSMR = 0x0000U;
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base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
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/* Set default base address */
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/* Reset FB_CSCRx register */
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base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
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base->CS[chip].CSCR = 0x0000U;
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/* Reset FB_CSCRx register */
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base->CS[chip].CSCR = 0x0000U;
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}
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/* Set FB_CSPMCR register */
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/* Set FB_CSPMCR register */
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/* FlexBus signal group 1 multiplex control */
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/* FlexBus signal group 1 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
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reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
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