Updated docs.
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Boot.md
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Boot.md
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# STi7105 hardware boot procedure
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## What we have learned
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* STi7105 starts execution at address `0x0000_0000`, in little endian mode.
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* Boot from SPI flash: the flash is mapped to EMI address space at `0x0000_0000`, determined by hardware pins.
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* The initialization process configures a bunch of registers, incl. clock and peripherals.
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* SH-4 CPU has two address modes, either 29bits or 32bits. The memory mapping for both modes is different.
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* As on-chip RAM is never found in documentation, we can assume that LMI DDR2 SDRAM is initialized before execution starts
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* ...which probably initialized by hardware or BootROM.
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* The LMI is mapped at `0x0C00_0000` in 29bit mode, `0x4000_0000` in 32bit mode.
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* The Github repo contains board support for this specific board(GB620)
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* Red LED is `P0_4`, Green LED is `P0_5`
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## TODO
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* Proper lds for bare metal testing
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* Proper assembly startup for bare metal testing
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## Supplementary files
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[Check Here](https://cloud.imi.moe/s/AFzsnEKNfxQYjjC)
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* STi7105 starts execution at address `0xA000_0000`, in little endian mode.
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* Boot from SPI flash: the flash is mapped to EMI address space at `0xA000_0000`, determined by hardware pins.
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* In 29-bit mode, these ranges are the same EMI address space as the processor simply discarded the higher 3 address bits.
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* The EMI can only be accessed in 32 bits, so XIP cannot be achieved.
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* MMU is forced active in 32bit(SE) mode, TLB or PMB has to be configured before mode switching
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* Most address space which PMB can configure is in P2/P3, which cannot be accessed when in user mode (U0)
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| Blue LED | PIO0_5 | N/A (GPIO) | Active low |
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| UART header TX | PIO4_0 | ALT_3 | ASC2 |
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| UART header RX | PIO4_1 | ALT_3 | ASC2, Default routed |
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## TODO
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* FreeRTOS
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* More peripheral drivers
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* U-Boot (finally)
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* Linux Kernel (in some future we can't expect)
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## Supplementary files
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[Check Here](https://cloud.imi.moe/s/AFzsnEKNfxQYjjC)
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