2022-06-25 16:19:46 +00:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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2018-07-18 20:34:23 +00:00
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%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
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2022-04-21 05:53:54 +00:00
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%D%/riscv/libriscv.la \
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%D%/xtensa/libxtensa.la \
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%D%/espressif/libespressif.la
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2018-07-18 20:34:23 +00:00
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2020-08-12 11:54:10 +00:00
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%C%_libtarget_la_CPPFLAGS = $(AM_CPPFLAGS)
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2013-08-08 21:45:47 +00:00
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2016-11-06 19:19:26 +00:00
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STARTUP_TCL_SRCS += %D%/startup.tcl
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2009-10-14 07:32:42 +00:00
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2016-11-06 19:19:26 +00:00
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noinst_LTLIBRARIES += %D%/libtarget.la
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%C%_libtarget_la_SOURCES = \
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2009-11-10 12:27:02 +00:00
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$(TARGET_CORE_SRC) \
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$(ARM_DEBUG_SRC) \
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$(ARMV4_5_SRC) \
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$(ARMV6_SRC) \
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$(ARMV7_SRC) \
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$(ARM_MISC_SRC) \
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2010-08-15 19:51:34 +00:00
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$(AVR32_SRC) \
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2009-11-10 12:27:02 +00:00
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$(MIPS32_SRC) \
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2013-02-05 01:34:18 +00:00
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$(NDS32_SRC) \
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2017-11-06 18:56:28 +00:00
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$(STM8_SRC) \
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2014-02-06 17:11:15 +00:00
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$(INTEL_IA32_SRC) \
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2018-08-29 00:18:01 +00:00
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$(ESIRISC_SRC) \
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Introduce ARCv2 architecture related code
This patch is an initial bump of ARC-specific code
which implements the ARCv2 target(EMSK board) initializing
routine and some basic remote connection/load/continue
functionality.
Changes:
03.12.2019:
-Add return value checks.
-Using static code analizer next fixes were made:
Mem leak in functions:
arc_jtag_read_memory,arc_jtag_read_memory,
arc_jtag_write_registers, arc_jtag_read_registers,
jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct,
arc_build_reg_cache, arc_mem_read.
Dead code in "arc_mem_read";
In arc_save_context, arc_restore_context correct arguments
in"memset" calls.
In "build_bcr_reg_cache", "arc_build_reg_cache" check
if list is not empty.
29.12.2019
-Moved code from arc_v2.c to arc.c
-Added checks of the result of calloc/malloc calls
-Reworked arc_cmd.c: replaced spagetty code with functions
-Moved to one style in if statements - to "if(!bla)"
-Changed Licence headers
22.01.2020
-Removed unused variables in arc_common
-Renamed register operation functions
-Introduced arc_deinit_target function
-Fixed interrupt handling in halt/resume:
* add irq_state field in arc_common
* fix irq enable/disable calls ( now STATUS32 register is used)
-Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32()
-Made some cleanup
30.01.2020
-Removed redundant arc_register struct, moved target link to arc_reg_desc
-Introduced link to BCR reg cache in arc_common for freeing memory.
-Now arc_deinit_target frees all arc-related allocated memory.
Valgrind shows no memory leaks.
-Inroduced arch description in arc.c
01.02.2020
-Remove small memory allocations in arc_init_reg. Instead created reg_value
and feature fields in arc_reg_desc.
-Add return value for arc_init_reg() func.
-Replaced some integer constants(61,62,63) with defines.
-Removed redundant conversions in arc_reg_get_field().
-Moved iccm/dccm configuration code from arc_configure()
to separate functions.
19.02.2020
-Change sizeof(struct) to sizeof(*ptr) in allocations
-Changed if/while(ptr != NULL) to if/while(ptr)
-Removed unused variables from struct arc_jtag
-Add additional structs to arc_reg_data_type
to reduce amount of memory allocations calls
and simplifying memory freeing.
-Add helper arc_reg_bitfield_t struct which includes
reg_data_type_bitfield object and char[] name. Reduces
memory allocations calls.
-Add limit for reg_type/reg_type_field names(20 symbols).
-Add in jim_arc_add_reg_type*() functions additional
argnument checks(amount of field/name size).
-In jim_arc_add_reg_type*() reduced amount of memory allocations.
-Cleanup of jim_arc_add_reg_type*() functions.
-For commands update ".usage" fields according docopt.
-Cleanup in arc_jtag.c
-Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*()
-Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs
during regiter r/w.
24.02:
-Change include guards in arc* files according coding style
-Remove _t suffix in struct arc_reg_bitfield_t
-Some cleanup
Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5332
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-01-27 12:22:27 +00:00
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$(ARC_SRC) \
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2016-11-06 19:19:26 +00:00
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%D%/avrt.c \
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%D%/dsp563xx.c \
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%D%/dsp563xx_once.c \
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%D%/dsp5680xx.c \
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2019-06-17 22:46:11 +00:00
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%D%/hla_target.c \
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$(ARMV8_SRC) \
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$(MIPS64_SRC)
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2015-01-16 01:22:20 +00:00
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2020-08-12 11:54:10 +00:00
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if HAVE_CAPSTONE
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%C%_libtarget_la_CPPFLAGS += $(CAPSTONE_CFLAGS)
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%C%_libtarget_la_LIBADD += $(CAPSTONE_LIBS)
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endif
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2009-11-10 12:27:02 +00:00
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TARGET_CORE_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/algorithm.c \
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%D%/register.c \
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%D%/image.c \
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%D%/breakpoints.c \
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%D%/target.c \
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%D%/target_request.c \
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%D%/testee.c \
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2018-05-13 15:39:06 +00:00
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%D%/semihosting_common.c \
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2020-09-17 13:23:31 +00:00
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%D%/smp.c \
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%D%/rtt.c
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2009-11-10 12:27:02 +00:00
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ARMV4_5_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/armv4_5.c \
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%D%/armv4_5_mmu.c \
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%D%/armv4_5_cache.c \
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2009-11-10 12:27:02 +00:00
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$(ARM7_9_SRC)
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ARM7_9_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/arm7_9_common.c \
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%D%/arm7tdmi.c \
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%D%/arm720t.c \
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%D%/arm9tdmi.c \
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%D%/arm920t.c \
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%D%/arm966e.c \
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%D%/arm946e.c \
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%D%/arm926ejs.c \
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%D%/feroceon.c
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2009-11-10 12:27:02 +00:00
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ARM_MISC_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/fa526.c \
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%D%/xscale.c
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2009-11-10 12:27:02 +00:00
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ARMV6_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/arm11.c \
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%D%/arm11_dbgtap.c
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2009-11-10 12:27:02 +00:00
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ARMV7_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/armv7m.c \
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%D%/armv7m_trace.c \
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%D%/cortex_m.c \
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%D%/armv7a.c \
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2016-07-14 19:00:59 +00:00
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%D%/armv7a_mmu.c \
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2016-11-06 19:19:26 +00:00
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%D%/cortex_a.c \
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2017-02-20 13:29:01 +00:00
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%D%/ls1_sap.c \
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%D%/mem_ap.c
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2009-11-10 12:27:02 +00:00
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2015-01-16 01:22:20 +00:00
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ARMV8_SRC = \
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2016-09-03 21:20:58 +00:00
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%D%/armv8_dpm.c \
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2016-09-15 07:13:51 +00:00
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%D%/armv8_opcodes.c \
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2015-01-16 01:22:20 +00:00
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%D%/aarch64.c \
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2019-03-30 11:27:57 +00:00
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%D%/a64_disassembler.c \
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2016-09-20 09:16:30 +00:00
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%D%/armv8.c \
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%D%/armv8_cache.c
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2015-01-16 01:22:20 +00:00
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2009-11-10 12:27:02 +00:00
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ARM_DEBUG_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/arm_dpm.c \
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%D%/arm_jtag.c \
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%D%/arm_disassembler.c \
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%D%/arm_simulator.c \
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%D%/arm_semihosting.c \
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%D%/arm_adi_v5.c \
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2018-03-23 20:17:29 +00:00
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%D%/arm_dap.c \
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2016-11-06 19:19:26 +00:00
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%D%/armv7a_cache.c \
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%D%/armv7a_cache_l2x.c \
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2019-01-23 09:52:28 +00:00
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%D%/adi_v5_dapdirect.c \
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2016-11-06 19:19:26 +00:00
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%D%/adi_v5_jtag.c \
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%D%/adi_v5_swd.c \
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%D%/embeddedice.c \
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%D%/trace.c \
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%D%/etb.c \
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%D%/etm.c \
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2016-11-19 09:02:34 +00:00
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%D%/etm_dummy.c \
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2020-10-11 22:11:46 +00:00
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%D%/arm_tpiu_swo.c \
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2016-11-19 09:02:34 +00:00
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%D%/arm_cti.c
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2009-11-10 12:27:02 +00:00
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2010-08-15 19:51:34 +00:00
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AVR32_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/avr32_ap7k.c \
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%D%/avr32_jtag.c \
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%D%/avr32_mem.c \
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%D%/avr32_regs.c
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2010-08-15 19:51:34 +00:00
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2009-11-10 12:27:02 +00:00
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MIPS32_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/mips32.c \
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%D%/mips_m4k.c \
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%D%/mips32_pracc.c \
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%D%/mips32_dmaacc.c \
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%D%/mips_ejtag.c
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2009-11-10 12:27:02 +00:00
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2014-09-23 08:46:02 +00:00
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MIPS64_SRC = \
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%D%/mips64.c \
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%D%/mips32_pracc.c \
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%D%/mips64_pracc.c \
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2014-09-23 08:51:05 +00:00
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%D%/mips_mips64.c \
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2014-09-23 08:46:02 +00:00
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%D%/trace.c \
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%D%/mips_ejtag.c
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2013-02-05 01:34:18 +00:00
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NDS32_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/nds32.c \
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%D%/nds32_reg.c \
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%D%/nds32_cmd.c \
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%D%/nds32_disassembler.c \
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%D%/nds32_tlb.c \
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%D%/nds32_v2.c \
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%D%/nds32_v3_common.c \
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%D%/nds32_v3.c \
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%D%/nds32_v3m.c \
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%D%/nds32_aice.c
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2013-02-05 01:34:18 +00:00
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2017-11-06 18:56:28 +00:00
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STM8_SRC = \
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%D%/stm8.c
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2014-02-06 17:11:15 +00:00
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INTEL_IA32_SRC = \
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2016-11-06 19:19:26 +00:00
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%D%/quark_x10xx.c \
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%D%/quark_d20xx.c \
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%D%/lakemont.c \
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%D%/x86_32_common.c
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2018-08-29 00:18:01 +00:00
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ESIRISC_SRC = \
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%D%/esirisc.c \
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2018-10-25 02:29:03 +00:00
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%D%/esirisc_jtag.c \
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%D%/esirisc_trace.c
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2018-08-29 00:18:01 +00:00
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|
Introduce ARCv2 architecture related code
This patch is an initial bump of ARC-specific code
which implements the ARCv2 target(EMSK board) initializing
routine and some basic remote connection/load/continue
functionality.
Changes:
03.12.2019:
-Add return value checks.
-Using static code analizer next fixes were made:
Mem leak in functions:
arc_jtag_read_memory,arc_jtag_read_memory,
arc_jtag_write_registers, arc_jtag_read_registers,
jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct,
arc_build_reg_cache, arc_mem_read.
Dead code in "arc_mem_read";
In arc_save_context, arc_restore_context correct arguments
in"memset" calls.
In "build_bcr_reg_cache", "arc_build_reg_cache" check
if list is not empty.
29.12.2019
-Moved code from arc_v2.c to arc.c
-Added checks of the result of calloc/malloc calls
-Reworked arc_cmd.c: replaced spagetty code with functions
-Moved to one style in if statements - to "if(!bla)"
-Changed Licence headers
22.01.2020
-Removed unused variables in arc_common
-Renamed register operation functions
-Introduced arc_deinit_target function
-Fixed interrupt handling in halt/resume:
* add irq_state field in arc_common
* fix irq enable/disable calls ( now STATUS32 register is used)
-Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32()
-Made some cleanup
30.01.2020
-Removed redundant arc_register struct, moved target link to arc_reg_desc
-Introduced link to BCR reg cache in arc_common for freeing memory.
-Now arc_deinit_target frees all arc-related allocated memory.
Valgrind shows no memory leaks.
-Inroduced arch description in arc.c
01.02.2020
-Remove small memory allocations in arc_init_reg. Instead created reg_value
and feature fields in arc_reg_desc.
-Add return value for arc_init_reg() func.
-Replaced some integer constants(61,62,63) with defines.
-Removed redundant conversions in arc_reg_get_field().
-Moved iccm/dccm configuration code from arc_configure()
to separate functions.
19.02.2020
-Change sizeof(struct) to sizeof(*ptr) in allocations
-Changed if/while(ptr != NULL) to if/while(ptr)
-Removed unused variables from struct arc_jtag
-Add additional structs to arc_reg_data_type
to reduce amount of memory allocations calls
and simplifying memory freeing.
-Add helper arc_reg_bitfield_t struct which includes
reg_data_type_bitfield object and char[] name. Reduces
memory allocations calls.
-Add limit for reg_type/reg_type_field names(20 symbols).
-Add in jim_arc_add_reg_type*() functions additional
argnument checks(amount of field/name size).
-In jim_arc_add_reg_type*() reduced amount of memory allocations.
-Cleanup of jim_arc_add_reg_type*() functions.
-For commands update ".usage" fields according docopt.
-Cleanup in arc_jtag.c
-Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*()
-Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs
during regiter r/w.
24.02:
-Change include guards in arc* files according coding style
-Remove _t suffix in struct arc_reg_bitfield_t
-Some cleanup
Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5332
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-01-27 12:22:27 +00:00
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ARC_SRC = \
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%D%/arc.c \
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%D%/arc_cmd.c \
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%D%/arc_jtag.c \
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%D%/arc_mem.c
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2016-11-06 19:19:26 +00:00
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%C%_libtarget_la_SOURCES += \
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%D%/algorithm.h \
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%D%/arm.h \
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2021-08-08 14:46:30 +00:00
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%D%/arm_coresight.h \
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2016-11-06 19:19:26 +00:00
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%D%/arm_dpm.h \
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%D%/arm_jtag.h \
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%D%/arm_adi_v5.h \
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%D%/armv7a_cache.h \
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%D%/armv7a_cache_l2x.h \
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2016-07-14 19:00:59 +00:00
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%D%/armv7a_mmu.h \
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2016-11-06 19:19:26 +00:00
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%D%/arm_disassembler.h \
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2019-03-30 11:27:57 +00:00
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%D%/a64_disassembler.h \
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2016-11-06 19:19:26 +00:00
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%D%/arm_opcodes.h \
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%D%/arm_simulator.h \
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%D%/arm_semihosting.h \
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%D%/arm7_9_common.h \
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%D%/arm7tdmi.h \
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%D%/arm720t.h \
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%D%/arm9tdmi.h \
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%D%/arm920t.h \
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%D%/arm926ejs.h \
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%D%/arm966e.h \
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%D%/arm946e.h \
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%D%/arm11.h \
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%D%/arm11_dbgtap.h \
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%D%/armv4_5.h \
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%D%/armv4_5_mmu.h \
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%D%/armv4_5_cache.h \
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%D%/armv7a.h \
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%D%/armv7m.h \
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%D%/armv7m_trace.h \
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2015-01-16 01:22:20 +00:00
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%D%/armv8.h \
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2016-09-03 21:20:58 +00:00
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%D%/armv8_dpm.h \
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2016-09-02 08:38:08 +00:00
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%D%/armv8_opcodes.h \
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2016-09-20 09:16:30 +00:00
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%D%/armv8_cache.h \
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2016-11-06 19:19:26 +00:00
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%D%/avrt.h \
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%D%/dsp563xx.h \
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%D%/dsp563xx_once.h \
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%D%/dsp5680xx.h \
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%D%/breakpoints.h \
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%D%/cortex_m.h \
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%D%/cortex_a.h \
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2015-01-16 01:22:20 +00:00
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%D%/aarch64.h \
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2016-11-06 19:19:26 +00:00
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%D%/embeddedice.h \
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%D%/etb.h \
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%D%/etm.h \
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%D%/etm_dummy.h \
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2020-10-11 22:11:46 +00:00
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%D%/arm_tpiu_swo.h \
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2016-11-06 19:19:26 +00:00
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%D%/image.h \
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%D%/mips32.h \
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2014-09-23 08:46:02 +00:00
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%D%/mips64.h \
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2016-11-06 19:19:26 +00:00
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%D%/mips_m4k.h \
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2014-09-23 08:51:05 +00:00
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%D%/mips_mips64.h \
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2016-11-06 19:19:26 +00:00
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%D%/mips_ejtag.h \
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%D%/mips32_pracc.h \
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%D%/mips32_dmaacc.h \
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2014-09-23 08:46:02 +00:00
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%D%/mips64_pracc.h \
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2016-11-06 19:19:26 +00:00
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%D%/register.h \
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%D%/target.h \
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%D%/target_type.h \
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%D%/trace.h \
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%D%/target_request.h \
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%D%/trace.h \
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%D%/xscale.h \
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%D%/smp.h \
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%D%/avr32_ap7k.h \
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%D%/avr32_jtag.h \
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%D%/avr32_mem.h \
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%D%/avr32_regs.h \
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%D%/nds32.h \
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%D%/nds32_cmd.h \
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%D%/nds32_disassembler.h \
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%D%/nds32_edm.h \
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%D%/nds32_insn.h \
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%D%/nds32_reg.h \
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%D%/nds32_tlb.h \
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%D%/nds32_v2.h \
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%D%/nds32_v3_common.h \
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%D%/nds32_v3.h \
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%D%/nds32_v3m.h \
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%D%/nds32_aice.h \
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2018-05-13 15:39:06 +00:00
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%D%/semihosting_common.h \
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2017-11-06 18:56:28 +00:00
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%D%/stm8.h \
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2016-11-06 19:19:26 +00:00
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%D%/lakemont.h \
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2016-11-19 09:02:34 +00:00
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%D%/x86_32_common.h \
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2018-08-29 00:18:01 +00:00
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%D%/arm_cti.h \
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%D%/esirisc.h \
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%D%/esirisc_jtag.h \
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2018-10-25 02:29:03 +00:00
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%D%/esirisc_regs.h \
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Introduce ARCv2 architecture related code
This patch is an initial bump of ARC-specific code
which implements the ARCv2 target(EMSK board) initializing
routine and some basic remote connection/load/continue
functionality.
Changes:
03.12.2019:
-Add return value checks.
-Using static code analizer next fixes were made:
Mem leak in functions:
arc_jtag_read_memory,arc_jtag_read_memory,
arc_jtag_write_registers, arc_jtag_read_registers,
jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct,
arc_build_reg_cache, arc_mem_read.
Dead code in "arc_mem_read";
In arc_save_context, arc_restore_context correct arguments
in"memset" calls.
In "build_bcr_reg_cache", "arc_build_reg_cache" check
if list is not empty.
29.12.2019
-Moved code from arc_v2.c to arc.c
-Added checks of the result of calloc/malloc calls
-Reworked arc_cmd.c: replaced spagetty code with functions
-Moved to one style in if statements - to "if(!bla)"
-Changed Licence headers
22.01.2020
-Removed unused variables in arc_common
-Renamed register operation functions
-Introduced arc_deinit_target function
-Fixed interrupt handling in halt/resume:
* add irq_state field in arc_common
* fix irq enable/disable calls ( now STATUS32 register is used)
-Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32()
-Made some cleanup
30.01.2020
-Removed redundant arc_register struct, moved target link to arc_reg_desc
-Introduced link to BCR reg cache in arc_common for freeing memory.
-Now arc_deinit_target frees all arc-related allocated memory.
Valgrind shows no memory leaks.
-Inroduced arch description in arc.c
01.02.2020
-Remove small memory allocations in arc_init_reg. Instead created reg_value
and feature fields in arc_reg_desc.
-Add return value for arc_init_reg() func.
-Replaced some integer constants(61,62,63) with defines.
-Removed redundant conversions in arc_reg_get_field().
-Moved iccm/dccm configuration code from arc_configure()
to separate functions.
19.02.2020
-Change sizeof(struct) to sizeof(*ptr) in allocations
-Changed if/while(ptr != NULL) to if/while(ptr)
-Removed unused variables from struct arc_jtag
-Add additional structs to arc_reg_data_type
to reduce amount of memory allocations calls
and simplifying memory freeing.
-Add helper arc_reg_bitfield_t struct which includes
reg_data_type_bitfield object and char[] name. Reduces
memory allocations calls.
-Add limit for reg_type/reg_type_field names(20 symbols).
-Add in jim_arc_add_reg_type*() functions additional
argnument checks(amount of field/name size).
-In jim_arc_add_reg_type*() reduced amount of memory allocations.
-Cleanup of jim_arc_add_reg_type*() functions.
-For commands update ".usage" fields according docopt.
-Cleanup in arc_jtag.c
-Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*()
-Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs
during regiter r/w.
24.02:
-Change include guards in arc* files according coding style
-Remove _t suffix in struct arc_reg_bitfield_t
-Some cleanup
Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5332
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-01-27 12:22:27 +00:00
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%D%/esirisc_trace.h \
|
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%D%/arc.h \
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%D%/arc_cmd.h \
|
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%D%/arc_jtag.h \
|
2020-09-17 13:23:31 +00:00
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%D%/arc_mem.h \
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%D%/rtt.h
|
2016-11-06 19:19:26 +00:00
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include %D%/openrisc/Makefile.am
|
2018-07-18 20:34:23 +00:00
|
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include %D%/riscv/Makefile.am
|
2022-04-21 05:53:54 +00:00
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include %D%/xtensa/Makefile.am
|
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include %D%/espressif/Makefile.am
|