Add the SPDX tag to makefiles, configuration scripts and tcl files
present in the folders under src/
Change-Id: I1e4552aafe46ef4893d510da9d732c5f181784a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7051
Tested-by: jenkins
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Several magic numbers related to ARM CoreSight specification
IHI0029E are spread around OpenOCD code.
Define through macros the ARM CoreSight magic numbers and collect
them in a single include file.
Use the new macros wherever possible.
Change-Id: I9b0c1c651ce4ffbaf08d31791ef16e95983ee4cb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6446
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
The code for oocd_trace has been marked as deprecated in release
v0.10.0, 4 years ago.
Time to drop it!
Change-Id: I989f8345dee4ff2369bcf5e2e2ace86bbd5aa6a5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6088
Tested-by: jenkins
This is supposed to replace big part of armv7m_trace.[ch], since
TPIU is not only the one implemented in Cortex-M3 and M4.
Change-Id: I7588d16cbefe9cdb371c52fb0aa5cdfb48518804
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5858
Tested-by: jenkins
Real Time Transfer (RTT) is an interface specified by SEGGER based on
basic memory reads and writes to transfer data bidirectionally between
target and host.
Every target that supports so called "background memory access", which
means that the target memory can be accessed by the debugger while the
target is running, can be used.
RTT is especially of interest for targets which do not support Serial
Wire Output (SWO) (e.g. ARM Cortex-M0) or where using semihosting is
not possible (e.g. real-time applications) [1].
The data transfer is organized in channels where each channel consists
of an up- and/or down-channel. See [2] for more details.
Channels are exposed via TCP connections. One or more RTT server can be
assigned to each channel to make them accessible to an unlimited number
of TCP connections.
The current implementation does not respect buffer flags which are used
to determine what happens when writing to a full buffer.
Note that the implementation is designed in a way that the RTT
operations can be directly performed by an adapter (e.g. J-Link).
[1] https://devzone.nordicsemi.com/tutorials/6/
[2] https://www.segger.com/jlink-rtt.html
Change-Id: I8bc8a1b381fb74e08b8752d5cf53804cc573c1e0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/4055
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
BUILD_TARGET64 creates a larger test matrix and mostly gates the
building of the aarch64/armv8 target, make that unconditional, which
would help fixing any issues with 64-bit address types anyway.
Rebased by Antonio Borneo after commit 1fbe8450a9 ("mips: Add
MIPS64 support")
Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5240
Tested-by: jenkins
This patch is an initial bump of ARC-specific code
which implements the ARCv2 target(EMSK board) initializing
routine and some basic remote connection/load/continue
functionality.
Changes:
03.12.2019:
-Add return value checks.
-Using static code analizer next fixes were made:
Mem leak in functions:
arc_jtag_read_memory,arc_jtag_read_memory,
arc_jtag_write_registers, arc_jtag_read_registers,
jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct,
arc_build_reg_cache, arc_mem_read.
Dead code in "arc_mem_read";
In arc_save_context, arc_restore_context correct arguments
in"memset" calls.
In "build_bcr_reg_cache", "arc_build_reg_cache" check
if list is not empty.
29.12.2019
-Moved code from arc_v2.c to arc.c
-Added checks of the result of calloc/malloc calls
-Reworked arc_cmd.c: replaced spagetty code with functions
-Moved to one style in if statements - to "if(!bla)"
-Changed Licence headers
22.01.2020
-Removed unused variables in arc_common
-Renamed register operation functions
-Introduced arc_deinit_target function
-Fixed interrupt handling in halt/resume:
* add irq_state field in arc_common
* fix irq enable/disable calls ( now STATUS32 register is used)
-Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32()
-Made some cleanup
30.01.2020
-Removed redundant arc_register struct, moved target link to arc_reg_desc
-Introduced link to BCR reg cache in arc_common for freeing memory.
-Now arc_deinit_target frees all arc-related allocated memory.
Valgrind shows no memory leaks.
-Inroduced arch description in arc.c
01.02.2020
-Remove small memory allocations in arc_init_reg. Instead created reg_value
and feature fields in arc_reg_desc.
-Add return value for arc_init_reg() func.
-Replaced some integer constants(61,62,63) with defines.
-Removed redundant conversions in arc_reg_get_field().
-Moved iccm/dccm configuration code from arc_configure()
to separate functions.
19.02.2020
-Change sizeof(struct) to sizeof(*ptr) in allocations
-Changed if/while(ptr != NULL) to if/while(ptr)
-Removed unused variables from struct arc_jtag
-Add additional structs to arc_reg_data_type
to reduce amount of memory allocations calls
and simplifying memory freeing.
-Add helper arc_reg_bitfield_t struct which includes
reg_data_type_bitfield object and char[] name. Reduces
memory allocations calls.
-Add limit for reg_type/reg_type_field names(20 symbols).
-Add in jim_arc_add_reg_type*() functions additional
argnument checks(amount of field/name size).
-In jim_arc_add_reg_type*() reduced amount of memory allocations.
-Cleanup of jim_arc_add_reg_type*() functions.
-For commands update ".usage" fields according docopt.
-Cleanup in arc_jtag.c
-Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*()
-Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs
during regiter r/w.
24.02:
-Change include guards in arc* files according coding style
-Remove _t suffix in struct arc_reg_bitfield_t
-Some cleanup
Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5332
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Some high level adapters, like STLINK-V3 and new firmware for
ST-Link/V2, provide API to directly access the DAP registers
hiding the details of the physical transport JTAG or SWD.
OpenOCD has already the intermediate API in struct dap_ops that
are suitable for such adapters, but are not exposed to the
adapter drivers.
Add in struct adapter_driver two independent struct dap_ops for
the cases of physical JTAG and SWD transport.
Add new transport names "dapdirect_jtag" and "dapdirect_swd", to
be used by the drivers that provide one or both DAP API.
Add the necessarily glue in target/adi_v5_dapdirect.c
Change-Id: I2bb8e3a80fba750f2c218d877cfa5888428e3c28
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4903
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This patch adds support for instruction tracing to eSi-RISC targets. The
command interface is borrowed heavily from ETM; eSi-Trace uses a less
sophisticated model for tracing, however the setup and usage is similar.
This patch also cleans up the command interfaces of the other esirisc
command groups and adds additional debugging information to log messages
when dealing with CSRs.
This patch "finalizes" support for 32-bit eSi-RISC targets.
Change-Id: Ia2a9de79a3c7c066240b5212721fb1b7584a9a45
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4780
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.
Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This pseudo target allows attaching to any access point on the DAP at the
MEM-AP level and read and write addresses on the connected bus. For
example, one can create a mem_ap target on the APB-AP and read and write
registers of debug components directly. This allows many diagnostic
and other features be programmed entirely using TCL, without necessity
of adding drivers to OpenOCD.
Change-Id: I53229ffd68fb0f96fb68be15b0f3a76cc8843c8e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4002
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Leonard Crestez <cdleonard@gmail.com>
This supports both 0.11 and 0.13 versions of the debug spec.
Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.
Flash support for the SiFive boards will also come in a later commit.
Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
In 2016, ARM released the second edition of the semihosting specs
("Semihosting for AArch32 and AArch64"), adding support for 64-bits.
To ease the reuse of the semihosting logic for other platforms
(like RISC-V), the semihosting code was isolated from the ARM
target and updated to the latest specs.
The new code is already in use since January (in GNU MCU Eclipse
OpenOCD) and no problems were reported, neither for ARM nor for
RISC-V targets, after more than 7K downloads.
The 2 new files were formatted with uncrustify.
Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96
Signed-off-by: Liviu Ionescu <ilg@livius.net>
Reviewed-on: http://openocd.zylin.com/4518
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
longer references the dap, daps are now independently
created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
power cycle)
- update documentation
- update target files
Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4468
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
New STM8 target based mostly on mips4k. Target communication
through STLINK/SWIM. No flash driver yet but it is still possible
to program flash through load_image command. The usual target debug
methods are implemented.
Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3953
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Not specific to ARMv8, the Cross Trigger Interface
deserves an independent access wrapper.
Change-Id: I84f8faad15ed3515e0fff7f6cc5d1109ef91a869
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3986
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add database for common, equivalent opcodes for Aarch32 and
Aarch64 execution states
Revisit all functions that access Aarch64 specific registers
or use Aarch64 opcodes and rewrite them to act depending on
current state of the core.
Add core register access functions for Aarch32 state
Add function to determine the core execution state without
reading DSPSR.
Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
For now only D-Cache flush (Clean&Invalidate) and I-Cache
invalidate are implemented. That's enough for software breakpoints.
Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Add or move ARMv8 related dpm function to their own source module
Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Avoid special rules to generate array at compile time by shipping
the generated file. Convert to Makefile build like the other
loaders.
Change-Id: I5a05edddcfaff3d395086cd3aa33120f8a7aa9dc
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3864
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The SAP in LS102x SoC's from Freescale is able to read and write to all
physical memory locations, independently of CPU cores and DAP.
This implementation is 100% based on reverse-engineering of JTAG
communication with an LS1021A SAP using a JTAG debugger with SAP support.
And as such, this code is for now "works-for-me", pending verification
by other OpenOCD users, or even better, actual information from Freescale
on the SAP interface.
Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3096
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add support for the Intel Quark mcu D2000 using the new quark_d2xx
target.
Changes to the lakemont part are needed for the D2000 core and
backwards compatible with the X1000 one.
Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3199
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch introduces, new command set and handlers for l1 and l2x caches.
Patch set 10 folded the following changes into this one:
Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415
If8d87a03281d0f4ad402909998e7834eb4837e79
I0749f129fa74e04f4e9c20d143a744f09ef750d8
Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/2800
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Valgrind-tested.
Comparison of flashing performance on an FRDM-KL25Z board running mbed
CMSIS-DAP variant, 5MHz clock, old driver:
wrote 28096 bytes from file demo.elf in 26.833590s (1.023 KiB/s)
verified 27264 bytes in 1.754972s (15.171 KiB/s)
this implementation:
wrote 28096 bytes from file demo.elf in 3.691939s (7.432 KiB/s)
verified 27264 bytes in 0.598987s (44.450 KiB/s)
Also tested "Keil ULINK-ME CMSIS-DAP" with an STM32F100 target, 5MHz
clock, results reading from flash, old driver:
dumped 131072 bytes in 98.445305s (1.300 KiB/s)
this implementation:
dumped 131072 bytes in 8.242686s (15.529 KiB/s)
Change-Id: Ic64d3124b1d6cd9dd1016445bb627c71e189ae95
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2356
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This provides support for various trace-related subsystems in a
generic and expandable way.
Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins
Don't hardcode the type for the array, just output the array initializer
so the includer can choose the type and storage class, zero-terminate at
will and so on.
Change-Id: I6d5e0710eaaba0a218b3eb32f6569177356f4462
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2176
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Using custom build-time tools is always more problematic, especially
for cross-compiling.
This alternative implementation assumes "od" (IEEE Std 1003.1-2001)
and sed are available which should be the case for any reasonably
modern system.
Change-Id: I0208f475648c78e7dca127ff4bab60d314b2bf53
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2139
Tested-by: jenkins
Reviewed-by: Fatih Aşıcı <fatih.asici@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
GPL requires providing sources for any derived work. I do not see any
reason to not include the xscale stuff into release tarballs.
Wildcard matching is used because plain directory name matches
implicit rule for executables and xscale.c built is errorneously
attempted, and directory name with a slash duplicates a directory
(xscale/xscale) in dist.
Change-Id: Ie0266470dcb97be87a09ba2dda9b3957f7cbc2fa
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1911
Tested-by: jenkins
Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Intel Quark X10xx SoC debug support added
Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC
Generic x86 32-bit code is in x86_32_common.c/h
Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368
Signed-off-by: adrian.burns@intel.com
Reviewed-on: http://openocd.zylin.com/1829
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is based on work from:
https://github.com/TheShed/OpenOCD-CMSIS-DAP/tree/cmsis-dap
Main changes include moving over to using HIDAPI rather than libusb-1.0
and cleaning up to merge into master. Support for reset using srst has
also been added.
It has been tested on all the mbed boards as well as the Freedom board
from Freescale. These boards only implement SWD mode, however JTAG mode
has been tested with a Keil ULINK2 and a stm32 target - but requires a lot
more work.
Change-Id: I96d5ee1993bc9c0526219ab754c5aad3b55d812d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1542
Tested-by: jenkins
Add support for OpenRISC target. This implementation
supports the adv_debug_sys debug unit core. The mohor
dbg_if is not supported. Support for mohor TAP core
and Altera Virtual JTAG core are also provided.
Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1547
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add target code for Andes targets.
Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Andes AICE uses USB to transfer packets between OpenOCD and AICE.
It uses high-level USB commands to control targets instead of using
JTAG signals. I define an interface as aice_port_api_s. It contains
all basic operations needed by target-dependent code.
Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1256
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This enables us to change the target name without breaking any
target scripts.
Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/919
Tested-by: jenkins
even the AT91EB40a's flash is covered by CFI and nobody ever submitted
any other drivers based on eCos code. It's just possible that this
idea was missing documentation and "marketing", but it's in git if
somebody wants to resurrect it.
Change-Id: I66449aa6e0997301f9d67f28098789bfc891d6e9
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/502
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
automake 1.11.2 throws `pkglibdir' is not a legitimate directory for `DATA'
if nobase_dist_pkglib_DATA is used.
We work around this issue by defining our own location.
Change-Id: I3c29e2df0b67e745283c50d358e31699bd60dc74
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/457
Tested-by: jenkins
This rename is in preparation for cortex_m4 support.
Change-Id: Ic08c298ec6ed2aabc2c39db67191f68b3a51f550
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/147
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Use "git revert <commit>" to revert this commit, then build and
repair and post patch to the mailing list.
Warnings generated with:
nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222)
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data':
openocd/src/target/dsp5680xx.c:252: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data':
openocd/src/target/dsp5680xx.c:268: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store':
openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned
pointer will break strict-aliasing rules
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read':
openocd/src/target/dsp5680xx.c:736: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:737: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8':
openocd/src/target/dsp5680xx.c:823: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write':
openocd/src/target/dsp5680xx.c:938: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:941: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr':
openocd/src/target/dsp5680xx.c:1355: warning: cast increases required
alignment of target type
Antonio Borneo
Erhan Kurubas
Marc Schink
Mete Balci
Florian Fainelli
Evgeniy Didin
Peter Mamonov
Steven Stallion
Matthias Welwarsky
Tim Newsome
Liviu Ionescu
Ake Rehnman
David Ung
Andreas Fritiofson
Esben Haabendal
Ivan De Cesaris
Oleksij Rempel
Paul Fertser
Adrian Burns
Spencer Oliver
Franck Jullien
Hsiangkai Wang
Øyvind Harboe
Mathias K
Jie Zhang