stm32f1x: fix bug in flash loader and restrict instruction set to armv6-m
Correct the offset to the read pointer when clearing it on error. Also restrict the instruction set to armv6-m so the flash driver can be used on Cortex-M0 parts with the same flash controller. Change-Id: I380f9dabcc41fb6e4d43a7e02f355e2381913f39 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/399 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Andreas Fritiofson
Spencer Oliver
parent
61f3d4b7e4
commit
81b4ef6ee5
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@ -20,7 +20,7 @@
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.text
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.text
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.syntax unified
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.syntax unified
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.cpu cortex-m3
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.cpu cortex-m0
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.thumb
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.thumb
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.thumb_func
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.thumb_func
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.global write
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.global write
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@ -34,6 +34,7 @@
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* Clobbered:
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* Clobbered:
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* r5 - rp
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* r5 - rp
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* r6 - wp, tmp
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* r6 - wp, tmp
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* r7 - tmp
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*/
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*/
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */
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@ -48,24 +49,31 @@ wait_fifo:
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beq wait_fifo
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beq wait_fifo
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movs r6, #1 /* set PG flag to enable flash programming */
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movs r6, #1 /* set PG flag to enable flash programming */
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str r6, [r0, #STM32_FLASH_CR_OFFSET]
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str r6, [r0, #STM32_FLASH_CR_OFFSET]
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ldrh r6, [r5], #2 /* "*target_address++ = *rp++" */
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ldrh r6, [r5] /* "*target_address++ = *rp++" */
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strh r6, [r4], #2
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strh r6, [r4]
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adds r5, #2
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adds r4, #2
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busy:
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busy:
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ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
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ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
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tst r6, #1
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movs r7, #1
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tst r6, r7
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bne busy
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bne busy
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tst r6, #0x14 /* check the error bits */
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movs r7, #0x14 /* check the error bits */
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tst r6, r7
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bne error
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bne error
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cmp r5, r3 /* wrap rp at end of buffer */
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cmp r5, r3 /* wrap rp at end of buffer */
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it cs
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bcc no_wrap
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addcs r5, r2, #8
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mov r5, r2
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adds r5, #8
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no_wrap:
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str r5, [r2, #4] /* store rp */
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str r5, [r2, #4] /* store rp */
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subs r1, r1, #1 /* decrement halfword count */
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subs r1, r1, #1 /* decrement halfword count */
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cbz r1, exit /* loop if not done */
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cmp r1, #0
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b wait_fifo
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beq exit /* loop if not done */
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b wait_fifo
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error:
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error:
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movs r0, #0
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movs r0, #0
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str r0, [r2, #2] /* set rp = 0 on error */
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str r0, [r2, #4] /* set rp = 0 on error */
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exit:
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exit:
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mov r0, r6 /* return status in r0 */
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mov r0, r6 /* return status in r0 */
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bkpt #0
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bkpt #0
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@ -635,35 +635,42 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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/* #define STM32_FLASH_CR_OFFSET 0x10 */
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/* #define STM32_FLASH_CR_OFFSET 0x10 */
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/* #define STM32_FLASH_SR_OFFSET 0x0C */
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/* #define STM32_FLASH_SR_OFFSET 0x0C */
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/* wait_fifo: */
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/* wait_fifo: */
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0x16, 0x68, /* ldr r6, [r2, #0] */
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0x16, 0x68, /* ldr r6, [r2, #0] */
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0x00, 0x2e, /* cmp r6, #0 */
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0x00, 0x2e, /* cmp r6, #0 */
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0x1a, 0xd0, /* beq exit */
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0x1a, 0xd0, /* beq exit */
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0x55, 0x68, /* ldr r5, [r2, #4] */
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0x55, 0x68, /* ldr r5, [r2, #4] */
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0xb5, 0x42, /* cmp r5, r6 */
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0xb5, 0x42, /* cmp r5, r6 */
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0xf9, 0xd0, /* beq wait_fifo */
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0xf9, 0xd0, /* beq wait_fifo */
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0x01, 0x26, /* movs r6, #1 */
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0x01, 0x26, /* movs r6, #1 */
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0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
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0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
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0x35, 0xf8, 0x02, 0x6b, /* ldrh r6, [r5], #2 */
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0x2e, 0x88, /* ldrh r6, [r5, #0] */
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0x24, 0xf8, 0x02, 0x6b, /* strh r6, [r4], #2 */
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0x26, 0x80, /* strh r6, [r4, #0] */
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0x02, 0x35, /* adds r5, #2 */
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0x02, 0x34, /* adds r4, #2 */
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/* busy: */
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/* busy: */
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0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
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0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
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0x16, 0xf0, 0x01, 0x0f, /* tst r6, #1 */
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0x01, 0x27, /* movs r7, #1 */
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0xfb, 0xd1, /* bne busy */
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0x3e, 0x42, /* tst r6, r7 */
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0x16, 0xf0, 0x14, 0x0f, /* tst r6, #0x14 */
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0xfb, 0xd1, /* bne busy */
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0x07, 0xd1, /* bne error */
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0x14, 0x27, /* movs r7, #0x14 */
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0x9d, 0x42, /* cmp r5, r3 */
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0x3e, 0x42, /* tst r6, r7 */
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0x28, 0xbf, /* it cs */
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0x08, 0xd1, /* bne error */
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0x02, 0xf1, 0x08, 0x05, /* addcs r5, r2, #8 */
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0x9d, 0x42, /* cmp r5, r3 */
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0x55, 0x60, /* str r5, [r2, #4] */
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0x01, 0xd3, /* bcc no_wrap */
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0x01, 0x39, /* subs r1, r1, #1 */
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0x15, 0x46, /* mov r5, r2 */
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0x19, 0xb1, /* cbz r1, exit */
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0x08, 0x35, /* adds r5, #8 */
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0xe4, 0xe7, /* b wait_fifo */
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/* no_wrap: */
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0x55, 0x60, /* str r5, [r2, #4] */
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0x01, 0x39, /* subs r1, r1, #1 */
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0x00, 0x29, /* cmp r1, #0 */
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0x02, 0xd0, /* beq exit */
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0xe3, 0xe7, /* b wait_fifo */
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/* error: */
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/* error: */
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0x00, 0x20, /* movs r0, #0 */
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0x00, 0x20, /* movs r0, #0 */
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0xc2, 0xf8, 0x02, 0x00, /* str r0, [r2, #2] */
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0x50, 0x60, /* str r0, [r2, #4] */
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/* exit: */
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/* exit: */
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0x30, 0x46, /* mov r0, r6 */
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0x30, 0x46, /* mov r0, r6 */
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0x00, 0xbe, /* bkpt #0 */
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0x00, 0xbe, /* bkpt #0 */
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};
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};
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/* flash write code */
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/* flash write code */
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