It was observed on AM437x that after every reset the target's debug
regions are unpowered. To be able to properly communicate with the
target and perform cortex_a init debug access after a reset event the
examination need to be performed every time, not just on OpenOCD
start.
Change-Id: Idf272e127ee88341e806ee00df154eade573451d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2723
Tested-by: jenkins
Reviewed-by: Felipe Balbi <balbi@ti.com>
After intermittent connection failures or target power failures it
might be necessary to try reexamination even when polling fails. This
should make communication with Cortex-A targets more reliable.
This was runtime tested with stlink attached to an stm32l1 and an FTDI JTAG
adapter attached to an stm32f1 target.
Change-Id: I38c4db8124b7f4bbf53ddda53c13273449f49c15
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2721
Tested-by: jenkins
Reviewed-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Some targets need arbitrary amount of time (usually not too long)
after reset (both sysresetreq and srst) to do initialisation, and
SWD/JTAG is not available during that. According to PSoC4 docs, the
debugger should try connecting until it succeeds.
Also ahbap_debugport_init might be necessary to perform after using
hardware srst too, so add it there (except for the targets that
support srst_nogate since they are very unlikely to need it).
Change-Id: I3598d5ff7b8e0bf3a5566a57dec4b0b2b243d297
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2601
Tested-by: jenkins
In some cases (the most obvious are TI's SoCs) ROM table lacks entries
for the cores, so OpenOCD has no way to determine what debug base to
use. Due to an error fixed in ec9ccaa288 it wasn't handled properly,
and OpenOCD would continue to try using dbgbase = 0, which happened to
work for e.g. AM437x.
This patch adds a clear indication to the user that to access such a
target, dbgbase must be set manually in the config.
Reported by Felipe Balbi on IRC.
Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2603
Tested-by: jenkins
Calling ahbap_debugport_init() is wrong here because the actions
performed by it might lead to jtagdp_transaction_endcheck errors thus
leading to infinite recursion.
The removed code is not needed now because target polling should lead
to reexamination automatically, and both cortex_a and cortex_m call
ahbap_debugport_init() as part of their target examine handler.
This was reported as a real life issue on IRC by Weaselweb with
Cortex-A target. Quitte reports similar results in some circumstances
(adapter_khz too high) with LPC17xx.
Change-Id: I7148022f76a1272b5262d251f2e807ffb1543547
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2697
Tested-by: jenkins
When the SCTLR has C set but M unset (i.e. Caching on, but MMU off) the cache
if effectively off. So only flush the cache if MMU is on, otherwise stale
entries might be committed to memory.
Change-Id: Iaff8b6f25b7a41ba838b91d45684c98f99fc0b27
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/2429
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Vladimir Svoboda <ze.vlad@gmail.com>
Bug in read pointer check within flash write algorithm made incorrect check
if block size is more than 4 bytes (bug was detected with 16 bytes block size).
Change-Id: I5b8e7ebca619a0a85ae6e9e496ff792248134d81
Signed-off-by: DmitryShpak <disona@yandex.ru>
Reviewed-on: http://openocd.zylin.com/2657
Tested-by: jenkins
Reviewed-by: Jens Bauer <jens@gpio.dk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This brings SWD reconnection procedure in line with the ARM
documentation and changes cortex_m reset procedure to make use of it.
The motivation behind this patch is to make SAM4L "reset" and "reset
halt" properly without SRST. The complication here is that EDBG issues
an additional read of DP_RDBUFF automatically right after writing
SYSRESETREQ, that leads to a FAULT which needs to be dealt with
properly. With this patch the very first ahbap_debugport_init DAP
access will make SWD layer properly reinitialise the link before
continuing.
Runtime tested with mbed CMIS-DAP + KL25 only.
Change-Id: Ic506f9db30931dfa60860036b83f73b897975909
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2596
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Valgrind-tested.
Comparison of flashing performance on an FRDM-KL25Z board running mbed
CMSIS-DAP variant, 5MHz clock, old driver:
wrote 28096 bytes from file demo.elf in 26.833590s (1.023 KiB/s)
verified 27264 bytes in 1.754972s (15.171 KiB/s)
this implementation:
wrote 28096 bytes from file demo.elf in 3.691939s (7.432 KiB/s)
verified 27264 bytes in 0.598987s (44.450 KiB/s)
Also tested "Keil ULINK-ME CMSIS-DAP" with an STM32F100 target, 5MHz
clock, results reading from flash, old driver:
dumped 131072 bytes in 98.445305s (1.300 KiB/s)
this implementation:
dumped 131072 bytes in 8.242686s (15.529 KiB/s)
Change-Id: Ic64d3124b1d6cd9dd1016445bb627c71e189ae95
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2356
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This provides support for various trace-related subsystems in a
generic and expandable way.
Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins
This should facilitate dynamic target creation and removal.
Currently it helps with getting 0 bytes lost report from Valgrind on
exit (after talking to a nucleo board). However, 1,223,886 bytes in
5,268 blocks are still reachable which means the app holds pointers to
that data on exit. The majority comes from the jtag command queue,
there're also many blocks from TCL command registration.
Change-Id: I7523234bb90fffd26f7d29cdd7648ddd221d46ab
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2544
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
The target might be using Tcl examine-start and examine-end handlers,
they need to be called when the target gets reexamined after polling
succeeds again.
Change-Id: I371380c6f3c427ec7a0206d73426f6589f18a9bd
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2536
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
This bug was exposed by Valgrind.
Change-Id: If50878664d928c0a44e309ca1452089c1ac71466
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2542
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Warning, behaviour change: before this patch if a timer callback
returned an error, the other handlers in the list were not called.
This patch fixes two different issues with the way timer callbacks are
called:
1. The function is not designed to be reentrant but a nested call is
possible via: target_handle timer event -> poll -> target events
before/after reexaminantion -> script_command_run ->
target_call_timer_callbacks_now . This patch makes function a no-op
when called recursively;
2. The current code can deal with the case when calling a handler
leads to its removal but not when it leads to removal of the next
callback in the list. This patch defers actual removal to consolidate
it with the calling loop.
These bugs were exposed by Valgrind.
Change-Id: Ia628a744634f5d2911eb329747e826cb9772e789
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2541
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
When target was already halted during the initial examination,
arm11_check_init() was trying to read, store and interpret DSCR
contents before the DPM structure is initialised. This caused
a segfault like described on
http://sourceforge.net/apps/trac/openocd/ticket/65 .
This is a totally untested attempt to fix this issue.
Change-Id: I2fff115679a3f0023e7a88c749ccb5f045d6cf01
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2043
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is runtime and valgrind tested with l0, l1 and f3 hla boards.
Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2516
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds the fpv4-sp-d16 registers to the armv7m register set.
The work is inspired by Mathias K but takes a different approach:
instead of having both double and single presicion registers in the
cache this patch works only with the doubles and counts on GDB to
split the data in halves whenever needed.
Tested with HLA only (on an STM32F334 disco board).
Currently this patch makes all ARMv7-M targets report an FPU-enabled
target description to GDB. It shouldn't harm if the user is not trying
to access non-existing FPU. However, the plan is to make this depend
on actual FPU presence later.
Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a
Signed-off-by: Mathias K <kesmtp@freenet.de>
[fercerpav@gmail.com: rework to fit target description framework]
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/514
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Found by clang static checker.
Change-Id: I77b0dc18188328fdb28d07b9e5c52e06182d9e2b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2561
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Given that the manual states that these two subcommands are
deprecated and were scheduled to be removed back in 2010,
remove them and the corresponding documentation from the
manual.
Change-Id: Iaac633349d7fcb8b7f964109c7d26dd0cc5fc233
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-on: http://openocd.zylin.com/1860
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Without this patch, to perform a memory read, OpenOCD first issues an
LDC instruction into DBGITR in Stall mode (thus executing the
instruction), then switches to Fast mode and reads from DBGDTRTX once
for each word to transfer.
At the very end of the transfer, the final Fast mode read of DBGDTRTX
has, as always, the side effect of re-issuing the LDC instruction. This
causes two problems:
(1) If the word immediately beyond the end of the requested region is
inaccessible, this spurious LDC will cause a fault. On a fast CPU, the
LDC will finish executing by the time the poll of DSCR takes place,
failing the entire memory read. On a slow CPU, the LDC might finish
executing later, leaving an unexpected and confusing sticky fault lying
around for the next operation to see.
(2) If the LDC succeeds, it will leave the loaded word in DBGDTRTX, thus
setting DBGDSCR.TXFULL=1. The cortex_a_read_apb_ab_memory routine
completes without consuming that last word, thus confusing the next
routine that tries to use DBGDTRTX (this may not have any visible effect
on some implementations, because writing to DBGDTRTXint when TXFULL=1 is
defined as Unpredictable, but I believe it caused a visible problem for
me).
With this patch, the bulk mem_ap_sel_read_buf_noincr is modified to omit
the last word of the block. The second-to-last read of DBGDTRTX by that
function will cause the issue of the LDC for the last word. After
switching back to Normal mode and waiting for that instruction to
finish, do a final read of DBGDTRTX to extract the last word into the
buffer, leaving TXFULL=0.
Without this patch, memory accesses are always expanded such that they
are aligned to the access size. With this patch, accesses are issued
exactly as ordered by the caller. The caller is expected to handle
fragments at the beginning and end of the transfer if the address is
unaligned and an unaligned access is not desired.
Without this patch, the DFAR and DFSR registers, which report the
location and status of data faults, are ignored while performing memory
accesses, which could cause problems debugging an OS page fault handler.
With this patch, DFAR and DFSR are preserved across memory accesses, and
DFSR is decoded in the event of a synchronous fault to provide the
caller with more information about the reason for failure.
Thanks to Boris Brezillon for the original patch whose ideas led to the
non-word access mechanism implemented here and to various code reviewers
for their comments.
Change-Id: I11ae7104fbe69a522efadefc705c9a217a7eef41
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/2381
Tested-by: jenkins
Reviewed-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Convert the DWT register store to use a byte array and fix the byte order
bug uncovered by that. Also fix an incorrect access of the PC value.
Change-Id: Idb5acab71bdf5a96895c358324b05c335e4d32ca
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2476
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The registers are represented as bit arrays intended to be accessed using
the buf_set_* and buf_get_* functions. Storing the register values in
integers enables accessing them directly, which gives different results
depending on host byte order.
Convert the register store to use a byte array instead and fix all the
byte order bugs uncovered by that.
Also merge the 32 and 64 bit register fields. Only one of them is used at
a time and after the change to byte arrays their types are also the same.
Change-Id: I456869a1737f4b4f5e8ecbfc1c63c49a75d21619
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2475
Tested-by: jenkins
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
On armv7 there no longer are 1kB pages. Instead the bit that in
older architectures distinguished 1kB pages from 4kB pages is on
armv7 used for as execute-never marker. There may now also be 16MB
supersections with 40 bit physical address.
Change-Id: I959bdb8012782a9d07d968907a21f50e3d9b356a
Signed-off-by: Daniel Glöckner <daniel-gl@gmx.net>
Reviewed-on: http://openocd.zylin.com/2386
Tested-by: jenkins
Reviewed-by: Vladimir Svoboda <ze.vlad@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add Cortex-A5 identification to ROM-table display, and also
to cortex_a_init_debug_access. This change is mostly cosmetic.
Change-Id: I7b1dd8755d70d45eb5f315aa1918d44a813b3cdf
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/2483
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The image struct is malloc'd and hence base_address_set doesn't have a
defined value.
Caught by Valgrind.
Change-Id: Ice15b2299fc768e44e8034eeb93e035076eacd03
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2524
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
After profiling gmon.out was being written in little endian format only
which would cause gprof to issue and error and exit on big endian targets.
Change-Id: I526a40adae0f9a439fc5b77cef30fda228198b48
Signed-off-by: Jose de Sousa <jose.t.de.sousa@gmail.com>
Reviewed-on: http://openocd.zylin.com/2168
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Also remove an unrelated no-op cast.
Change-Id: Ibeb6c72e5b0b0347abb568947a05a179661faf2d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2473
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This helps to uncover incorrect usage when a pointer to uint32_t is
passed to those functions which leads to subtle bugs on BE systems.
The reason is that it's normally assumed that any uint32_t variable
holds its value in host byte order, but using but_set_u32 on it
silently does implicit pointer conversion to (void *) and the
assumption ends up broken without any indication.
Change-Id: I48ffd190583d8aa32ec1fef8f1cdc0b4184e4546
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2467
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The default label does just return the same error code as the case for
zero, so this can be handled by a simple if statement.
Change-Id: I61a8cb51b5e261f21eca386af7d8cbf17ffa2d44
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/2430
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A7 MPCore needs unlocking the debug registers same as with A15 MPCore.
Found out by hacking on the code.
Change-Id: I613cb4fb35007b85b4a9a401577b47768bc1a08b
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-on: http://openocd.zylin.com/2344
Tested-by: jenkins
Reviewed-by: Kamal Dasu <kamal.dasu@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Added Cortex-A15 support for DAP AHB-AP init code as per ADI V5 spec.
Also added changes to make the APB MEM-AP to work with A15.
Made the the cortex_a target code generic to work with A8, A9
and A15 single core or multicore implementation. Added armv7a code
for os_border calculation to work for known A8, A9 and A15
platforms based on the ARM DDI 0344H, ARM DDI 0407F, ARM DDI 0406C
ARMV7A architecture docs.
Change-Id: Ib2803ab62588bf40f1ae4b9192b619af31525a1a
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1601
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
For example "bp 0x20000000 8 2" makes openocd segfaulting on a
stm32f4x Discovery board.
Change-Id: I1ddd46b1fa9ade78db2234ed975ccefb72539331
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/2342
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
GCC-4.2 on Mac/PPC complains about size_t is expected for %zx and the build stops.
In order to avoid other problems, I've chosen simply to typecast.
Change-Id: I99b569c4d1100e729712e31d24d6539f8b5971b6
Signed-off-by: Jens Bauer <jens@gpio.dk>
Reviewed-on: http://openocd.zylin.com/2360
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
When communication with target fails for whatever reason, it makes
sense to do JTAG-to-SWD (in case the target got power-cycled or the
DAP method was reset anyhow), SWD line reset sequence (part of
JTAG-to-SWD already) and the mandatory IDCODE read. Schedule that to
be performed on the next poll.
Fix the return values for ftdi and jlink drivers to be consistent with
OpenOCD error codes and remove ad-hoc calls to perform DAP method
switching (as it's now done from the upper layer automatically).
Change-Id: Ie18797d4ce7ac43d8249f8f81f1064a2424e02be
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2371
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mateusz Manowiecki <segmentation@fault.pl>
When a target was present on OpenOCD start but later disappeared for
whatever reason (typically unstable connection or target going to
sleep) and reappeared only for a brief period of time, reexamination
would fail, and poll would no longer run. This patch fixes it.
Change-Id: I61f9b5a3f366a761320e233f4e1689f926b5556d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2370
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
The FSF address has changed; The FSF site says that
address is
Free Software Foundation
51 Franklin Street, Fifth Floor
Boston, MA 02110-1301
USA
(see http://www.fsf.org/about/contact/)
Instead of updating it each time the address changes,
just drop it completely treewide.
Change-Id: I27199f7625901f677d8105d1e8876cff00147b71
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2340
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
added "Single Wire Output" and "Trace Memory Controller" peripheral
IDs to dap_rom_display(), which is invoked by the "dap info" command
Change-Id: Iea3201007bb98e6376fbb50be40a4a2e031b0a03
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2369
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
