This patch contains configuration for the twr-vf65gs10 system module
of the Freescale (NXP) tower system. It provides support for both the
CMSIS-DAP available via USB and the Cortex+ETM connector
on J5. The configuration also contains DDR and clock init code
hooked into the reset-init event handler.
Change-Id: I68303e0038e137dcadc57525e662428769fb69f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3564
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Both boards use SEGGER interface.
nRF52 flash driver is in change 3511.
The board files were needed for transport select to SWD. The default
jtag transport didn't failover to SWD.
Change-Id: Id9c72aa88eeeb6a4e1999ee182f5284dbe535c05
Signed-off-by: Rick Foos <rfoos@solengtech.com>
Reviewed-on: http://openocd.zylin.com/3600
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com>
Reviewed-by: Michael Dietz <mjdietzx@gmail.com>
Reviewed-by: Jiří Pinkava <j-pi@seznam.cz>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Linksys WAG200G router has a TI AR7 SoC and a 4MB Flash layout
similar to the Netgear DG834v3 router [1].
Below is an example of a successful flash recovery, using a TUMPA,
connected to the MIPS EJTAG 2.6 header (JP102) of the router.
WAG200G [2] TUMPA [3]
Desc Pin Pin Desc
------------------------
nTRST 1 3 nTRST
TDI 3 5 TDI
TDO 5 13 TDO
TMS 7 7 TMS
TCK 9 9 TCK
nSRST 11 15 RST
GND 2 4 GND
Note that nSRST is optional to halt the CPU, but is required to probe
the flash. For instance, recover the kernel with:
$ sudo ./src/openocd -s tcl \
-f interface/ftdi/tumpa.cfg \
-f tools/firmware-recovery.tcl \
-c 'board linksys-wag200g;
reset_config srst_only;
flash_part kernel /path/to/kernel.bin;
shutdown'
[1] https://wiki.openwrt.org/toh/linksys/wag200g
[2] https://www.linux-mips.org/wiki/JTAG#JTAG_headers
[3] http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual#20_PIN_JTAG_Connector
Change-Id: I952ba9f706e2e4f8f95ca03a5fa58f391ca030b6
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-on: http://openocd.zylin.com/3776
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Increase workareasize when it is know we have a larger device.
Change-Id: Ieaee92e7cd25cc201989f14de122349698871412
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3378
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Just like observed with the General App Kit earlier, it now started to
fail halting:
SWD IDCODE 0x2ba01477
TARGET: xmc4500.cpu - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'
SWD IDCODE 0x2ba01477
Halt timed out, wake up GDB.
Rely on the target's default sysresetreq behavior to allow flashing to
work seemlessly again.
Change-Id: Ib9ce5f2c0ab99dca6d0fc74435fe26a58437fae5
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3416
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The current configuration leads to the following error when trying to
program the target:
SWD IDCODE 0x2ba01477
timed out while waiting for target halted
TARGET: efm32.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 478
in procedure 'ocd_bouncer'
Use the default reset handling of the target (SYSRESETREQ) to reset the
system rather than SRST to fix the problem.
Tested on EFM32GG, EFM32TG and EZR32WG STK.
Change-Id: I788c41baf08b20814cbe0934b563424c4bc144b8
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3420
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Both the STM32F429I-DISC{O,1} boards are equipped with the same MCU, but
differ by the debugging chip:
- the STM32F429I-DISCO uses the ST-LINK/V2 chip;
- the STM32F429I-DISC1 uses the ST-LINK/V2-B chip (which matches the USB
VID/PID set in stlink-v2-1.cfg).
Change-Id: I07d637f72d26cf5d714472638da974eb6ca02325
Signed-off-by: Samuel Martin <s.martin49@gmail.com>
Reviewed-on: http://openocd.zylin.com/3492
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The XMC1000 family uses a very different flash interface from XMC4000.
Tested on XMC 2Go and XMC1100 Boot Kit.
Change-Id: I3edaed420ef1c0fb89fdf221022c8b04163d41b3
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3418
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for the Intel Quark mcu D2000 using the new quark_d2xx
target.
Changes to the lakemont part are needed for the D2000 core and
backwards compatible with the X1000 one.
Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3199
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with "J-Link OB RX621-ARM-SWD V1 compiled Nov 4 2014 10:47:22".
Change-Id: Ib64c0be407f99df57f058a4498556fd5ab7e9112
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3170
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with Relax Kit for 5V Shields:
J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50
and with Relax Lite Kit:
J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50
Derived from xmc4800-relax.cfg.
Change-Id: I4e10fb6ed1f85168634d3b5259d3041ffc6b74d8
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3130
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The pflash.0 bank should not be present as it overlaps with
the flash bank created by target/kx.cfg, triggering an error.
This is also in line with the existing twr-k60f120m.cfg.
Change-Id: I5f620e01319d967f12e029fb6865ccdd031713b3
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3108
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
16000kHz is only safe after PLLs have been locked
properly. Until that's done (with reset init), we
can only safely run at 1000kHz.
Change-Id: I4e0a17e88aa9919cd6c34d44da68e23115c0d3a3
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/3015
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested with cmsis-dap using the EDBG chip on the board.
Change-Id: I3d398685c81e4701a9f6c1a66e60f7a87f839daa
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/3092
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This reverts commit 7d7a43fd36.
The change concerns the "Black" variant of the TI BeagleBone, while the
configuration file is for the original BeagleBone board, which actually
embeds a debug interface on the PCB.
Change-Id: I2232af210deb698f8b3c0a547f26cd0a0a8f89d0
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3094
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: La Fonera FON2200
Change-Id: Ibfdbfc9c2beca6cf436c9ee5e493b08bfb55ac85
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2839
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: Netgear WP102
Change-Id: Id93957b5d5851a272f15be35f9f448a9ce6d8a08
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2835
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since 2cbbe9a it was actually decreasing the configured work area size.
We could now do "set WORKAREASIZE 0x2000" before sourcing lpc4350.cfg,
but there seems no point in doing so. Simply drop the configuration here.
Change-Id: I25b9dbbc007ba652b66099832198b7c329929858
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3086
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Board files should not select the interface. The BeagleBone Black is not
limited to just one JTAG interface.
Change-Id: I71ccc3dd9e2ca331a436701fab04e548b0abf829
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3083
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Adapted from diolan_lpc4350-db1.cfg. Both boards are identical except
for the SoC, so keep them in sync.
Change-Id: If892d8e953b0e3a9209a95b3b23a547357c10b7a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3038
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Its memory layout is different from MB9BFxxx.
Change-Id: I39c9f9cf582cd182971a9f83bb88c7a18da6cf15
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The xCORE-XA Core Module board has an XS1-XAU8A-10 SoC with 8 xCORE cores
and one ARM core. This config is for the ARM Cortex-M3, via J-Link OB.
Tested with "J-Link OB-STM32F103 V1 compiled Feb 5 2014 13:48:52".
Change-Id: Id7fadf8f323b45d5cfc0cae1054bd7b916771d6a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2763
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Another board supported by the ixo-usb-jtag project.
Change-Id: I676197c64e208886bc03d1bafcc964ef1fc2160b
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2963
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The board is supported via the ixo-usb-jtag firmware.
Change-Id: I1e8a5ead850c0843b8532a5b54a7e7117778278e
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2962
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested with Porcupine-1 JTAG adapter board and Digilent JTAG-HS3 interface;
reset does not yet work, pending nSRST configuration of the interface used.
Change-Id: I0d0679e098d93ffbd1539004cdb900e2a8ae4a25
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2730
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the chip IDs corresponding to the new 5V "SAMC" parts which are
otherwise identical to the SAMD and should work with this driver. Also
add the configurations for their Xplained Pro boards.
Change-Id: Ic268d4ac384a3a77d4211a94da9f9faf4d8c0f7b
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2809
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Pipistrello is a low cost FPGA board with a Xilinx
Spartan6 LX45, a SPI flash and onboard FTDI JTAG.
This board is a good example use case for the jtagspi
flash driver talking through a proxy bitstream.
Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2846
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
code polishing to be consistent with other scripts
Change-Id: Ib52a92f48df9d2bdf543792b856e33aa04dbebe3
Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com>
Reviewed-on: http://openocd.zylin.com/2779
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
