8b72657001
Add driver for the SH QSPI controller. This SPI controller is often connected to the boot SPI NOR flash on R-Car Gen2 platforms. Add the following two lines to board TCL file to bind the driver on R-Car Gen2 SoC and make SRAM work area available: flash bank flash0 sh_qspi 0xe6b10000 0 0 0 ${_TARGETNAME}0 cs0 ${_TARGETNAME}0 configure -work-area-phys 0xe6300000 -work-area-virt 0xe6300000 -work-area-size 0x10000 -work-area-backup 0 To install mainline U-Boot on the board, use the following procedure: proc update_uboot {} { # SPL flash erase_sector 0 0x0 0x0 flash write_bank 0 /u-boot/spl/u-boot-spl.bin 0x0 # U-Boot flash erase_sector 0 0x5 0x6 flash write_bank 0 /u-boot/u-boot.img 0x140000 } Change-Id: Ief22f61e93bcabae37f6e371156dece6c4be3459 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> --- V2: - Add Makefile and linker script for the SH QSPI IO algorithm - Include the algorithm code instead of hard-coding it Reviewed-on: http://openocd.zylin.com/5143 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> |
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at91sam7x | ||
bluenrg-x | ||
cc26xx | ||
cc3220sf | ||
fespi | ||
fm4 | ||
fpga | ||
kinetis | ||
kinetis_ke | ||
max32xxx | ||
msp432 | ||
sh_qspi | ||
stm32 | ||
xmc1xxx | ||
armv4_5_cfi_intel_8.s | ||
armv4_5_cfi_intel_16.s | ||
armv4_5_cfi_intel_32.s | ||
armv4_5_cfi_span_8.s | ||
armv4_5_cfi_span_16_dq7.s | ||
armv4_5_cfi_span_16.s | ||
armv4_5_cfi_span_32.s | ||
armv7m_cfi_span_16_dq7.s | ||
armv7m_cfi_span_16.s | ||
armv7m_io.s | ||
cortex-m0.S | ||
efm32.S | ||
k1921vk01t.S | ||
lpcspifi_erase.S | ||
lpcspifi_init.S | ||
lpcspifi_write.S | ||
mdr32fx.S | ||
mrvlqspi_write.S | ||
pic32mx.s | ||
sim3x.s | ||
stellaris.s | ||
str7x.s | ||
str9x.s |