Fixed LVGL.

Change SRAM MPU attributes back to NORMAL WB
LVGL testing, custom OpenOCD configuration
2021-01-18 02:20:07 +08:00 · 2021-01-17 20:34:50 +08:00 · 2021-01-17 20:26:19 +08:00
15 changed files with 228 additions and 47 deletions
--- a/Core/Inc/FreeRTOSConfig.h
+++ b/Core/Inc/FreeRTOSConfig.h
@ -64,7 +64,7 @@
 #define configTICK_RATE_HZ                       ((TickType_t)1000)
 #define configMAX_PRIORITIES                     ( 56 )
 #define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
-#define configTOTAL_HEAP_SIZE                    ((size_t)81920)
+#define configTOTAL_HEAP_SIZE                    ((size_t)262144)
 #define configMAX_TASK_NAME_LEN                  ( 16 )
 #define configUSE_TRACE_FACILITY                 1
 #define configUSE_16_BIT_TICKS                   0
--- a/Core/Inc/lv_conf.h
+++ b/Core/Inc/lv_conf.h
@ -20,8 +20,8 @@
 *====================*/

 /* Maximal horizontal and vertical resolution to support by the library.*/
-#define LV_HOR_RES_MAX          (104)
-#define LV_VER_RES_MAX          (212)
+#define LV_HOR_RES_MAX          (212)
+#define LV_VER_RES_MAX          (104)

 /* Color depth:
 * - 1:  1 byte per pixel
@ -48,7 +48,7 @@

 /* Default display refresh period.
 * Can be changed in the display driver (`lv_disp_drv_t`).*/
-#define LV_DISP_DEF_REFR_PERIOD      30      /*[ms]*/
+#define LV_DISP_DEF_REFR_PERIOD      60000      /*[ms]*/

 /* Dot Per Inch: used to initialize default sizes.
 * E.g. a button with width = LV_DPI / 2 -> half inch wide
@ -216,7 +216,7 @@ typedef void * lv_fs_drv_user_data_t;
 #endif

 /*1: Add a `user_data` to drivers and objects*/
-#define LV_USE_USER_DATA        0
+#define LV_USE_USER_DATA        1

 /*1: Show CPU usage and FPS count in the right bottom corner*/
 #define LV_USE_PERF_MONITOR     0
--- a/Core/Inc/stm32h7xx_it.h
+++ b/Core/Inc/stm32h7xx_it.h
@ -59,6 +59,7 @@ void RCC_IRQHandler(void);
 void DMA1_Stream0_IRQHandler(void);
 void EXTI9_5_IRQHandler(void);
 void SPI2_IRQHandler(void);
+void USART1_IRQHandler(void);
 void TIM7_IRQHandler(void);
 void FPU_IRQHandler(void);
 void QUADSPI_IRQHandler(void);
--- a/Core/Inc/user_lvgl_disp.h
+++ b/Core/Inc/user_lvgl_disp.h
@ -0,0 +1,14 @@
+#ifndef __USER_LVGL_DISP_H
+#define __USER_LVGL_DISP_H
+
+#include "lvgl.h"
+
+#include "depg0213_epd.h"
+
+void _epd_set_px_cb(lv_disp_drv_t *disp_drv, uint8_t *buf,
+                    lv_coord_t buf_w, lv_coord_t x, lv_coord_t y, lv_color_t color, lv_opa_t opa);
+
+void _epd_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area);
+void _epd_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p);
+
+#endif
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@ -355,9 +355,9 @@ static void MX_SPI2_Init(void)
  hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
  hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  hspi2.Init.CRCPolynomial = 0x0;
-  hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  hspi2.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
  hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
-  hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_16DATA;
+  hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
  hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
  hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
  hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
@ -591,7 +591,7 @@ void MPU_Config(void)

  HAL_MPU_ConfigRegion(&MPU_InitStruct);
  /* Enables the MPU */
-  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+  HAL_MPU_Enable(MPU_HFNMI_PRIVDEF_NONE);

 }
 /**
--- a/Core/Src/stm32h7xx_hal_msp.c
+++ b/Core/Src/stm32h7xx_hal_msp.c
@ -378,6 +378,9 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 6, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
@ -407,6 +410,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);

+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
  /* USER CODE BEGIN USART1_MspDeInit 1 */

  /* USER CODE END USART1_MspDeInit 1 */
--- a/Core/Src/stm32h7xx_it.c
+++ b/Core/Src/stm32h7xx_it.c
@ -59,6 +59,7 @@
 extern QSPI_HandleTypeDef hqspi;
 extern DMA_HandleTypeDef hdma_spi2_tx;
 extern SPI_HandleTypeDef hspi2;
+extern UART_HandleTypeDef huart1;
 extern TIM_HandleTypeDef htim7;

 /* USER CODE BEGIN EV */
@ -247,6 +248,20 @@ void SPI2_IRQHandler(void)
  /* USER CODE END SPI2_IRQn 1 */
 }

+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
 /**
  * @brief This function handles TIM7 global interrupt.
  */
--- a/Core/Src/user_irq_handlers.c
+++ b/Core/Src/user_irq_handlers.c
@ -8,7 +8,6 @@ extern osSemaphoreId_t g_epd_busy_semphr;
 extern osSemaphoreId_t g_spi2_semphr;

 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
-    // FIXME
    if(GPIO_Pin == SPI2_BUSY_Pin) {
        if(osKernelGetState() == osKernelRunning) { // Kernel has started, release semaphore.
            osSemaphoreRelease(g_epd_busy_semphr);
--- a/Core/Src/user_lvgl_disp.c
+++ b/Core/Src/user_lvgl_disp.c
@ -0,0 +1,46 @@
+#include "user_lvgl_disp.h"
+
+void _epd_set_px_cb(lv_disp_drv_t *disp_drv, uint8_t *buf,
+                    lv_coord_t buf_w, lv_coord_t x, lv_coord_t y, lv_color_t color, lv_opa_t opa) {
+    depg0213_epd_t *epd = disp_drv->user_data;
+
+    uint16_t byte_index;
+    uint8_t bit_index;
+
+    byte_index = x + (y / 8) * buf_w;
+    bit_index = 7 - (y & 7);
+
+    if(color.full) {
+        buf[byte_index] |= 1U << bit_index;
+    }
+    else {
+        buf[byte_index] &= ~(1U << bit_index);
+    }
+}
+
+void _epd_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area) {
+    depg0213_epd_t *epd = disp_drv->user_data;
+
+    if(epd->direction == DEPG0213_HORIZONTAL || epd->direction == DEPG0213_HORIZONTAL_INVERSE) {
+        area->y1 = (area->y1 / 8) * 8;
+        area->y2 = (area->y2 / 8) * 8 + 7;
+    }
+    else { // Vertical mode
+        area->x1 = (area->x1 / 8) * 8;
+        area->x2 = (area->x2 / 8) * 8 + 7;
+    }
+}
+
+void _epd_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) {
+    depg0213_epd_t *epd = disp_drv->user_data;
+
+    if(depg0213_epd_load(epd, color_p, NULL, area->x1, area->x2, area->y1, area->y2) != DEPG0213_OK) {
+        return;
+    }
+
+    if(lv_disp_flush_is_last(disp_drv)) {
+        if(depg0213_epd_update(epd) != DEPG0213_OK) return;
+    }
+
+    lv_disp_flush_ready(disp_drv);
+}
--- a/Core/Src/user_tasks.c
+++ b/Core/Src/user_tasks.c
@ -1,16 +1,24 @@
+#include <stdio.h>
+
 #include "cmsis_os2.h"

 #include "lvgl.h"

 #include "user_epd_impl.h"
+#include "user_lvgl_disp.h"

 // Defined in main.c
 extern SPI_HandleTypeDef hspi2;

 // Private function prototypes
 void user_task_flush_epd(void *arguments);
+void user_task_lvgl_tick(void *arguments);
+void user_task_hello(void *arguments);
+
 uint8_t _user_tasks_init_epd(void);
-void _user_tasks_init_lvgl(void);
+uint8_t _user_tasks_init_lvgl(void);
+
+#define FRAME_BUFFER_SIZE (212 * 10)

 // Globals
 depg0213_epd_t g_epd = {
@ -23,39 +31,84 @@ depg0213_epd_t g_epd = {
      }
 };

+lv_disp_buf_t g_disp_buf;
+lv_color_t g_epd_frame[FRAME_BUFFER_SIZE];
+lv_disp_t *g_epd_disp;
+
 osSemaphoreId_t g_epd_busy_semphr;
 osSemaphoreId_t g_spi2_semphr;
+osSemaphoreId_t g_lvgl_semphr;

 osThreadId_t g_flush_epd_task_handle;
 const osThreadAttr_t g_flush_epd_task_attributes = {
    .name = "flushEPD",
-    .priority = (osPriority_t) osPriorityNormal,
-    .stack_size = 512 * 4
+    .priority = (osPriority_t) osPriorityBelowNormal,
+    .stack_size = 2048 * 4
 };

-uint8_t frame_buffer_wb[212 * 104 / 8];
-uint8_t frame_buffer_rd[212 * 104 / 8];
+osThreadId_t g_lvgl_tick_handle;
+const osThreadAttr_t g_lvgl_tick_attributes = {
+    .name = "lvglTICK",
+    .priority = (osPriority_t) osPriorityBelowNormal,
+    .stack_size = 1024 * 4
+};
+
+osThreadId_t g_task_hello_handle;
+const osThreadAttr_t g_task_hello_attributes = {
+    .name = "HELLO",
+    .priority = (osPriority_t) osPriorityNormal,
+    .stack_size = 1024 * 4
+};

 void user_tasks_initialize(void) {
    HAL_NVIC_SetPriority(EXTI9_5_IRQn, 4, 0);
    HAL_NVIC_SetPriority(SPI2_IRQn, 4, 0);

    if(_user_tasks_init_epd()) return;
-    _user_tasks_init_lvgl();
+    if(_user_tasks_init_lvgl()) return;

    HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
    HAL_NVIC_SetPriority(SPI2_IRQn, 6, 0);

    g_flush_epd_task_handle = osThreadNew(user_task_flush_epd, NULL, &g_flush_epd_task_attributes);
+    g_lvgl_tick_handle = osThreadNew(user_task_lvgl_tick, NULL, &g_lvgl_tick_attributes);
+    g_task_hello_handle = osThreadNew(user_task_hello, NULL, &g_task_hello_attributes);
+}
+
+void user_task_hello(void *arguments) {
+    lv_obj_t *hello_label;
+    char buf[32];
+    osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
+    hello_label = lv_label_create(lv_scr_act(), NULL);
+    lv_label_set_align(hello_label, LV_LABEL_ALIGN_CENTER);
+    lv_label_set_text(hello_label, "Hello LVGL!!");
+    osSemaphoreRelease(g_lvgl_semphr);
+
+    for(;;) {
+        osDelay(10000);
+        snprintf(buf, 32, "LVGL@%ld", osKernelGetTickCount());
+        osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
+        lv_label_set_align(hello_label, LV_LABEL_ALIGN_CENTER);
+        lv_label_set_text(hello_label, buf);
+        osSemaphoreRelease(g_lvgl_semphr);
+    }
 }

 void user_task_flush_epd(void *arguments) {
    for(;;) {
-        memset(frame_buffer_wb, 0xFF, 212 * 104 / 8);
-        memset(frame_buffer_rd, 0x00, 212 * 104 / 8);
-        depg0213_epd_load(&g_epd, frame_buffer_wb, frame_buffer_rd);
-        depg0213_epd_deepsleep(&g_epd);
-        osDelay(300000);
+        osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
+        lv_task_handler();
+        osSemaphoreRelease(g_lvgl_semphr);
+        osDelay(200);
+    }
+}
+
+void user_task_lvgl_tick(void *arguments) {
+    for(;;) {
+        osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
+        lv_tick_inc(50);
+        osSemaphoreRelease(g_lvgl_semphr);
+        osDelay(50);
    }
 }

@ -71,15 +124,50 @@ uint8_t _user_tasks_init_epd(void) {
    ret = depg0213_epd_init(&g_epd);
    if(ret != DEPG0213_OK) return -2;

-    ret = depg0213_epd_direction(&g_epd, DEPG0213_HORIZONTAL_INVERSE);
+    ret = depg0213_epd_window(&g_epd, DEPG0213_HORIZONTAL, 0, 211, 0, 103);
    if(ret != DEPG0213_OK) return -3;

+    uint8_t buffer = 0x00;
+    for(uint16_t i = 0; i < 212; i++) {
+        for(uint16_t j = 0; j < 13; j++) {
+            depg0213_epd_load(&g_epd, NULL, &buffer, i, i, j * 8, j * 8 + 7);
+        }
+    }
+    buffer = 0xFF;
+    for(uint16_t i = 0; i < 212; i++) {
+        for(uint16_t j = 0; j < 13; j++) {
+            depg0213_epd_load(&g_epd, &buffer, NULL, i, i, j * 8, j * 8 + 7);
+        }
+    }
    ret = depg0213_epd_deepsleep(&g_epd);
-    if(ret != DEPG0213_OK) return -4;
+    if(ret != DEPG0213_OK) return -6;

    return 0;
 }

-void _user_tasks_init_lvgl(void) {
+uint8_t _user_tasks_init_lvgl(void) {
+    g_lvgl_semphr = osSemaphoreNew(1U, 1U, NULL); // Max: 1, initial 1, attr NULL
+    if(g_lvgl_semphr == NULL) return -1;
+
    lv_init();
+
+    lv_disp_buf_init(&g_disp_buf, g_epd_frame, NULL, FRAME_BUFFER_SIZE);
+
+    lv_disp_drv_t disp_drv;
+    lv_disp_drv_init(&disp_drv);
+    disp_drv.buffer = &g_disp_buf;
+    disp_drv.set_px_cb = _epd_set_px_cb;
+    disp_drv.flush_cb = _epd_flush_cb;
+    disp_drv.rounder_cb = _epd_rounder_cb;
+    disp_drv.user_data = &g_epd;
+
+    g_epd_disp = lv_disp_drv_register(&disp_drv);
+
+    if(g_epd_disp == NULL) {
+        for(;;) {
+            //
+         }
+    }
+
+    return 0;
 }
--- a/Drivers/Third_Party/depg0213_epd
+++ b/Drivers/Third_Party/depg0213_epd
@ -1 +1 @@
-Subproject commit 8abed07c233edb7fd2379eb5cc23d15abb10bcbe
+Subproject commit 77b9c803d81d5b7a5fd9cf2bcb13f4df1a545dc7
--- a/8
+++ b/8
@ -1,5 +1,5 @@
 ##########################################################################################################################
-# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Fri Jan 15 00:23:26 CST 2021] 
+# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Sun Jan 17 23:36:54 CST 2021] 
 ##########################################################################################################################

 # ------------------------------------------------
@ -42,6 +42,7 @@ Core/Src/stm32h7xx_hal_msp.c \
 Core/Src/user_epd_impl.c \
 Core/Src/user_tasks.c \
 Core/Src/user_irq_handlers.c \
+Core/Src/user_lvgl_disp.c \
 Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
 Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
 Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
@ -242,7 +243,8 @@ AS_DEFS =
 C_DEFS =  \
 -DUSE_HAL_DRIVER \
 -DSTM32H750xx \
-DLV_CONF_INCLUDE_SIMPLE
+-DLV_CONF_INCLUDE_SIMPLE \
+-DDEPG0213_LUT_OTP=1


 # AS includes
@ -285,7 +287,7 @@ LDSCRIPT = STM32H750VBTx_FLASH.ld
 # libraries
 LIBS = -lc -lm -lnosys 
 LIBDIR = 
-LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
+LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -Wl,--print-memory-usage

 # default action: build all
 all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
--- a/STM32H750VBTx_FLASH.ld
+++ b/STM32H750VBTx_FLASH.ld
@ -53,7 +53,7 @@
 ENTRY(Reset_Handler)

 /* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
+_estack = 0x24080000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x200;      /* required amount of heap  */
 _Min_Stack_Size = 0x400; /* required amount of stack */
@ -147,7 +147,7 @@ SECTIONS

    . = ALIGN(4);
    _edata = .;        /* define a global symbol at data end */
-  } >DTCMRAM AT> FLASH
+  } >RAM_D1 AT> FLASH

  
  /* Uninitialized data section */
@ -164,7 +164,7 @@ SECTIONS
    . = ALIGN(4);
    _ebss = .;         /* define a global symbol at bss end */
    __bss_end__ = _ebss;
-  } >DTCMRAM
+  } >RAM_D1

  /* User_heap_stack section, used to check that there is enough RAM left */
  ._user_heap_stack :
@ -175,9 +175,7 @@ SECTIONS
    . = . + _Min_Heap_Size;
    . = . + _Min_Stack_Size;
    . = ALIGN(8);
-  } >DTCMRAM
-
-  
+  } >RAM_D1

  /* Remove information from the standard libraries */
  /DISCARD/ :
--- a/STM32H750_EPD.ioc
+++ b/STM32H750_EPD.ioc
@ -1,7 +1,7 @@
 #MicroXplorer Configuration settings - do not modify
 Mcu.Family=STM32H7
 NVIC.FLASH_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
-RCC.DIVQ2Freq_Value=16125000
+RCC.DIVQ2Freq_Value=100000000
 ProjectManager.MainLocation=Core/Src
 Dma.SPI2_TX.0.MemInc=DMA_MINC_ENABLE
 SPI2.VirtualNSS=VM_NSSHARD
@ -20,14 +20,14 @@ PC10.Locked=true
 PC10.Signal=QUADSPI_BK1_IO1
 PB14.GPIO_Label=SPI2_DC
 PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_SPI2_Init-SPI2-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_SPI2_Init-SPI2-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 PD8.Locked=true
 VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
 RCC.RTCFreq_Value=32768
 PC9.Locked=true
 CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_FULL_ACCESS
 RCC.CpuClockFreq_Value=240000000
-RCC.VCO2OutputFreq_Value=32250000
+RCC.VCO2OutputFreq_Value=200000000
 Dma.SPI2_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
 USART1.IPParameters=VirtualMode-Asynchronous
 PD8.GPIO_PuPd=GPIO_PULLUP
@ -43,6 +43,7 @@ RCC.AHB4Freq_Value=120000000
 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
 Dma.SPI2_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
 RCC.VCOInput3Freq_Value=250000
+CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_NOT_SHAREABLE
 RCC.LPTIM1Freq_Value=120000000
 Mcu.IP4=NVIC
 Mcu.IP5=QUADSPI
@ -69,7 +70,7 @@ Mcu.IPNb=11
 ProjectManager.PreviousToolchain=
 RCC.SPDIFRXFreq_Value=60000000
 CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_TEX_LEVEL1
-PD8.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP,PinState,GPIO_PuPd
+PD8.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
 RCC.DIVQ3Freq_Value=16125000
 Mcu.Pin6=PB2
 PD8.Signal=GPIO_Output
@ -97,6 +98,7 @@ NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 PB2.Signal=QUADSPI_CLK
 CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_SIZE_128KB
 Mcu.IP10=USART1
+RCC.DIVM2=4
 NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
 RCC.DIVM1=4
 RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
@ -119,17 +121,17 @@ PA14\ (JTCK/SWCLK).Mode=Serial_Wire
 NVIC.SPI2_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
 NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
 Dma.SPI2_TX.0.RequestNumber=1
-RCC.DIVR2Freq_Value=16125000
+RCC.DIVR2Freq_Value=100000000
 CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_ENABLE
 Dma.RequestsNb=1
 ProjectManager.HalAssertFull=false
-FREERTOS.configTOTAL_HEAP_SIZE=81920
-RCC.DIVP2Freq_Value=16125000
+FREERTOS.configTOTAL_HEAP_SIZE=262144
+RCC.DIVP2Freq_Value=25000000
 ProjectManager.ProjectName=STM32H750_EPD
 RCC.APB3Freq_Value=120000000
 RCC.MCO2PinFreq_Value=240000000
 Mcu.Package=LQFP100
-SPI2.FifoThreshold=SPI_FIFO_THRESHOLD_16DATA
+SPI2.FifoThreshold=SPI_FIFO_THRESHOLD_01DATA
 PB12.Mode=NSS_Signal_Hard_Output
 NVIC.TimeBase=TIM7_IRQn
 SPI2.Mode=SPI_MODE_MASTER
@ -154,6 +156,7 @@ RCC.LPUART1Freq_Value=120000000
 NVIC.DMA1_Stream0_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
 SPI2.Direction=SPI_DIRECTION_2LINES_TXONLY
 PB13.Mode=TX_Only_Simplex_Unidirect_Master
+NVIC.USART1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
 Dma.Request0=SPI2_TX
 PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
 NVIC.TIM7_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
@ -182,15 +185,17 @@ Mcu.PinsNb=24
 ProjectManager.NoMain=false
 PC11.Locked=true
 NVIC.SavedSvcallIrqHandlerGenerated=true
+CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_NOT_SHAREABLE
 PC11.Signal=GPIO_Output
 VP_SYS_VS_tim7.Mode=TIM7
 CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_BUFFERABLE
 RCC.SWPMI1Freq_Value=120000000
 CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE
 RCC.SAI4BFreq_Value=60000000
-SPI2.NSSPMode=SPI_NSS_PULSE_ENABLE
+SPI2.NSSPMode=SPI_NSS_PULSE_DISABLE
 PC10.Mode=Single Bank 1
 ProjectManager.DefaultFWLocation=true
+RCC.DIVP2=8
 PD9.Signal=GPXTI9
 ProjectManager.DeletePrevious=true
 PB14.Locked=true
@ -204,7 +209,7 @@ PD8.GPIO_Label=SPI2_RES
 RCC.SPI6Freq_Value=120000000
 RCC.D1CPREFreq_Value=240000000
 USART1.VirtualMode-Asynchronous=VM_ASYNC
-CORTEX_M7.MPU_Control=MPU_PRIVILEGED_DEFAULT
+CORTEX_M7.MPU_Control=MPU_HFNMI_PRIVDEF_NONE
 RCC.USART234578Freq_Value=120000000
 PA9.Mode=Asynchronous
 RCC.SPI45Freq_Value=120000000
@ -217,6 +222,7 @@ CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LE
 RCC.VCO1OutputFreq_Value=480000000
 PA9.Signal=USART1_TX
 RCC.AXIClockFreq_Value=120000000
+RCC.DIVN2=100
 CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_CACHEABLE
 RCC.DIVN1=240
 CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
@ -245,12 +251,12 @@ RCC.FDCANFreq_Value=60000000
 Dma.SPI2_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
 RCC.RNGFreq_Value=48000000
 CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_SHAREABLE
-RCC.ADCFreq_Value=16125000
+RCC.ADCFreq_Value=25000000
 CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
 NVIC.HSEM1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
 ProjectManager.FreePins=false
-RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVN1,DIVN2,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
 ProjectManager.AskForMigrate=true
 Mcu.Name=STM32H750VBTx
 RCC.LPTIM2Freq_Value=120000000
@ -260,7 +266,7 @@ NVIC.SavedPendsvIrqHandlerGenerated=true
 CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS
 ProjectManager.UnderRoot=false
 CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
-CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings
+CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings
 Mcu.IP8=SPI2
 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
 Mcu.IP9=SYS
@ -312,7 +318,7 @@ CORTEX_M7.CPU_DCache=Enabled
 RCC.HCLK3ClockFreq_Value=120000000
 PB12.GPIO_PuPd=GPIO_PULLUP
 Dma.SPI2_TX.0.Direction=DMA_MEMORY_TO_PERIPH
-RCC.VCOInput2Freq_Value=250000
+RCC.VCOInput2Freq_Value=2000000
 PD9.Locked=true
 RCC.APB1Freq_Value=120000000
 PD8.PinState=GPIO_PIN_SET
--- a/generic_stm32h7.cfg
+++ b/generic_stm32h7.cfg
@ -0,0 +1,7 @@
+source /home/imi415/Documents/Conf/OpenOCD/interface/ft232-swd.cfg
+
+source [find target/stm32h7x.cfg]
+
+reset_config none
+cortex_m reset_config sysresetreq
+gdb_breakpoint_override hw
Author	SHA1	Message	Date
imi415	3ab650c6aa	Fixed LVGL. continuous-integration/drone/push Build is passing Details	2021-01-18 02:20:07 +08:00
imi415	61fbc21f8f	Change SRAM MPU attributes back to NORMAL WB continuous-integration/drone/push Build is passing Details	2021-01-17 20:34:50 +08:00
imi415	65dad330ae	LVGL testing, custom OpenOCD configuration continuous-integration/drone/push Build is passing Details LVGL is broken for now.	2021-01-17 20:26:19 +08:00