For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- AIRCR_SYSRESETREQ is generic; use it on any system where
SRST won't fly, not just on Stellaris-based ones.
- Reformat and improve comments about the Stellaris quirk; and
xref the only public docs (an email) about the issue.
It seems that *most* Stellaris chips have this problem. Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
issue with this is that the core debug support uses this
mechanism, then trashes its state over reset. Users can
Work around that (for now) by re-assigning the desired
config after reset.
Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Clean up treatment of registers in ARMv7-M and Cortex-M3.
- At the arch level:
* Just list registers and names; don't impose core-specific
policy about how they are accessed.
* Each register has a symbol.
* Remove the register mode field (irrelevant to debugger)
- At the core/implementation level:
* Just map the registers to their relevant access methods;
don't require the arch level to say how that should work
(cores other than Cortex-M3 could do it differently).
* Don't use undefined bits from register 20.
* Use register IDs that are part of the ARMv7-M interface.
In short, there's now a real distinction between the arch
and core layers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Initial support for disassembling Thumb2 code. This works only for
Cortex-M3 cores so far. Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.
- Update the 16-bit Thumb decoder:
* Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
by ARMv6. (It already seems to treat CPY as MOV.)
* Understand CB, CBNZ, WFI, IT, and other opcodes added by
in Thumb2.
- A new Thumb2 instruction decode routine is provided.
* This has a different signature: pass the target, not the
instruction, so it can fetch a second halfword when needed.
The instruction size is likewise returned to the caller.
* 32-bit instructions are recognized but not yet decoded.
- Start using the current "UAL" syntax in some cases. "SWI" is
renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".
- Define a new "cortex_m3 disassemble addr count" command to give
access to this disassembly.
Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch correctly identifies a running target.
Patch made a tad more palatable by David Brownell <david-b@pacbell.net>
git-svn-id: svn://svn.berlios.de/openocd/trunk@2510 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Update handle_reset_config_command in tcl.c to use new helpers.
- Replace direct accesses in JTAG interface and target drivers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2161 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add accessor functions to return their value.
- Use new SRST accessor in cortex_m3.c and mips_m4k.c
git-svn-id: svn://svn.berlios.de/openocd/trunk@2157 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- set TAR size to 12 bits for Cortex-M3.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2051 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- change SWJDP_IR/DR_APACC to DAP_IR/DR_APACC to conform with ARM_ADI docs.
- add swjdp->memaccess_tck field and code for extra tck clocks before accessing memory bus
- Set default memaccess value to 8 for Cortex-M3.
- Add dap memaccess command.
- document all armv7 dap cmds.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2005 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move definition of 'struct target_type_s' into new 'target_type.h' file.
- Forward delclaration remains in target.h, with comment pointing to new file.
- Replaces #define with #include in source files.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1971 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add DEFINE_TARGET_TYPE_S symbol in files that need it defined.
- Forward declare 'struct target_type_s' only, unless that symbol is defined.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1969 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replace all checks of target->type->examined with target_was_examined().
- replace all setting of target->type->examined with target_set_examined().
- replace clearing of target->type->examined with target_reset_examined().
- add documentation in target_s to warn not to access field directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1962 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->write_memory.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1960 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->read_memory.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1959 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Added support for accessport ROM table identification, dap command.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
(step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen
git-svn-id: svn://svn.berlios.de/openocd/trunk@1008 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- cleaned up headers to match rest of code
- added missing svn props for previously added files
git-svn-id: svn://svn.berlios.de/openocd/trunk@987 b42882b7-edfa-0310-969c-e2dbd0fdcd60
converts a number of 'simple string lookup tables' into NVP tables.
These NVP tables will be used by various commands coming in the next patch.
git-svn-id: svn://svn.berlios.de/openocd/trunk@962 b42882b7-edfa-0310-969c-e2dbd0fdcd60
