Add configuration for the Renesas R-Car R8A7794 E2
based Silk evaluation board.
Change-Id: I504b5630b1a2791ed6967c6c2af8851ceef9723f
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
NOTE: This requires SW7[1] in position 1 (default is 0)
Reviewed-on: http://openocd.zylin.com/4532
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Added cc26xx flash driver to support the TI CC26xx and CC13xx
microcontrollers. Driver is capable of determining which MCU
is connected and configures itself accordingly. Added config
files for four specific variants: CC26x0, CC13x0, CC26x2, and
CC13x2.
Note that the flash loader code is based on the sources used
to support flash in Code Composer Studio and Uniflash from TI.
Removed cc26xx.cfg file made obsolete by this patch.
Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4358
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Added cc3220sf flash driver to support the TI CC3220SF
microcontrollers. Implemented flash driver to support the
internal flash of the CC3220SF. The implementation does not
support the serial flash of the CC32xx family that requires
connection over UART, and not via JTAG/SWD debug. Added config
files for both CC32xx devices (no flash) and CC3220SF (with
flash).
Updated to implement comments from code review.
Additional updates to handle remaining comments from review.
Additional updates per review.
Added code to only request aligned writes and full 32-bit
words down to flash helper algorithm. Updated for recent
changes in OpenOCD flash code.
Removed cc32xx.cfg file made obsolete by this patch.
Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4319
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The "Blue Pill" is a popular development board with an STM32F103C8
micro controller. According to sources, it has a 128kB Flash on board
even though the option bytes only report 64kB. This patch therefore also
modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into
account which the board file sets to 0x20000.
Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4495
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
includes target configuration for i.MX8M SoC family,
board file needs to set up CHIPNAME and CHIPCORES
to match the actual hardware configuration
Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4434
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
configuration also contains a reset-init procedure that disables the
watchdog and initilizes the boards DDR memory so that you can upload
baremetal (e.g. boot loader) code into DDR and start it from there.
Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4227
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Most Xilinx FPGA devices contain an embedded, unique device identifier.
The identifier is nonvolatile, permanently programmed into the FPGA, and is
unchangeable providing a great serial / tracking number.
This commit adds generic support for reading the Xilinx Spartan 6 and 7
Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to
the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register
addresses are different and the logic has been simplified.
The code was not placed in xilinx-xc7.cfg. The approach of defining taps
in the same file as library code to use them is fundamentally broken on
boards that have more than one FPGA or other chips. This commit (like
the addition of support for Xilinx XADC) starts to remedy that by
splitting library code from board-specific fixed definitions.
The support code is sourced in the Kasli and KC705 board support files
as it was tested on these boards.
Change-Id: Iba559c7c1b7e93e1270535fd9e6650007f3794da
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4396
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
temperature, internal power supply rail voltages as well as external
voltages. The XADC is available both from fabric as well as through the
JTAG TAP.
This code implements access throught the JTAG TAP.
https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
Change-Id: I6cef4d0244add71749fa28b58a736302151cc4dd
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4395
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Kasli is an open hardware FPGA board. It is part of the Sinara family of
devices designed to control quantum physics experiments (see Sayma_AMC
for other boards already suppported by openocd).
Kasli was developed as part of the opticlock project. It features a
Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and
distribution network, four 6 Gb/s transceiver links (three SFP and
one SATA) as well as interfaces to up to 12 Eurocard Extension Modules
(EEMs).
https://github.com/m-labs/sinara/wiki/Kaslihttp://www.opticlock.de/en/
Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4341
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
* Disables the data output pin while SWD is reading, so that a simple FTDI
SWD interface can be made by connecting TCK to SWD_CLK and TDI+TDO directly
to SWDIO. Enabled by setting SWDIO_OE to 0.
Change-Id: I7d3b71cf3f4eea163cb320aff69ed95d219190bd
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com>
Reviewed-on: http://openocd.zylin.com/2274
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
We can now use the generic stlink.cfg which allows for both ST-LINK/V2
and V2-1 debuggers.
Change-Id: I229c6fe5f6a6a4f2d3c787a49939846f102f9e24
Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
Reviewed-on: http://openocd.zylin.com/4313
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Extend HLA interface to allow multiple VID/PID pairs and use it to
autodetect the connected stlink version.
Change-Id: I35cd895b2260e23cf0e8fcb1fc11a78c2b99c69b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3961
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Similar to the Sheevaplug fix inf95f8b70fbd0f7e9c91a2d9006b1abb2dd07ebf2
the OpenRD device has its JTAG interface on the first channel of the
ft2232, which is 0 for the new driver but was 1 for the old one. Correct
the config file appropriately. Also the device description was missing
the trailing " B" and thus not picking up the device correctly. Finally
add an adapter_khz setting in the OpenRD board configuration file - set
to 2MHz to match the Sheeva variant.
Confirmed as working thanks to Phil Hands providing me access to his
hardware to test on.
See also Debian Bug#793214; https://bugs.debian.org/793214
Change-Id: Ifacf53124eaa330bbbdf36dfa79e3256bf2a5201
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4254
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This config covers the 4x Cortex A53 CPUs. A custom connector
is required from J14 to standard ARM JTAG on v1 boards. However
v2 hardware should have a standard FTSH-105-01-L-DV connector.
Pinmuxing code to enable JTAG pins is included in l-loader-poplar
repository, so board is flashed with open source code, JTAG
is available at very early boot. Alternatively the following
pokes can be issued from U-Boot to enable JTAG (e.g. to debug
hisilicon SDK).
mw 0xf8a210ec 0x130;
mw 0xf8a210f0 0x130;
mw 0xf8a210f4 0x130;
mw 0xf8a210f8 0x130;
mw 0xf8a210fc 0x130;
mw 0xf8a21100 0x130;
Change-Id: I2b83dfcb3dc5461c1620f94dd99aa7b31fdda59b
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-on: http://openocd.zylin.com/4161
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Finally we can use this driver by default!
Change-Id: I09d215d1bd1dc16873a7379637e6869af65ad8f1
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4193
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds the file ti_beaglebone-base.cfg as the common base
configuration for all TI BeagleBone derived boards. It also modifies
ti_beaglebone.cfg to source the base board and only add the on-board
JTAG adapter. Lastly, it adds a file ti_beaglebone_black.cfg with
a suitable configuraton for the BeagleBone "Black" variant.
Change-Id: I40cacb8abed7bdb308929713891f7b5e5b685c95
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3099
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
configuration covers all 8 Cortex-A53 cores and auxiliary Cortex-M3
used for power management.
Change-Id: I5509f275aa669abe285f9152935ecdcbcd0c402e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4009
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch contains configuration for the twr-vf65gs10 system module
of the Freescale (NXP) tower system. It provides support for both the
CMSIS-DAP available via USB and the Cortex+ETM connector
on J5. The configuration also contains DDR and clock init code
hooked into the reset-init event handler.
Change-Id: I68303e0038e137dcadc57525e662428769fb69f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3564
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Both boards use SEGGER interface.
nRF52 flash driver is in change 3511.
The board files were needed for transport select to SWD. The default
jtag transport didn't failover to SWD.
Change-Id: Id9c72aa88eeeb6a4e1999ee182f5284dbe535c05
Signed-off-by: Rick Foos <rfoos@solengtech.com>
Reviewed-on: http://openocd.zylin.com/3600
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com>
Reviewed-by: Michael Dietz <mjdietzx@gmail.com>
Reviewed-by: Jiří Pinkava <j-pi@seznam.cz>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Linksys WAG200G router has a TI AR7 SoC and a 4MB Flash layout
similar to the Netgear DG834v3 router [1].
Below is an example of a successful flash recovery, using a TUMPA,
connected to the MIPS EJTAG 2.6 header (JP102) of the router.
WAG200G [2] TUMPA [3]
Desc Pin Pin Desc
------------------------
nTRST 1 3 nTRST
TDI 3 5 TDI
TDO 5 13 TDO
TMS 7 7 TMS
TCK 9 9 TCK
nSRST 11 15 RST
GND 2 4 GND
Note that nSRST is optional to halt the CPU, but is required to probe
the flash. For instance, recover the kernel with:
$ sudo ./src/openocd -s tcl \
-f interface/ftdi/tumpa.cfg \
-f tools/firmware-recovery.tcl \
-c 'board linksys-wag200g;
reset_config srst_only;
flash_part kernel /path/to/kernel.bin;
shutdown'
[1] https://wiki.openwrt.org/toh/linksys/wag200g
[2] https://www.linux-mips.org/wiki/JTAG#JTAG_headers
[3] http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual#20_PIN_JTAG_Connector
Change-Id: I952ba9f706e2e4f8f95ca03a5fa58f391ca030b6
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Reviewed-on: http://openocd.zylin.com/3776
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Increase workareasize when it is know we have a larger device.
Change-Id: Ieaee92e7cd25cc201989f14de122349698871412
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3378
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Just like observed with the General App Kit earlier, it now started to
fail halting:
SWD IDCODE 0x2ba01477
TARGET: xmc4500.cpu - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'
SWD IDCODE 0x2ba01477
Halt timed out, wake up GDB.
Rely on the target's default sysresetreq behavior to allow flashing to
work seemlessly again.
Change-Id: Ib9ce5f2c0ab99dca6d0fc74435fe26a58437fae5
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3416
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The current configuration leads to the following error when trying to
program the target:
SWD IDCODE 0x2ba01477
timed out while waiting for target halted
TARGET: efm32.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 478
in procedure 'ocd_bouncer'
Use the default reset handling of the target (SYSRESETREQ) to reset the
system rather than SRST to fix the problem.
Tested on EFM32GG, EFM32TG and EZR32WG STK.
Change-Id: I788c41baf08b20814cbe0934b563424c4bc144b8
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3420
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Both the STM32F429I-DISC{O,1} boards are equipped with the same MCU, but
differ by the debugging chip:
- the STM32F429I-DISCO uses the ST-LINK/V2 chip;
- the STM32F429I-DISC1 uses the ST-LINK/V2-B chip (which matches the USB
VID/PID set in stlink-v2-1.cfg).
Change-Id: I07d637f72d26cf5d714472638da974eb6ca02325
Signed-off-by: Samuel Martin <s.martin49@gmail.com>
Reviewed-on: http://openocd.zylin.com/3492
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The XMC1000 family uses a very different flash interface from XMC4000.
Tested on XMC 2Go and XMC1100 Boot Kit.
Change-Id: I3edaed420ef1c0fb89fdf221022c8b04163d41b3
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3418
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for the Intel Quark mcu D2000 using the new quark_d2xx
target.
Changes to the lakemont part are needed for the D2000 core and
backwards compatible with the X1000 one.
Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3199
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with "J-Link OB RX621-ARM-SWD V1 compiled Nov 4 2014 10:47:22".
Change-Id: Ib64c0be407f99df57f058a4498556fd5ab7e9112
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3170
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with Relax Kit for 5V Shields:
J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50
and with Relax Lite Kit:
J-Link Lite-XMC4200 Rev.1 compiled Oct 14 2015 10:14:50
Derived from xmc4800-relax.cfg.
Change-Id: I4e10fb6ed1f85168634d3b5259d3041ffc6b74d8
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3130
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The pflash.0 bank should not be present as it overlaps with
the flash bank created by target/kx.cfg, triggering an error.
This is also in line with the existing twr-k60f120m.cfg.
Change-Id: I5f620e01319d967f12e029fb6865ccdd031713b3
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3108
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
16000kHz is only safe after PLLs have been locked
properly. Until that's done (with reset init), we
can only safely run at 1000kHz.
Change-Id: I4e0a17e88aa9919cd6c34d44da68e23115c0d3a3
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/3015
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested with cmsis-dap using the EDBG chip on the board.
Change-Id: I3d398685c81e4701a9f6c1a66e60f7a87f839daa
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/3092
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This reverts commit 7d7a43fd36.
The change concerns the "Black" variant of the TI BeagleBone, while the
configuration file is for the original BeagleBone board, which actually
embeds a debug interface on the PCB.
Change-Id: I2232af210deb698f8b3c0a547f26cd0a0a8f89d0
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3094
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: La Fonera FON2200
Change-Id: Ibfdbfc9c2beca6cf436c9ee5e493b08bfb55ac85
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2839
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: Netgear WP102
Change-Id: Id93957b5d5851a272f15be35f9f448a9ce6d8a08
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2835
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since 2cbbe9a it was actually decreasing the configured work area size.
We could now do "set WORKAREASIZE 0x2000" before sourcing lpc4350.cfg,
but there seems no point in doing so. Simply drop the configuration here.
Change-Id: I25b9dbbc007ba652b66099832198b7c329929858
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3086
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Board files should not select the interface. The BeagleBone Black is not
limited to just one JTAG interface.
Change-Id: I71ccc3dd9e2ca331a436701fab04e548b0abf829
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3083
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Adapted from diolan_lpc4350-db1.cfg. Both boards are identical except
for the SoC, so keep them in sync.
Change-Id: If892d8e953b0e3a9209a95b3b23a547357c10b7a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3038
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Its memory layout is different from MB9BFxxx.
Change-Id: I39c9f9cf582cd182971a9f83bb88c7a18da6cf15
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The xCORE-XA Core Module board has an XS1-XAU8A-10 SoC with 8 xCORE cores
and one ARM core. This config is for the ARM Cortex-M3, via J-Link OB.
Tested with "J-Link OB-STM32F103 V1 compiled Feb 5 2014 13:48:52".
Change-Id: Id7fadf8f323b45d5cfc0cae1054bd7b916771d6a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2763
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Another board supported by the ixo-usb-jtag project.
Change-Id: I676197c64e208886bc03d1bafcc964ef1fc2160b
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2963
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The board is supported via the ixo-usb-jtag firmware.
Change-Id: I1e8a5ead850c0843b8532a5b54a7e7117778278e
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2962
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested with Porcupine-1 JTAG adapter board and Digilent JTAG-HS3 interface;
reset does not yet work, pending nSRST configuration of the interface used.
Change-Id: I0d0679e098d93ffbd1539004cdb900e2a8ae4a25
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2730
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the chip IDs corresponding to the new 5V "SAMC" parts which are
otherwise identical to the SAMD and should work with this driver. Also
add the configurations for their Xplained Pro boards.
Change-Id: Ic268d4ac384a3a77d4211a94da9f9faf4d8c0f7b
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2809
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Pipistrello is a low cost FPGA board with a Xilinx
Spartan6 LX45, a SPI flash and onboard FTDI JTAG.
This board is a good example use case for the jtagspi
flash driver talking through a proxy bitstream.
Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2846
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
code polishing to be consistent with other scripts
Change-Id: Ib52a92f48df9d2bdf543792b856e33aa04dbebe3
Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com>
Reviewed-on: http://openocd.zylin.com/2779
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reset stopped working with this setting.
Change-Id: I98e8fafa48e0ab65dce8110870be422edf7b2fdb
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2727
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Split TMS570 target into LS31/LS21 and LS20/LS10 targets.
Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI.
Tested attaching.
Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620
Signed-off-by: Alex Ray <a@machinaut.com>
Reviewed-on: http://openocd.zylin.com/2089
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds support for the new Atmel SAML21 family of low-power Cortex
M0+ devices. Their Flash controller is essentially the SAMDxx one so
the change consists of adding the new part IDs. Unfortunately the
device ID logic had a couple of mistakes in it that did not affect
anything on SAMD2x devices (due to 0 values expected there) but that is
a problem on L21, it's therefore addressed here and things should now
match the datasheets.
Tested on Amtel SAML21 Xplained Pro development kit against the included
SAML21J18A there. Also tested for regressions on a SAMD20 and SAMD21
using their dev kits.
Change-Id: I768f75e064b8656c15148730dacaa4c3acfc4101
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2690
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
GP and EPOS EVMs do not provide xds100v2 on board,
rather they have a pin header which can be used
to attach any debug pod the user might want.
Change-Id: I61678c50900fbe0fab500ea42f85ecde7a490ded
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2618
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Works best after update to firmware v2.3.
Change-Id: Id2d3a0ae28bba014ee5338df9280fe39773c3398
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2570
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested with "J-Link Lite-XMC4000 Rev.1 compiled Dec 7 2012 19:23:07"
on XMC4500 Relax Lite Kit V1.
Change-Id: Ib680a444fa4cadbf640afba15d607c0e6bd4ab2c
Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2567
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for Texas Instruments AM437x
Industrial Development Kit support.
Change-Id: I33ed71c7392c3805a86cf2c8adce83c0e8aa323d
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2617
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
xds100v2 asks us to call these three commands to
guarantee proper behavior, so do it.
Change-Id: Iecf9c148ce7c2082ef915b46eeb511ceea395cc3
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2613
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
default already is jtag, but this silences a
warning during startup.
Change-Id: I94478327bbb259649500ef74a5b5c10d51e2a517
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2612
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Since the very first flash bank is already defined in target/kx.cfg,
there's no sense in repeating it.
Reported and tested by Richard Braun.
Change-Id: I417b7072b5e6675ddbf824446e7581b8b7da8f4b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2595
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Initial Support for AT91SAM7A2 on Olimex SAM7-LA2 board.
The board seems not to be able to reset into halted mode, as srst is
connected to NRESET of the cpu (configured srst_pulls_trst).
JTAG RCLK is connected to CLK.
Tested with interface/ftdi/olimex-arm-usb-ocd-h.cfg.
Change-Id: I2bdd67e3683e45f1119c5850bad294aa107891d8
Signed-off-by: Arne Wichmann <arne.wichmann@gmail.com>
Reviewed-on: http://openocd.zylin.com/2318
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The F334 disco board has a stlink V.2-1 as F3 nucleo boards. Normal F3 disco
boards use stlink v2 and can't ne used.
Change-Id: I77ebef93b184592f25ff18bb2da776d636f60ff0
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2434
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds configs for Alphascale asm9260t ARM based SoC and
Evaluation Kit based on this chip.
Change-Id: Id8d3a1ef204e3ae84540c2693e3d62650ba82f73
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2515
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The flash definition belongs in the target cfg. Add some working area
and suitable reset_config.
Make kx.cfg more similar to klx.cfg.
Disable rclk as it is dead slow and a fixed 1MHz clock seems to work.
Change-Id: I8328f179c3a33be64403da93616abb48651bdfe6
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2227
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add configs for Atheros ar9331 MIPS based WiSoC and
board based on this chip: TP-LINK TL-MR3020
Change-Id: I9e99719bce4bbb28311f6e9cddb32288db6e7b91
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2519
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Added support for the ST nucleo l152re board with a stm32l152ret6 MCU,
analog to st_nucleo_f* configurations.
Change-Id: Id2c61dc7a7cb2e1cc64442191b367bab4247bdeb
Signed-off-by: Thomas Eichinger <eicht@lepus.uberspace.de>
Reviewed-on: http://openocd.zylin.com/2489
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
It depends on the particular target whether it can work with SRST
asserted or not, so this belongs to the target config rather than the
board config.
Also, this allows for simple
openocd -f myboard.cfg -c "reset_config connect_assert_srst"
command to be used whenever a user feels a need to connect to an
unresponsive target.
Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2459
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
It is derived from ti_tmdx570ls31usb.cfg, using a different TAP ID.
Change-Id: I2d911995c76ea4f75a780cc230d61f4959825809
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2440
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
commit b5a6ba46 broke the following board files, update to new cfg.
Change-Id: Ic3b776bd32eb72eae6ad1e130e329268ce9ba71a
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2384
Tested-by: jenkins
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup. It has no endian options, no boundary scan.
Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.
Tested on STM32L053 Discovery and STM32L151 Discovery.
Has _not_ been tested with jtag on L1.
Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
this board use STLink-V2-1, the STM32L1xx use the STLink-V2.
Change-Id: Ie58f45affcb1e9a6fed711b48c3c03b5035ab2b2
Signed-off-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Reviewed-on: http://openocd.zylin.com/2317
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Remove this underutilized feature. Despite the fact that a lot of configs
specifies a arbitrary "variant", only the xscale target actually defines
any.
In the case of xscale, the use of -variant is dubious since
1) it's used as a redundant irlen specifier,
2) it carries a comment that it doesn't really need it and
3) only two xscale configs even specify it.
If there's a future target that needs a variant set, a target specific
option could be added when needed.
Change-Id: I1ba25a946f0d80872cbd96ddcc48f92695c4ae20
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2283
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This combination is known to work properly with 2MHz JTAG clock.
Change-Id: Ie5ec3d3b415efbb13faee7d34e0c7f862b78350c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2266
Tested-by: jenkins
Since now auto-detection for flash size works nicely, there's no
reason to keep numerous configs around.
Change-Id: If0cbc37985abf17ef7c1f7d0688e76500fac228f
Signed-off-by: Vanya Sergeev <vsergeev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1960
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This should allow to share common configs for both regular access and
high-level adapters.
Use the newly-added functionality in stlink and icdi drivers, amend
the configs accordingly.
Runtime-tested with a TI tm4c123g board.
Change-Id: Ibb88266a4ca25f06f6c073e916c963f017447bad
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
[gus@projectgus.com: context-specific deprecation warnings]
Signed-off-by: Angus Gratton <gus@projectgus.com>
[andrew.smirnov@gmail.com: additional nrf51.cfg mods]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1664
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The Atmel SAMR21 is a Atmel SAMD21 with an Atmel RF233 in one package (two
dies). Tested with the SAMR21 Xplained Pro eval kit.
Change-Id: I1d79ea05834b925d7ec810527206fe86854e684b
Signed-off-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-on: http://openocd.zylin.com/2194
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Gumstix AeroCore board [1] contains a STM32F427 microcontroller.
Schematics for this board will also be made available [2].
The JTAG interface for this chip can be accessed via a USB connection
provided by an FTDI chip (0403:6011).
[1] https://store.gumstix.com/index.php/products/585/
[2] https://pubs.gumstix.com/boards/AEROCORE
Change-Id: I0bf3bb525f51528bedd807b1f7210b09ef2e1015
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Reviewed-on: http://openocd.zylin.com/2117
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Also add the board to the firmware recovery script.
Change-Id: I4f9c895dae171df7249e3b1c0563b288518b9fe0
Signed-off-by: Lee Bowyer <lee@sodnpoo.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2097
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch allows users to specify TAP_TYPE from
the command line when using or1k_generic.cfg.
Change-Id: I9f4b7d8e4867658fa34bb4e92fc3a5f25227df11
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/2056
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This adds support for the am43xx SoC and the AM437x GP EVM and AM438x
ePOS EVM.
Change-Id: I09cbb09072f38e0e08fdd520dedb6e67d45056be
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2047
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reported and tested by Gracana on IRC.
Change-Id: If0524d2d627d566e8b5e1d00784dd7556f44b125
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2036
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add support for Broadcom's dual A9 mobile SoC and its reference board.
Change-Id: Ia145b120043bddc89c44726066023154ae390788
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-on: http://openocd.zylin.com/1926
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
flash: at91sam4: add support for the SAMG53 family (this also covers the
SAMG51). The SAMG5x parts have an EEFC (enhanced embedded flash controller)
which seems to be identical to the EFC that the sam4 driver supports.
Add a script for the Xplained Pro G53 board, this has the onboard CMSIS-DAP
debugger and a SAMG53N19. Tested on this board and chip combination.
Change-Id: I12af50402cd2069b3c7380d92e6fe54816d6c045
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1974
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Intel Quark X10xx SoC debug support added
Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC
Generic x86 32-bit code is in x86_32_common.c/h
Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368
Signed-off-by: adrian.burns@intel.com
Reviewed-on: http://openocd.zylin.com/1829
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested with SAMD21J18A on the SAMD21 Xplained Pro board.
Change-Id: Ice9ebcd229ed038b3193baf92d910f9256d7ce91
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1873
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
These kits feature a CMSIS-DAP compliant debugger and so have been added
as part of the pending support.
Currently the flash drivers for the L8 and D20 are wip.
One issue this implementation of CMSIS-DAP raised is that it supports
512byte HID reports, however using the current HIDAPI we have no cross platform
way of querying this info. Long term we plan to add this support to HIDAPI.
Change-Id: Ie8b7c871f58a099d963cd71a9f8a0105a38784e9
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1625
Tested-by: jenkins
This is based on work from:
https://github.com/TheShed/OpenOCD-CMSIS-DAP/tree/cmsis-dap
Main changes include moving over to using HIDAPI rather than libusb-1.0
and cleaning up to merge into master. Support for reset using srst has
also been added.
It has been tested on all the mbed boards as well as the Freedom board
from Freescale. These boards only implement SWD mode, however JTAG mode
has been tested with a Keil ULINK2 and a stm32 target - but requires a lot
more work.
Change-Id: I96d5ee1993bc9c0526219ab754c5aad3b55d812d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1542
Tested-by: jenkins
Tested flashing a real v1.1 device.
Change-Id: Ie0d202b9fded8b92e731d93e0ef17be415a75fc8
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1852
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds the bcm47xx config with the special undocumented trick to
put it into standard EJTAG mode from the mystic "LV mode".
The RAM setup is not done as it would require considerable efforts
without much practical gain.
The only issue I noticed so far is that "reset" doesn't actually reset
the chip.
Unfortunately, it's unclear how to make it work properly with SRST as
OpenOCD asserts it in MIPS-specific code so the device will enter LV
mode again but the LV tap is already disabled by that time, so it's
not possible to send the magic command again.
Anyway, this config is more than enough to "recover" any RT-N16
provided the hardware is not damaged.
Change-Id: I0894e339763e6d20d1c93341c597382b479d039b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1849
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.
Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick
development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and
reading and writing memory and registers.
Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1788
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Almost the same as the LM4F120 LaunchPad but the chip is using the new
naming scheme (Tiva C series), supports USB OTG and has some new PWM
hardware blocks.
Change-Id: I6a7b2df76768766471f366cddaf64df3cc63f5f2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1647
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for OpenRISC target. This implementation
supports the adv_debug_sys debug unit core. The mohor
dbg_if is not supported. Support for mohor TAP core
and Altera Virtual JTAG core are also provided.
Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1547
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
