2022-06-26 16:18:19 +00:00
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#include "stx7105.h"
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2022-09-07 14:12:54 +00:00
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#define WEAK_ATTR __attribute__((weak))
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#define IRQ_ATTR __attribute__((interrupt_handler))
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#define WEAK_IRQ_ATTR __attribute__((weak, interrupt_handler))
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2022-06-26 16:18:19 +00:00
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typedef enum {
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2022-09-07 15:11:11 +00:00
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EXP_TYPE_RADDERR = 0x0E0,
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EXP_TYPE_WADDERR = 0x100,
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EXP_TYPE_TRAP = 0x160,
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2022-06-26 16:18:19 +00:00
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} expevt_type_t;
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2022-08-07 03:35:45 +00:00
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typedef enum {
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2022-08-08 01:12:06 +00:00
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INT_TYPE_TMU_TNUI0 = 0x400,
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INT_TYPE_TMU_TNUI1 = 0x420,
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INT_TYPE_TMU_TNUI2 = 0x440,
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INT_TYPE_TMU_TICPI2 = 0x460,
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INT_TYPE_ASC_UART0 = 0x1160,
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INT_TYPE_ASC_UART1 = 0x1140,
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INT_TYPE_ASC_UART2 = 0x1120,
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INT_TYPE_ASC_UART3 = 0x1100,
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} intevt_type_t;
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typedef enum {
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2022-09-07 15:11:11 +00:00
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TRA_TYPE_START_SCHEDULER = 32,
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TRA_TYPE_YIELD = 33,
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TRA_TYPE_SYSCALL = 34,
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2022-06-26 16:18:19 +00:00
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} tra_type_t;
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2022-09-07 14:12:54 +00:00
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/* ========================= TMU 0/1/2 Underrun Interrupt Handlers ================================= */
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2022-06-26 16:18:19 +00:00
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2022-09-07 14:27:21 +00:00
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WEAK_ATTR void tuni0_handler(void) {
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2022-08-08 01:12:06 +00:00
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/* Does nothing */
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}
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2022-09-07 14:27:21 +00:00
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WEAK_ATTR void tuni1_handler(void) {
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/* Does nothing */
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}
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2022-09-07 14:27:21 +00:00
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WEAK_ATTR void tuni2_handler(void) {
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/* Does nothing */
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}
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/* ========================= ASC(UART) 0/1/2 Interrupt Handlers ================================= */
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2022-09-07 15:11:11 +00:00
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WEAK_ATTR void asc0_handler(void) {
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/* Does nothing */
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}
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WEAK_ATTR void asc1_handler(void) {
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/* Does nothing */
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}
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WEAK_ATTR void asc2_handler(void) {
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/* Does nothing */
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}
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WEAK_ATTR void asc3_handler(void) {
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/* Does nothing */
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}
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/* ========================= Different Trap Code Handlers ================================= */
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WEAK_ATTR void syscall_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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/* Does nothing */
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}
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WEAK_ATTR void yield_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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/* Does nothing */
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}
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2022-09-07 14:12:54 +00:00
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/* ========================= TRAPA(Trap) Exception Handlers ================================= */
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WEAK_ATTR void trap_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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tra_type_t tra = (CSP->TRA >> 2U) & 0xFFU; /* TRA[9:2] */
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switch (tra) {
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case TRA_TYPE_SYSCALL:
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syscall_handler(p1, p2, p3, p4);
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break;
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case TRA_TYPE_YIELD:
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yield_handler(p1, p2, p3, p4);
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break;
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default:
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break;
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}
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}
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2022-09-07 15:11:11 +00:00
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/* ========================= Address Error Exception Handlers ================================= */
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WEAK_ATTR void radderr_handler(void) {
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/* Dead... */
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for (;;) {
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/* Loop... */
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}
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}
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WEAK_ATTR void wadderr_handler(void) {
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/* Dead... */
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for (;;) {
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/* Loop... */
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}
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}
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2022-09-07 14:12:54 +00:00
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/* ========================= System Exception Handlers ================================= */
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WEAK_IRQ_ATTR void general_exc_handler(uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) {
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expevt_type_t expevt = CSP->EXPEVT;
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switch (expevt) {
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case EXP_TYPE_TRAP:
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trap_handler(p1, p2, p3, p4);
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break;
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case EXP_TYPE_RADDERR:
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radderr_handler();
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break;
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case EXP_TYPE_WADDERR:
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wadderr_handler();
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break;
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default:
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break;
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}
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}
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2022-09-07 14:12:54 +00:00
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/* ========================= System Interrupt Handlers ================================= */
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2022-09-07 14:27:21 +00:00
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WEAK_IRQ_ATTR void general_int_handler(void) {
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2022-09-04 11:47:08 +00:00
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intevt_type_t intevt = CSP->INTEVT;
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2022-08-08 01:12:06 +00:00
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switch (intevt) {
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case INT_TYPE_TMU_TNUI0:
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tuni0_handler();
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break;
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case INT_TYPE_TMU_TNUI1:
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tuni1_handler();
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break;
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case INT_TYPE_TMU_TNUI2:
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tuni2_handler();
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break;
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2022-09-07 15:11:11 +00:00
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case INT_TYPE_ASC_UART0:
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asc0_handler();
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break;
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case INT_TYPE_ASC_UART1:
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asc1_handler();
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break;
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case INT_TYPE_ASC_UART2:
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asc2_handler();
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break;
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case INT_TYPE_ASC_UART3:
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asc3_handler();
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break;
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2022-08-08 01:12:06 +00:00
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default:
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break;
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}
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}
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