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Updated FDMA related files.

This commit is contained in:
imi415 2022-09-04 19:43:35 +08:00
parent 029f336438
commit 650049d060
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
3 changed files with 32 additions and 14 deletions
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12
.clang-format Normal file
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@ -0,0 +1,12 @@
BasedOnStyle: Google
IndentWidth: 4
AlignConsecutiveMacros: Consecutive
AlignConsecutiveDeclarations: true
AlignConsecutiveAssignments: true
AllowShortFunctionsOnASingleLine: false
BreakBeforeBraces: Custom
BraceWrapping:
AfterEnum: false
AfterStruct: false
SplitEmptyFunction: false
ColumnLimit: 120

19
include/stx7105_fdma.h
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@ -25,21 +25,24 @@ typedef enum {
} FDMA_ReqCtl_Opcode_TypeDef;
typedef struct {
__IO uint32_t PTRN; /* Offset: 0x0000 */
uint32_t UNUSED2; /* Offset: 0x0004 */
__IO uint32_t CNTN; /* Offset: 0x0008 */
__IO uint32_t SADDRN; /* Offset: 0x000C */
__IO uint32_t DADDRN; /* Offset: 0x0010 */
__IO uint32_t NEXT; /* Offset: 0x0000, Next node in the list */
__IO uint32_t CTRL; /* Offset: 0x0004, Control register */
__IO uint32_t NBYTES; /* Offset: 0x0008, Number of bytes */
__IO uint32_t SADDR; /* Offset: 0x000C, Source address */
__IO uint32_t DADDR; /* Offset: 0x0010, Destination address */
__IO uint32_t LENGTH; /* Offset: 0x0014, Burst length */
__IO uint32_t S_STRIDE; /* Offset: 0x0018, Source stride */
__IO uint32_t D_STRIDE; /* Offset: 0x001C, Destination stride */
} FDMA_FwRegs_Channel_TypeDef;
/* Firmware regs, implemented on the base of DMEM */
typedef struct {
__IO uint32_t REVID; /* Offset: 0x8000 */
uint32_t UNUSED0[1103]; /* Offset: 0x8004 */
__IO uint32_t CMD_STATN[16]; /* Offset: 0x9140 */
__IO uint32_t REQ_CTLN[16]; /* Offset: 0x9180 */
__IO uint32_t CMD_STAT[16]; /* Offset: 0x9140 */
__IO uint32_t REQ_CTRL[16]; /* Offset: 0x9180 */
uint32_t UNUSED1[240]; /* Offset: 0x91C0 */
FDMA_FwRegs_Channel_TypeDef CHANNELN[16]; /* Offset: 0x9580 */
FDMA_FwRegs_Channel_TypeDef CHANNEL[16]; /* Offset: 0x9580 */
} FDMA_FWRegs_TypeDef;
#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_Pos 0U

15
src/main.c
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@ -21,9 +21,8 @@
#define MEMTEST_START 0x82000000
#define MEMTEST_END 0x8F000000
#define DMA_BUFFER_SIZE 1024
#define DMA_BUFFER_SIZE 16
uint8_t src_buffer[DMA_BUFFER_SIZE];
uint8_t dst_buffer[DMA_BUFFER_SIZE];
void uart_init(void) {
PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */
@ -103,10 +102,14 @@ int main(void) {
FDMA_FWRegs_TypeDef *fdma0_fwregs = (FDMA_FWRegs_TypeDef *)(FDMA0->SLIM_DMEM);
fdma0_fwregs->CHANNELN[0].CNTN = DMA_BUFFER_SIZE;
fdma0_fwregs->CHANNELN[0].SADDRN = src_buffer;
fdma0_fwregs->CHANNELN[0].DADDRN = dst_buffer;
fdma0_fwregs->REQ_CTLN[0] =
fdma0_fwregs->CHANNEL[0].NEXT = (uint32_t)NULL;
fdma0_fwregs->CHANNEL[0].NBYTES = DMA_BUFFER_SIZE;
fdma0_fwregs->CHANNEL[0].LENGTH = DMA_BUFFER_SIZE;
fdma0_fwregs->CHANNEL[0].SADDR = (uint32_t)src_buffer;
fdma0_fwregs->CHANNEL[0].DADDR = CONSOLE_ASC->TX_BUF;
fdma0_fwregs->CHANNEL[0].S_STRIDE = 0U;
fdma0_fwregs->CHANNEL[0].D_STRIDE = 0U;
fdma0_fwregs->REQ_CTRL[0] = (1U << FDMA_FwRegs_REQ_CTLN_NUM_OPS_Pos) | FDMA_FwRegs_REQ_CTLN_INC_ADDR_Msk;
delay_ms(5000);