Updated FDMA related files.
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BasedOnStyle: Google
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AlignConsecutiveMacros: Consecutive
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AlignConsecutiveDeclarations: true
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AlignConsecutiveAssignments: true
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AllowShortFunctionsOnASingleLine: false
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BreakBeforeBraces: Custom
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BraceWrapping:
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AfterEnum: false
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AfterStruct: false
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SplitEmptyFunction: false
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ColumnLimit: 120
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@ -25,21 +25,24 @@ typedef enum {
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} FDMA_ReqCtl_Opcode_TypeDef;
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} FDMA_ReqCtl_Opcode_TypeDef;
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typedef struct {
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typedef struct {
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__IO uint32_t PTRN; /* Offset: 0x0000 */
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__IO uint32_t NEXT; /* Offset: 0x0000, Next node in the list */
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uint32_t UNUSED2; /* Offset: 0x0004 */
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__IO uint32_t CTRL; /* Offset: 0x0004, Control register */
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__IO uint32_t CNTN; /* Offset: 0x0008 */
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__IO uint32_t NBYTES; /* Offset: 0x0008, Number of bytes */
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__IO uint32_t SADDRN; /* Offset: 0x000C */
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__IO uint32_t SADDR; /* Offset: 0x000C, Source address */
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__IO uint32_t DADDRN; /* Offset: 0x0010 */
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__IO uint32_t DADDR; /* Offset: 0x0010, Destination address */
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__IO uint32_t LENGTH; /* Offset: 0x0014, Burst length */
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__IO uint32_t S_STRIDE; /* Offset: 0x0018, Source stride */
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__IO uint32_t D_STRIDE; /* Offset: 0x001C, Destination stride */
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} FDMA_FwRegs_Channel_TypeDef;
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} FDMA_FwRegs_Channel_TypeDef;
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/* Firmware regs, implemented on the base of DMEM */
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/* Firmware regs, implemented on the base of DMEM */
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typedef struct {
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typedef struct {
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__IO uint32_t REVID; /* Offset: 0x8000 */
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__IO uint32_t REVID; /* Offset: 0x8000 */
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uint32_t UNUSED0[1103]; /* Offset: 0x8004 */
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uint32_t UNUSED0[1103]; /* Offset: 0x8004 */
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__IO uint32_t CMD_STATN[16]; /* Offset: 0x9140 */
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__IO uint32_t CMD_STAT[16]; /* Offset: 0x9140 */
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__IO uint32_t REQ_CTLN[16]; /* Offset: 0x9180 */
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__IO uint32_t REQ_CTRL[16]; /* Offset: 0x9180 */
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uint32_t UNUSED1[240]; /* Offset: 0x91C0 */
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uint32_t UNUSED1[240]; /* Offset: 0x91C0 */
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FDMA_FwRegs_Channel_TypeDef CHANNELN[16]; /* Offset: 0x9580 */
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FDMA_FwRegs_Channel_TypeDef CHANNEL[16]; /* Offset: 0x9580 */
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} FDMA_FWRegs_TypeDef;
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} FDMA_FWRegs_TypeDef;
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#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_Pos 0U
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#define FDMA_FwRegs_REQ_CTLN_HOLDOFF_Pos 0U
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15
src/main.c
15
src/main.c
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@ -21,9 +21,8 @@
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#define MEMTEST_START 0x82000000
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#define MEMTEST_START 0x82000000
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#define MEMTEST_END 0x8F000000
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#define MEMTEST_END 0x8F000000
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#define DMA_BUFFER_SIZE 1024
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#define DMA_BUFFER_SIZE 16
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uint8_t src_buffer[DMA_BUFFER_SIZE];
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uint8_t src_buffer[DMA_BUFFER_SIZE];
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uint8_t dst_buffer[DMA_BUFFER_SIZE];
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void uart_init(void) {
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void uart_init(void) {
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PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */
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PIO4->CLR_PC0 = 1U; /* PC = 110, AFOUT, PP */
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@ -103,10 +102,14 @@ int main(void) {
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FDMA_FWRegs_TypeDef *fdma0_fwregs = (FDMA_FWRegs_TypeDef *)(FDMA0->SLIM_DMEM);
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FDMA_FWRegs_TypeDef *fdma0_fwregs = (FDMA_FWRegs_TypeDef *)(FDMA0->SLIM_DMEM);
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fdma0_fwregs->CHANNELN[0].CNTN = DMA_BUFFER_SIZE;
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fdma0_fwregs->CHANNEL[0].NEXT = (uint32_t)NULL;
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fdma0_fwregs->CHANNELN[0].SADDRN = src_buffer;
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fdma0_fwregs->CHANNEL[0].NBYTES = DMA_BUFFER_SIZE;
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fdma0_fwregs->CHANNELN[0].DADDRN = dst_buffer;
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fdma0_fwregs->CHANNEL[0].LENGTH = DMA_BUFFER_SIZE;
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fdma0_fwregs->REQ_CTLN[0] =
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fdma0_fwregs->CHANNEL[0].SADDR = (uint32_t)src_buffer;
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fdma0_fwregs->CHANNEL[0].DADDR = CONSOLE_ASC->TX_BUF;
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fdma0_fwregs->CHANNEL[0].S_STRIDE = 0U;
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fdma0_fwregs->CHANNEL[0].D_STRIDE = 0U;
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fdma0_fwregs->REQ_CTRL[0] = (1U << FDMA_FwRegs_REQ_CTLN_NUM_OPS_Pos) | FDMA_FwRegs_REQ_CTLN_INC_ADDR_Msk;
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delay_ms(5000);
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delay_ms(5000);
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