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target: add generic Xtensa LX support 

Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file.  Not yet fully-featured.  Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support

Valgrind-clean, no new Clang analyzer warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ian Thompson 2022-06-24 22:27:32 -07:00 committed by Antonio Borneo
parent be2e5c6c35
commit ce5ca9f7ba
25 changed files with 3589 additions and 1800 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

161
doc/openocd.texi
View File

@ -4906,6 +4906,7 @@ And two debug interfaces cores:
@item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
@item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core.
@end itemize
@end deffn
@ -10935,33 +10936,150 @@ OpenOCD supports debugging STM8 through the STMicroelectronics debug
protocol SWIM, @pxref{swimtransport,,SWIM}.
@section Xtensa Architecture
Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
that can easily scale from a tiny, cache-less controller or task engine to a high-performance
SIMD/VLIW DSP provided by Cadence.
@url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
OpenOCD supports generic Xtensa processors implementation which can be customized by
simply providing vendor-specific core configuration which controls every configurable
Xtensa is a highly-customizable, user-extensible microprocessor and DSP
architecture for complex embedded systems provided by Cadence Design
Systems, Inc. See the
@uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP}
website for additional information and documentation.
OpenOCD supports generic Xtensa processor implementations which can be customized by
providing a core-specific configuration file which describes every enabled
Xtensa architecture option, e.g. number of address registers, exceptions, reduced
size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
configurations for Xtensa processors with any number of cores and allows to configure
their debug signals interconnection (so-called "break/stall networks") which control how
debug signals are distributed among cores. Xtensa "break networks" are compatible with
ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
size instructions support, memory banks configuration etc. OpenOCD also supports SMP
configurations for Xtensa processors with any number of cores and allows configuring
their debug interconnect (termed "break/stall networks"), which control how debug
signals are distributed among cores. Xtensa "break networks" are compatible with
ARM's Cross Trigger Interface (CTI). OpenOCD implements both generic Xtensa targets
as well as several Espressif Xtensa-based chips from the
@uref{https://www.espressif.com/en/products/socs, ESP32 family}.
@subsection General Xtensa Commands
OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa
Debug Module (XDM), which provides external connectivity either through a
traditional JTAG interface or an ARM DAP interface. If used, the DAP interface
can control Xtensa targets through JTAG or SWD probes.
@subsection Xtensa Core Configuration
Due to the high level of configurability in Xtensa cores, the Xtensa target
configuration comprises two categories:
@enumerate
@item Base Xtensa support common to all core configurations, and
@item Core-specific support as configured for individual cores.
@end enumerate
All common Xtensa support is built into the OpenOCD Xtensa target layer and
is enabled through a combination of TCL scripts: the target-specific
@file{target/xtensa.cfg} and a board-specific @file{board/xtensa-*.cfg},
similar to other target architectures.
Importantly, core-specific configuration information must be provided by
the user, and takes the form of an @file{xtensa-core-XXX.cfg} TCL script that
defines the core's configurable features through a series of Xtensa
configuration commands (detailed below).
This core-specific @file{xtensa-core-XXX.cfg} file is typically either:
@itemize @bullet
@item Located within the Xtensa core configuration build as
@file{src/config/xtensa-core-openocd.cfg}, or
@item Generated by running the command @code{xt-gdb --dump-oocd-config}
from the Xtensa processor tool-chain's command-line tools.
@end itemize
NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
connected to OpenOCD.
Some example Xtensa configurations are bundled with OpenOCD for reference:
@itemize @bullet
@item Cadence Palladium VDebug emulation target. The user can combine their
@file{xtensa-core-XXX.cfg} with the provided
@file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are
@file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}.
Additional information is provided by
@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
NXP}.
@end itemize
@subsection Xtensa Configuration Commands
@deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
Configure the Xtensa target architecture. Currently, Xtensa support is limited
to LX6, LX7, and NX cores.
@end deffn
@deffn {Command} {xtensa xtopt} option value
Configure Xtensa target options that are relevant to the debug subsystem.
@var{option} is one of: @option{arnum}, @option{windowed},
@option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
@option{excmlevel}, @option{intlevels}, @option{debuglevel},
@option{ibreaknum}, or @option{dbreaknum}. @var{value} is an integer with
the exact range determined by each particular option.
NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
others may be common to both but have different valid ranges.
@end deffn
@deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
Configure Xtensa target memory. Memory type determines access rights,
where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
@var{bytes} are both integers, typically hexadecimal and decimal, respectively.
@end deffn
@deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
Configure Xtensa processor cache. All parameters are required except for
the optional @option{writeback} parameter; all are integers.
@end deffn
@deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
and/or control cacheability of specific address ranges, but are lighter-weight
than a full traditional MMU. All parameters are required; all are integers.
@end deffn
@deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
(Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
parameters are required; both are integers.
@end deffn
@deffn {Command} {xtensa xtregs} numregs
Configure the total number of registers for the Xtensa core. Configuration
logic expects to subsequently process this number of @code{xtensa xtreg}
definitions. @var{numregs} is an integer.
@end deffn
@deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
Configure the type of register map used by GDB to access the Xtensa core.
Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
additional, optional integer parameter @option{numgregs}, which specifies the number
of general registers used in handling g/G packets.
@end deffn
@deffn {Command} {xtensa xtreg} name offset
Configure an Xtensa core register. All core registers are 32 bits wide,
while TIE and user registers may have variable widths. @var{name} is a
character string identifier while @var{offset} is a hexadecimal integer.
@end deffn
@subsection Xtensa Operation Commands
@deffn {Command} {xtensa maskisr} (@option{on}|@option{off})
(Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step.
When masked, an interrupt that occurs during a step operation is handled and
its ISR is executed, with the user's debug session returning after potentially
executing many instructions. When unmasked, a triggered interrupt will result
in execution progressing the requested number of instructions into the relevant
vector/ISR code.
@end deffn
@deffn {Command} {xtensa set_permissive} (0|1)
By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
When set to (1), skips access controls and address range check before read/write memory.
@end deffn
@deffn {Command} {xtensa maskisr} (on|off)
Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
@end deffn
@deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
Configures debug signals connection ("break network") for currently selected core.
@itemize @bullet
@ -10985,6 +11103,13 @@ This feature is not well implemented and tested yet.
@end itemize
@end deffn
@deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
Execute arbitrary instruction(s) provided as an ascii string. The string represents an integer
number of instruction bytes, thus its length must be even.
@end deffn
@subsection Xtensa Performance Monitor Configuration
@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
Enable and start performance counter.
@itemize @bullet
@ -11004,6 +11129,8 @@ whether to count.
Dump performance counter value. If no argument specified, dumps all counters.
@end deffn
@subsection Xtensa Trace Configuration
@deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
This command also allows to specify the amount of data to capture after stop trigger activation.

5
src/target/espressif/Makefile.am
View File

@ -7,8 +7,5 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
%D%/esp32.c \
%D%/esp32.h \
%D%/esp32s2.c \
%D%/esp32s2.h \
%D%/esp32s3.c \
%D%/esp32s3.h
%D%/esp32s3.c

205
src/target/espressif/esp32.c
View File

@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
#include "esp32.h"
#include "esp_xtensa_smp.h"
/*
@ -70,204 +69,6 @@ implementation.
#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
*xtensa-overlay */
static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = {
XT_REG_IDX_PC,
XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
ESP32_REG_IDX_EXPSTATE,
ESP32_REG_IDX_F64R_LO,
ESP32_REG_IDX_F64R_HI,
ESP32_REG_IDX_F64S,
XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
};
static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = {
{ "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type },
{ "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type },
{ "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type },
{ "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type },
};
static const struct xtensa_config esp32_xtensa_cfg = {
.density = true,
.aregs_num = XT_AREGS_NUM_MAX,
.windowed = true,
.coproc = true,
.fp_coproc = true,
.loop = true,
.miscregs_num = 4,
.threadptr = true,
.boolean = true,
.reloc_vec = true,
.proc_id = true,
.cond_store = true,
.mac16 = true,
.user_regs_num = ARRAY_SIZE(esp32_user_regs),
.user_regs = esp32_user_regs,
.fetch_user_regs = xtensa_fetch_user_regs_u32,
.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
.gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND,
.gdb_regs_mapping = esp32_gdb_regs_mapping,
.irom = {
.count = 2,
.regions = {
{
.base = ESP32_IROM_LOW,
.size = ESP32_IROM_HIGH - ESP32_IROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_IROM_MASK_LOW,
.size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.iram = {
.count = 2,
.regions = {
{
.base = ESP32_IRAM_LOW,
.size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_RTC_IRAM_LOW,
.size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.drom = {
.count = 1,
.regions = {
{
.base = ESP32_DROM_LOW,
.size = ESP32_DROM_HIGH - ESP32_DROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.dram = {
.count = 6,
.regions = {
{
.base = ESP32_DRAM_LOW,
.size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_RTC_DRAM_LOW,
.size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_RTC_DATA_LOW,
.size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_EXTRAM_DATA_LOW,
.size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_DR_REG_LOW,
.size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_SYS_RAM_LOW,
.size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.exc = {
.enabled = true,
},
.irq = {
.enabled = true,
.irq_num = 32,
},
.high_irq = {
.enabled = true,
.excm_level = 3,
.nmi_num = 1,
},
.tim_irq = {
.enabled = true,
.comp_num = 3,
},
.debug = {
.enabled = true,
.irq_level = 6,
.ibreaks_num = 2,
.dbreaks_num = 2,
.icount_sz = 32,
},
.trace = {
.enabled = true,
.mem_sz = ESP32_TRACEMEM_BLOCK_SZ,
.reversed_mem_access = true,
},
};
/* 0 - don't care, 1 - TMS low, 2 - TMS high */
enum esp32_flash_bootstrap {
FBS_DONTCARE = 0,
@ -401,7 +202,8 @@ static int esp32_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
target->state);
get_timeout = true;
break;
}
@ -481,7 +283,6 @@ static int esp32_virt2phys(struct target *target,
return ERROR_FAIL;
}
/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
* can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
* esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
@ -544,7 +345,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg,
int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
&esp32_dm_cfg, &esp32_chip_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");

31
src/target/espressif/esp32.h
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@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* ESP32 target for OpenOCD *
* Copyright (C) 2017 Espressif Systems Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32_H
#define OPENOCD_TARGET_ESP32_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_DROM_LOW 0x3F400000
#define ESP32_DROM_HIGH 0x3F800000
#define ESP32_IROM_LOW 0x400D0000
#define ESP32_IROM_HIGH 0x40400000
/* Number of registers returned directly by the G command
* Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_NUM_REGS_G_COMMAND 105
enum esp32_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START,
ESP32_REG_IDX_F64R_LO,
ESP32_REG_IDX_F64R_HI,
ESP32_REG_IDX_F64S,
ESP32_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32_H */

196
src/target/espressif/esp32s2.c
View File

@ -14,7 +14,6 @@
#include <target/target.h>
#include <target/target_type.h>
#include "esp_xtensa.h"
#include "esp32s2.h"
/* Overall memory map
* TODO: read memory configuration from target registers */
@ -89,190 +88,6 @@
#define ESP32_S2_DR_REG_UART_BASE 0x3f400000
#define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
#define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
* xtensa-overlay */
static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = {
XT_REG_IDX_PC,
XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
XT_REG_IDX_SAR,
XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS, XT_REG_IDX_THREADPTR,
ESP32_S2_REG_IDX_GPIOOUT,
XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR,
XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
};
static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = {
{ "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
};
static const struct xtensa_config esp32s2_xtensa_cfg = {
.density = true,
.aregs_num = XT_AREGS_NUM_MAX,
.windowed = true,
.coproc = true,
.miscregs_num = 4,
.reloc_vec = true,
.proc_id = true,
.threadptr = true,
.user_regs_num = ARRAY_SIZE(esp32s2_user_regs),
.user_regs = esp32s2_user_regs,
.fetch_user_regs = xtensa_fetch_user_regs_u32,
.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
.gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND,
.gdb_regs_mapping = esp32s2_gdb_regs_mapping,
.irom = {
.count = 2,
.regions = {
{
.base = ESP32_S2_IROM_LOW,
.size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_S2_IROM_MASK_LOW,
.size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.iram = {
.count = 2,
.regions = {
{
.base = ESP32_S2_IRAM_LOW,
.size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_RTC_IRAM_LOW,
.size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.drom = {
.count = 2,
.regions = {
{
.base = ESP32_S2_DROM0_LOW,
.size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_S2_DROM1_LOW,
.size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.dram = {
.count = 6,
.regions = {
{
.base = ESP32_S2_DRAM_LOW,
.size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_RTC_DRAM_LOW,
.size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_RTC_DATA_LOW,
.size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_EXTRAM_DATA_LOW,
.size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_DR_REG_LOW,
.size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_SYS_RAM_LOW,
.size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.exc = {
.enabled = true,
},
.irq = {
.enabled = true,
.irq_num = 32,
},
.high_irq = {
.enabled = true,
.excm_level = 3,
.nmi_num = 1,
},
.tim_irq = {
.enabled = true,
.comp_num = 3,
},
.debug = {
.enabled = true,
.irq_level = 6,
.ibreaks_num = 2,
.dbreaks_num = 2,
.icount_sz = 32,
},
.trace = {
.enabled = true,
.mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ,
},
};
struct esp32s2_common {
struct esp_xtensa_common esp_xtensa;
};
@ -313,7 +128,7 @@ int esp32s2_soft_reset_halt(struct target *target)
int res = esp32s2_soc_reset(target);
if (res != ERROR_OK)
return res;
return xtensa_assert_reset(target);
return xtensa_soft_reset_halt(target);
}
static int esp32s2_set_peri_reg_mask(struct target *target,
@ -476,7 +291,8 @@ static int esp32s2_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
target->state);
return ERROR_TARGET_TIMEOUT;
}
}
@ -638,7 +454,7 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg);
int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@ -653,10 +469,6 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
static const struct command_registration esp32s2_command_handlers[] = {
{
.name = "xtensa",
.mode = COMMAND_ANY,
.help = "Xtensa commands group",
.usage = "",
.chain = xtensa_command_handlers,
},
COMMAND_REGISTRATION_DONE

28
src/target/espressif/esp32s2.h
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* ESP32-S2 target for OpenOCD *
* Copyright (C) 2019 Espressif Systems Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32S2_H
#define OPENOCD_TARGET_ESP32S2_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_S2_DROM_LOW 0x3f000000
#define ESP32_S2_DROM_HIGH 0x3ff80000
#define ESP32_S2_IROM_LOW 0x40080000
#define ESP32_S2_IROM_HIGH 0x40800000
/* Number of registers returned directly by the G command
* Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_S2_NUM_REGS_G_COMMAND 72
enum esp32s2_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_S2_REG_IDX_GPIOOUT = XT_USR_REG_START,
ESP32_S2_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32S2_H */

239
src/target/espressif/esp32s3.c
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@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
#include "esp32s3.h"
#include "esp_xtensa_smp.h"
/*
@ -75,246 +74,10 @@ implementation.
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
*xtensa-overlay */
static const unsigned int esp32s3_gdb_regs_mapping[ESP32_S3_NUM_REGS] = {
XT_REG_IDX_PC,
XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
ESP32_S3_REG_IDX_GPIOOUT,
XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
XT_REG_IDX_FCR, XT_REG_IDX_FSR,
ESP32_S3_REG_IDX_ACCX_0, ESP32_S3_REG_IDX_ACCX_1,
ESP32_S3_REG_IDX_QACC_H_0, ESP32_S3_REG_IDX_QACC_H_1, ESP32_S3_REG_IDX_QACC_H_2,
ESP32_S3_REG_IDX_QACC_H_3, ESP32_S3_REG_IDX_QACC_H_4,
ESP32_S3_REG_IDX_QACC_L_0, ESP32_S3_REG_IDX_QACC_L_1, ESP32_S3_REG_IDX_QACC_L_2,
ESP32_S3_REG_IDX_QACC_L_3, ESP32_S3_REG_IDX_QACC_L_4,
ESP32_S3_REG_IDX_SAR_BYTE, ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
ESP32_S3_REG_IDX_UA_STATE_0, ESP32_S3_REG_IDX_UA_STATE_1, ESP32_S3_REG_IDX_UA_STATE_2,
ESP32_S3_REG_IDX_UA_STATE_3,
ESP32_S3_REG_IDX_Q0, ESP32_S3_REG_IDX_Q1, ESP32_S3_REG_IDX_Q2, ESP32_S3_REG_IDX_Q3,
ESP32_S3_REG_IDX_Q4, ESP32_S3_REG_IDX_Q5, ESP32_S3_REG_IDX_Q6, ESP32_S3_REG_IDX_Q7,
XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
};
/* actually this table contains user + TIE registers
* TODO: for TIE registers we need to specify custom access functions instead of `xtensa_user_reg_xxx_type`*/
static const struct xtensa_user_reg_desc esp32s3_user_regs[ESP32_S3_NUM_REGS - XT_NUM_REGS] = {
{ "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
{ "accx_0", 0x01, 0, 32, &xtensa_user_reg_u32_type },
{ "accx_1", 0x02, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_0", 0x03, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_1", 0x04, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_2", 0x05, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_3", 0x06, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_4", 0x07, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_0", 0x08, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_1", 0x09, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_2", 0x0A, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_3", 0x0B, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_4", 0x0C, 0, 32, &xtensa_user_reg_u32_type },
{ "sar_byte", 0x0D, 0, 32, &xtensa_user_reg_u32_type },
{ "fft_bit_width", 0x0E, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_0", 0x0F, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_1", 0x10, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_2", 0x11, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_3", 0x12, 0, 32, &xtensa_user_reg_u32_type },
{ "q0", 0x13, 0, 128, &xtensa_user_reg_u128_type },
{ "q1", 0x14, 0, 128, &xtensa_user_reg_u128_type },
{ "q2", 0x15, 0, 128, &xtensa_user_reg_u128_type },
{ "q3", 0x16, 0, 128, &xtensa_user_reg_u128_type },
{ "q4", 0x17, 0, 128, &xtensa_user_reg_u128_type },
{ "q5", 0x18, 0, 128, &xtensa_user_reg_u128_type },
{ "q6", 0x19, 0, 128, &xtensa_user_reg_u128_type },
{ "q7", 0x20, 0, 128, &xtensa_user_reg_u128_type },
};
struct esp32s3_common {
struct esp_xtensa_smp_common esp_xtensa_smp;
};
static int esp32s3_fetch_user_regs(struct target *target);
static int esp32s3_queue_write_dirty_user_regs(struct target *target);
static const struct xtensa_config esp32s3_xtensa_cfg = {
.density = true,
.aregs_num = XT_AREGS_NUM_MAX,
.windowed = true,
.coproc = true,
.fp_coproc = true,
.loop = true,
.miscregs_num = 4,
.threadptr = true,
.boolean = true,
.reloc_vec = true,
.proc_id = true,
.cond_store = true,
.mac16 = true,
.user_regs_num = ARRAY_SIZE(esp32s3_user_regs),
.user_regs = esp32s3_user_regs,
.fetch_user_regs = esp32s3_fetch_user_regs,
.queue_write_dirty_user_regs = esp32s3_queue_write_dirty_user_regs,
.gdb_general_regs_num = ESP32_S3_NUM_REGS_G_COMMAND,
.gdb_regs_mapping = esp32s3_gdb_regs_mapping,
.irom = {
.count = 2,
.regions = {
{
.base = ESP32_S3_IROM_LOW,
.size = ESP32_S3_IROM_HIGH - ESP32_S3_IROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_S3_IROM_MASK_LOW,
.size = ESP32_S3_IROM_MASK_HIGH - ESP32_S3_IROM_MASK_LOW,
.access = XT_MEM_ACCESS_READ,
}
}
},
.iram = {
.count = 2,
.regions = {
{
.base = ESP32_S3_IRAM_LOW,
.size = ESP32_S3_IRAM_HIGH - ESP32_S3_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_RTC_IRAM_LOW,
.size = ESP32_S3_RTC_IRAM_HIGH - ESP32_S3_RTC_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.drom = {
.count = 1,
.regions = {
{
.base = ESP32_S3_DROM_LOW,
.size = ESP32_S3_DROM_HIGH - ESP32_S3_DROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.dram = {
.count = 4,
.regions = {
{
.base = ESP32_S3_DRAM_LOW,
.size = ESP32_S3_DRAM_HIGH - ESP32_S3_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_RTC_DRAM_LOW,
.size = ESP32_S3_RTC_DRAM_HIGH - ESP32_S3_RTC_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_RTC_DATA_LOW,
.size = ESP32_S3_RTC_DATA_HIGH - ESP32_S3_RTC_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_SYS_RAM_LOW,
.size = ESP32_S3_SYS_RAM_HIGH - ESP32_S3_SYS_RAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.exc = {
.enabled = true,
},
.irq = {
.enabled = true,
.irq_num = 32,
},
.high_irq = {
.enabled = true,
.excm_level = 3,
.nmi_num = 1,
},
.tim_irq = {
.enabled = true,
.comp_num = 3,
},
.debug = {
.enabled = true,
.irq_level = 6,
.ibreaks_num = 2,
.dbreaks_num = 2,
.icount_sz = 32,
},
.trace = {
.enabled = true,
.mem_sz = ESP32_S3_TRACEMEM_BLOCK_SZ,
},
};
static int esp32s3_fetch_user_regs(struct target *target)
{
LOG_DEBUG("%s: user regs fetching is not implemented!", target_name(target));
return ERROR_OK;
}
static int esp32s3_queue_write_dirty_user_regs(struct target *target)
{
LOG_DEBUG("%s: user regs writing is not implemented!", target_name(target));
return ERROR_OK;
}
/* Reset ESP32-S3's peripherals.
* 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
* If that fails, tries to reset it (via OCD) and then halt.
@ -537,7 +300,6 @@ static int esp32s3_virt2phys(struct target *target,
return ERROR_FAIL;
}
static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
{
return esp_xtensa_target_init(cmd_ctx, target);
@ -577,7 +339,6 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
int ret = esp_xtensa_smp_init_arch_info(target,
&esp32s3->esp_xtensa_smp,
&esp32s3_xtensa_cfg,
&esp32s3_dm_cfg,
&esp32s3_chip_ops);
if (ret != ERROR_OK) {

54
src/target/espressif/esp32s3.h
View File

@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* ESP32-S3 target for OpenOCD *
* Copyright (C) 2020 Espressif Systems Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32S3_H
#define OPENOCD_TARGET_ESP32S3_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_S3_DROM_LOW 0x3C000000
#define ESP32_S3_DROM_HIGH 0x3D000000
#define ESP32_S3_IROM_LOW 0x42000000
#define ESP32_S3_IROM_HIGH 0x44000000
/*Number of registers returned directly by the G command
*Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_S3_NUM_REGS_G_COMMAND 128
enum esp32s3_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
ESP32_S3_REG_IDX_ACCX_0,
ESP32_S3_REG_IDX_ACCX_1,
ESP32_S3_REG_IDX_QACC_H_0,
ESP32_S3_REG_IDX_QACC_H_1,
ESP32_S3_REG_IDX_QACC_H_2,
ESP32_S3_REG_IDX_QACC_H_3,
ESP32_S3_REG_IDX_QACC_H_4,
ESP32_S3_REG_IDX_QACC_L_0,
ESP32_S3_REG_IDX_QACC_L_1,
ESP32_S3_REG_IDX_QACC_L_2,
ESP32_S3_REG_IDX_QACC_L_3,
ESP32_S3_REG_IDX_QACC_L_4,
ESP32_S3_REG_IDX_SAR_BYTE,
ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
ESP32_S3_REG_IDX_UA_STATE_0,
ESP32_S3_REG_IDX_UA_STATE_1,
ESP32_S3_REG_IDX_UA_STATE_2,
ESP32_S3_REG_IDX_UA_STATE_3,
ESP32_S3_REG_IDX_Q0,
ESP32_S3_REG_IDX_Q1,
ESP32_S3_REG_IDX_Q2,
ESP32_S3_REG_IDX_Q3,
ESP32_S3_REG_IDX_Q4,
ESP32_S3_REG_IDX_Q5,
ESP32_S3_REG_IDX_Q6,
ESP32_S3_REG_IDX_Q7,
ESP32_S3_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32S3_H */

3
src/target/espressif/esp_xtensa.c
View File

@ -17,10 +17,9 @@
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg)
{
return xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg);
return xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg);
}
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)

1
src/target/espressif/esp_xtensa.h
View File

@ -23,7 +23,6 @@ static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *targ
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg);
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
void esp_xtensa_target_deinit(struct target *target);

192
src/target/espressif/esp_xtensa_smp.c
View File

@ -450,11 +450,10 @@ int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *w
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops)
{
int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg);
int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg);
if (ret != ERROR_OK)
return ret;
esp_xtensa_smp->chip_ops = chip_ops;
@ -467,6 +466,139 @@ int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *t
return esp_xtensa_target_init(cmd_ctx, target);
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode)
{
struct target *target = get_current_target(CMD_CTX);
@ -632,6 +764,62 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump)
}
const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = {
{
.name = "xtdef",
.handler = esp_xtensa_smp_cmd_xtdef,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa core type",
.usage = "<type>",
},
{
.name = "xtopt",
.handler = esp_xtensa_smp_cmd_xtopt,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa core option",
.usage = "<name> <value>",
},
{
.name = "xtmem",
.handler = esp_xtensa_smp_cmd_xtmem,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa memory/cache option",
.usage = "<type> [parameters]",
},
{
.name = "xtmmu",
.handler = esp_xtensa_smp_cmd_xtmmu,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa MMU option",
.usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>",
},
{
.name = "xtmpu",
.handler = esp_xtensa_smp_cmd_xtmpu,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa MPU option",
.usage = "<num FG seg> <min seg size> <lockable> <executeonly>",
},
{
.name = "xtreg",
.handler = esp_xtensa_smp_cmd_xtreg,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa register",
.usage = "<regname> <regnum>",
},
{
.name = "xtregs",
.handler = esp_xtensa_smp_cmd_xtreg,
.mode = COMMAND_CONFIG,
.help = "Configure number of Xtensa registers",
.usage = "<numregs>",
},
{
.name = "xtregfmt",
.handler = esp_xtensa_smp_cmd_xtregfmt,
.mode = COMMAND_CONFIG,
.help = "Configure format of Xtensa register map",
.usage = "<numgregs>",
},
{
.name = "set_permissive",
.handler = esp_xtensa_smp_cmd_permissive_mode,

1
src/target/espressif/esp_xtensa_smp.h
View File

@ -43,7 +43,6 @@ int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target);
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops);

2
src/target/target.c
View File

@ -77,6 +77,7 @@ extern struct target_type fa526_target;
extern struct target_type feroceon_target;
extern struct target_type dragonite_target;
extern struct target_type xscale_target;
extern struct target_type xtensa_chip_target;
extern struct target_type cortexm_target;
extern struct target_type cortexa_target;
extern struct target_type aarch64_target;
@ -118,6 +119,7 @@ static struct target_type *target_types[] = {
&feroceon_target,
&dragonite_target,
&xscale_target,
&xtensa_chip_target,
&cortexm_target,
&cortexa_target,
&cortexr4_target,

2
src/target/xtensa/Makefile.am
View File

@ -4,6 +4,8 @@ noinst_LTLIBRARIES += %D%/libxtensa.la
%C%_libxtensa_la_SOURCES = \
%D%/xtensa.c \
%D%/xtensa.h \
%D%/xtensa_chip.c \
%D%/xtensa_chip.h \
%D%/xtensa_debug_module.c \
%D%/xtensa_debug_module.h \
%D%/xtensa_regs.h

2846
src/target/xtensa/xtensa.c
View File

File diff suppressed because it is too large Load Diff

209
src/target/xtensa/xtensa.h
View File

@ -2,6 +2,7 @@
/***************************************************************************
* Generic Xtensa target *
* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2019 Espressif Systems Ltd. *
***************************************************************************/
@ -19,41 +20,77 @@
* Holds the interface to Xtensa cores.
*/
#define XT_ISNS_SZ_MAX 3
/* Big-endian vs. little-endian detection */
#define XT_ISBE(X) ((X)->target->endianness == TARGET_BIG_ENDIAN)
#define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6)
#define XT_PS_RING_MSK (0x3 << 6)
#define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3)
#define XT_PS_CALLINC_MSK (0x3 << 16)
#define XT_PS_OWB_MSK (0xF << 8)
/* 24-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
#define XT_INS_BREAK_LE(S, T) (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4))
#define XT_INS_BREAK_BE(S, T) (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF))
#define XT_INS_BREAK(X, S, T) (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T))
#define XT_LOCAL_MEM_REGIONS_NUM_MAX 8
/* 16-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
#define XT_INS_BREAKN_LE(IMM4) (0xF02D | (((IMM4) & 0xF) << 8))
#define XT_INS_BREAKN_BE(IMM4) (0x0FD2 | (((IMM4) & 0xF) << 12))
#define XT_INS_BREAKN(X, IMM4) (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4))
#define XT_AREGS_NUM_MAX 64
#define XT_USER_REGS_NUM_MAX 256
#define XT_ISNS_SZ_MAX 3
#define XT_MEM_ACCESS_NONE 0x0
#define XT_MEM_ACCESS_READ 0x1
#define XT_MEM_ACCESS_WRITE 0x2
#define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6)
#define XT_PS_RING_MSK (0x3 << 6)
#define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3)
#define XT_PS_CALLINC_MSK (0x3 << 16)
#define XT_PS_OWB_MSK (0xF << 8)
#define XT_PS_WOE_MSK BIT(18)
enum xtensa_mem_err_detect {
XT_MEM_ERR_DETECT_NONE,
XT_MEM_ERR_DETECT_PARITY,
XT_MEM_ERR_DETECT_ECC,
#define XT_LOCAL_MEM_REGIONS_NUM_MAX 8
#define XT_AREGS_NUM_MAX 64
#define XT_USER_REGS_NUM_MAX 256
#define XT_MEM_ACCESS_NONE 0x0
#define XT_MEM_ACCESS_READ 0x1
#define XT_MEM_ACCESS_WRITE 0x2
#define XT_MAX_TIE_REG_WIDTH (512) /* TIE register file max 4096 bits */
#define XT_QUERYPKT_RESP_MAX (XT_MAX_TIE_REG_WIDTH * 2 + 1)
enum xtensa_qerr_e {
XT_QERR_INTERNAL = 0,
XT_QERR_FAIL,
XT_QERR_INVAL,
XT_QERR_MEM,
XT_QERR_NUM,
};
/* An and ARn registers potentially used as scratch regs */
enum xtensa_ar_scratch_set_e {
XT_AR_SCRATCH_A3 = 0,
XT_AR_SCRATCH_AR3,
XT_AR_SCRATCH_A4,
XT_AR_SCRATCH_AR4,
XT_AR_SCRATCH_NUM
};
struct xtensa_keyval_info_s {
char *chrval;
int intval;
};
enum xtensa_type {
XT_UNDEF = 0,
XT_LX,
};
struct xtensa_cache_config {
uint8_t way_count;
uint8_t line_size;
uint16_t size;
bool writeback;
enum xtensa_mem_err_detect mem_err_check;
uint32_t line_size;
uint32_t size;
int writeback;
};
struct xtensa_local_mem_region_config {
target_addr_t base;
uint32_t size;
enum xtensa_mem_err_detect mem_err_check;
int access;
};
@ -66,13 +103,14 @@ struct xtensa_mmu_config {
bool enabled;
uint8_t itlb_entries_count;
uint8_t dtlb_entries_count;
bool ivarway56;
bool dvarway56;
};
struct xtensa_exception_config {
struct xtensa_mpu_config {
bool enabled;
uint8_t depc_num;
uint8_t nfgseg;
uint32_t minsegsize;
bool lockable;
bool execonly;
};
struct xtensa_irq_config {
@ -82,8 +120,8 @@ struct xtensa_irq_config {
struct xtensa_high_prio_irq_config {
bool enabled;
uint8_t level_num;
uint8_t excm_level;
uint8_t nmi_num;
};
struct xtensa_debug_config {
@ -91,7 +129,7 @@ struct xtensa_debug_config {
uint8_t irq_level;
uint8_t ibreaks_num;
uint8_t dbreaks_num;
uint8_t icount_sz;
uint8_t perfcount_num;
};
struct xtensa_tracing_config {
@ -100,48 +138,26 @@ struct xtensa_tracing_config {
bool reversed_mem_access;
};
struct xtensa_timer_irq_config {
bool enabled;
uint8_t comp_num;
};
struct xtensa_config {
bool density;
enum xtensa_type core_type;
uint8_t aregs_num;
bool windowed;
bool coproc;
bool fp_coproc;
bool loop;
uint8_t miscregs_num;
bool threadptr;
bool boolean;
bool cond_store;
bool ext_l32r;
bool mac16;
bool reloc_vec;
bool proc_id;
bool mem_err_check;
uint16_t user_regs_num;
const struct xtensa_user_reg_desc *user_regs;
int (*fetch_user_regs)(struct target *target);
int (*queue_write_dirty_user_regs)(struct target *target);
bool exceptions;
struct xtensa_irq_config irq;
struct xtensa_high_prio_irq_config high_irq;
struct xtensa_mmu_config mmu;
struct xtensa_mpu_config mpu;
struct xtensa_debug_config debug;
struct xtensa_tracing_config trace;
struct xtensa_cache_config icache;
struct xtensa_cache_config dcache;
struct xtensa_local_mem_config irom;
struct xtensa_local_mem_config iram;
struct xtensa_local_mem_config drom;
struct xtensa_local_mem_config dram;
struct xtensa_local_mem_config uram;
struct xtensa_local_mem_config xlmi;
struct xtensa_mmu_config mmu;
struct xtensa_exception_config exc;
struct xtensa_irq_config irq;
struct xtensa_high_prio_irq_config high_irq;
struct xtensa_timer_irq_config tim_irq;
struct xtensa_debug_config debug;
struct xtensa_tracing_config trace;
unsigned int gdb_general_regs_num;
const unsigned int *gdb_regs_mapping;
struct xtensa_local_mem_config sram;
struct xtensa_local_mem_config srom;
};
typedef uint32_t xtensa_insn_t;
@ -175,13 +191,26 @@ struct xtensa_sw_breakpoint {
*/
struct xtensa {
unsigned int common_magic;
const struct xtensa_config *core_config;
struct xtensa_chip_common *xtensa_chip;
struct xtensa_config *core_config;
struct xtensa_debug_module dbg_mod;
struct reg_cache *core_cache;
unsigned int regs_num;
unsigned int total_regs_num;
unsigned int core_regs_num;
bool regmap_contiguous;
unsigned int genpkt_regs_num;
struct xtensa_reg_desc **contiguous_regs_desc;
struct reg **contiguous_regs_list;
/* Per-config Xtensa registers as specified via "xtreg" in xtensa-core*.cfg */
struct xtensa_reg_desc *optregs;
unsigned int num_optregs;
struct reg *empty_regs;
char qpkt_resp[XT_QUERYPKT_RESP_MAX];
/* An array of pointers to buffers to backup registers' values while algo is run on target.
* Size is 'regs_num'. */
void **algo_context_backup;
unsigned int eps_dbglevel_idx;
unsigned int dbregs_num;
struct target *target;
bool reset_asserted;
enum xtensa_stepping_isr_mode stepping_isr_mode;
@ -192,11 +221,18 @@ struct xtensa {
bool permissive_mode; /* bypass memory checks */
bool suppress_dsr_errors;
uint32_t smp_break;
uint32_t spill_loc;
unsigned int spill_bytes;
uint8_t *spill_buf;
int8_t probe_lsddr32p;
/* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
* time.This is the number of polling periods after which core is considered to be powered
* off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
* SW running on target).*/
uint8_t come_online_probes_num;
bool proc_syscall;
bool halt_request;
struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM];
bool regs_fetched; /* true after first register fetch completed successfully */
};
@ -210,7 +246,6 @@ static inline struct xtensa *target_to_xtensa(struct target *target)
int xtensa_init_arch_info(struct target *target,
struct xtensa *xtensa,
const struct xtensa_config *cfg,
const struct xtensa_debug_module_config *dm_cfg);
int xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
void xtensa_target_deinit(struct target *target);
@ -233,11 +268,41 @@ static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
return true;
if (xtensa_addr_in_mem(&xtensa->core_config->dram, addr))
return true;
if (xtensa_addr_in_mem(&xtensa->core_config->uram, addr))
if (xtensa_addr_in_mem(&xtensa->core_config->sram, addr))
return true;
return false;
}
static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, unsigned int reg, uint8_t *data)
{
struct xtensa_debug_module *dm = &xtensa->dbg_mod;
if (!xtensa->core_config->trace.enabled &&
(reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
return ERROR_FAIL;
}
return dm->dbg_ops->queue_reg_read(dm, reg, data);
}
static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
{
struct xtensa_debug_module *dm = &xtensa->dbg_mod;
if (!xtensa->core_config->trace.enabled &&
(reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
return ERROR_FAIL;
}
return dm->dbg_ops->queue_reg_write(dm, reg, data);
}
static inline int xtensa_core_status_clear(struct target *target, uint32_t bits)
{
struct xtensa *xtensa = target_to_xtensa(target);
return xtensa_dm_core_status_clear(&xtensa->dbg_mod, bits);
}
int xtensa_core_status_check(struct target *target);
int xtensa_examine(struct target *target);
@ -248,11 +313,15 @@ int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set);
int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val);
xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id);
void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value);
void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value);
int xtensa_fetch_all_regs(struct target *target);
int xtensa_get_gdb_reg_list(struct target *target,
struct reg **reg_list[],
int *reg_list_size,
enum target_register_class reg_class);
uint32_t xtensa_cause_get(struct target *target);
void xtensa_cause_clear(struct target *target);
void xtensa_cause_reset(struct target *target);
int xtensa_poll(struct target *target);
void xtensa_on_poll(struct target *target);
int xtensa_halt(struct target *target);
@ -281,16 +350,22 @@ int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t c
int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum);
int xtensa_assert_reset(struct target *target);
int xtensa_deassert_reset(struct target *target);
int xtensa_soft_reset_halt(struct target *target);
int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
void xtensa_set_permissive_mode(struct target *target, bool state);
int xtensa_fetch_user_regs_u32(struct target *target);
int xtensa_queue_write_dirty_user_regs_u32(struct target *target);
const char *xtensa_get_gdb_arch(struct target *target);
int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
@ -300,8 +375,6 @@ COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
extern const struct reg_arch_type xtensa_user_reg_u32_type;
extern const struct reg_arch_type xtensa_user_reg_u128_type;
extern const struct command_registration xtensa_command_handlers[];
#endif /* OPENOCD_TARGET_XTENSA_H */

170
src/target/xtensa/xtensa_chip.c Normal file
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@ -0,0 +1,170 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Xtensa Chip-level Target Support for OpenOCD *
* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "assert.h"
#include <target/target.h>
#include <target/target_type.h>
#include <target/arm_adi_v5.h>
#include <rtos/rtos.h>
#include "xtensa_chip.h"
int xtensa_chip_init_arch_info(struct target *target, void *arch_info,
struct xtensa_debug_module_config *dm_cfg)
{
struct xtensa_chip_common *xtensa_chip = (struct xtensa_chip_common *)arch_info;
int ret = xtensa_init_arch_info(target, &xtensa_chip->xtensa, dm_cfg);
if (ret != ERROR_OK)
return ret;
/* All xtensa target structures point back to original xtensa_chip */
xtensa_chip->xtensa.xtensa_chip = arch_info;
return ERROR_OK;
}
int xtensa_chip_target_init(struct command_context *cmd_ctx, struct target *target)
{
return xtensa_target_init(cmd_ctx, target);
}
int xtensa_chip_arch_state(struct target *target)
{
return ERROR_OK;
}
static int xtensa_chip_poll(struct target *target)
{
enum target_state old_state = target->state;
int ret = xtensa_poll(target);
if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
/*Call any event callbacks that are applicable */
if (old_state == TARGET_DEBUG_RUNNING)
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
else
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
return ret;
}
static int xtensa_chip_virt2phys(struct target *target,
target_addr_t virtual, target_addr_t *physical)
{
if (physical) {
*physical = virtual;
return ERROR_OK;
}
return ERROR_FAIL;
}
static const struct xtensa_debug_ops xtensa_chip_dm_dbg_ops = {
.queue_enable = xtensa_dm_queue_enable,
.queue_reg_read = xtensa_dm_queue_reg_read,
.queue_reg_write = xtensa_dm_queue_reg_write
};
static const struct xtensa_power_ops xtensa_chip_dm_pwr_ops = {
.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
.queue_reg_write = xtensa_dm_queue_pwr_reg_write
};
static int xtensa_chip_target_create(struct target *target, Jim_Interp *interp)
{
struct xtensa_debug_module_config xtensa_chip_dm_cfg = {
.dbg_ops = &xtensa_chip_dm_dbg_ops,
.pwr_ops = &xtensa_chip_dm_pwr_ops,
.tap = NULL,
.queue_tdi_idle = NULL,
.queue_tdi_idle_arg = NULL,
};
xtensa_chip_dm_cfg.tap = target->tap;
LOG_DEBUG("JTAG: %s:%s pos %d", target->tap->chip, target->tap->tapname, target->tap->abs_chain_position);
struct xtensa_chip_common *xtensa_chip = calloc(1, sizeof(struct xtensa_chip_common));
if (!xtensa_chip) {
LOG_ERROR("Failed to alloc chip-level memory!");
return ERROR_FAIL;
}
int ret = xtensa_chip_init_arch_info(target, xtensa_chip, &xtensa_chip_dm_cfg);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(xtensa_chip);
return ret;
}
/*Assume running target. If different, the first poll will fix this. */
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
return ERROR_OK;
}
void xtensa_chip_target_deinit(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
xtensa_target_deinit(target);
free(xtensa->xtensa_chip);
}
static int xtensa_chip_examine(struct target *target)
{
return xtensa_examine(target);
}
int xtensa_chip_jim_configure(struct target *target, struct jim_getopt_info *goi)
{
target->has_dap = false;
return JIM_CONTINUE;
}
/** Methods for generic example of Xtensa-based chip-level targets. */
struct target_type xtensa_chip_target = {
.name = "xtensa",
.poll = xtensa_chip_poll,
.arch_state = xtensa_chip_arch_state,
.halt = xtensa_halt,
.resume = xtensa_resume,
.step = xtensa_step,
.assert_reset = xtensa_assert_reset,
.deassert_reset = xtensa_deassert_reset,
.soft_reset_halt = xtensa_soft_reset_halt,
.virt2phys = xtensa_chip_virt2phys,
.mmu = xtensa_mmu_is_enabled,
.read_memory = xtensa_read_memory,
.write_memory = xtensa_write_memory,
.read_buffer = xtensa_read_buffer,
.write_buffer = xtensa_write_buffer,
.checksum_memory = xtensa_checksum_memory,
.get_gdb_reg_list = xtensa_get_gdb_reg_list,
.add_breakpoint = xtensa_breakpoint_add,
.remove_breakpoint = xtensa_breakpoint_remove,
.add_watchpoint = xtensa_watchpoint_add,
.remove_watchpoint = xtensa_watchpoint_remove,
.target_create = xtensa_chip_target_create,
.target_jim_configure = xtensa_chip_jim_configure,
.init_target = xtensa_chip_target_init,
.examine = xtensa_chip_examine,
.deinit_target = xtensa_chip_target_deinit,
.gdb_query_custom = xtensa_gdb_query_custom,
.commands = xtensa_command_handlers,
};

34
src/target/xtensa/xtensa_chip.h Normal file
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@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Xtensa Chip-level Target Support for OpenOCD *
* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
***************************************************************************/
#ifndef OPENOCD_TARGET_XTENSA_CHIP_H
#define OPENOCD_TARGET_XTENSA_CHIP_H
#include <target/target.h>
#include "xtensa.h"
#include "xtensa_debug_module.h"
struct xtensa_chip_common {
struct xtensa xtensa;
/* Chip-specific extensions can be added here */
};
static inline struct xtensa_chip_common *target_to_xtensa_chip(struct target *target)
{
return container_of(target->arch_info, struct xtensa_chip_common, xtensa);
}
int xtensa_chip_init_arch_info(struct target *target, void *arch_info,
struct xtensa_debug_module_config *dm_cfg);
int xtensa_chip_target_init(struct command_context *cmd_ctx, struct target *target);
int xtensa_chip_arch_state(struct target *target);
void xtensa_chip_queue_tdi_idle(struct target *target);
void xtensa_chip_on_reset(struct target *target);
bool xtensa_chip_on_halt(struct target *target);
void xtensa_chip_on_poll(struct target *target);
#endif /* OPENOCD_TARGET_XTENSA_CHIP_H */

224
src/target/xtensa/xtensa_regs.h
View File

@ -2,6 +2,7 @@
/***************************************************************************
* Generic Xtensa target API for OpenOCD *
* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
* Author: Angus Gratton gus@projectgus.com *
***************************************************************************/
@ -14,6 +15,7 @@ struct reg_arch_type;
enum xtensa_reg_id {
XT_REG_IDX_PC = 0,
XT_REG_IDX_AR0,
XT_REG_IDX_ARFIRST = XT_REG_IDX_AR0,
XT_REG_IDX_AR1,
XT_REG_IDX_AR2,
XT_REG_IDX_AR3,
@ -29,152 +31,23 @@ enum xtensa_reg_id {
XT_REG_IDX_AR13,
XT_REG_IDX_AR14,
XT_REG_IDX_AR15,
XT_REG_IDX_AR16,
XT_REG_IDX_AR17,
XT_REG_IDX_AR18,
XT_REG_IDX_AR19,
XT_REG_IDX_AR20,
XT_REG_IDX_AR21,
XT_REG_IDX_AR22,
XT_REG_IDX_AR23,
XT_REG_IDX_AR24,
XT_REG_IDX_AR25,
XT_REG_IDX_AR26,
XT_REG_IDX_AR27,
XT_REG_IDX_AR28,
XT_REG_IDX_AR29,
XT_REG_IDX_AR30,
XT_REG_IDX_AR31,
XT_REG_IDX_AR32,
XT_REG_IDX_AR33,
XT_REG_IDX_AR34,
XT_REG_IDX_AR35,
XT_REG_IDX_AR36,
XT_REG_IDX_AR37,
XT_REG_IDX_AR38,
XT_REG_IDX_AR39,
XT_REG_IDX_AR40,
XT_REG_IDX_AR41,
XT_REG_IDX_AR42,
XT_REG_IDX_AR43,
XT_REG_IDX_AR44,
XT_REG_IDX_AR45,
XT_REG_IDX_AR46,
XT_REG_IDX_AR47,
XT_REG_IDX_AR48,
XT_REG_IDX_AR49,
XT_REG_IDX_AR50,
XT_REG_IDX_AR51,
XT_REG_IDX_AR52,
XT_REG_IDX_AR53,
XT_REG_IDX_AR54,
XT_REG_IDX_AR55,
XT_REG_IDX_AR56,
XT_REG_IDX_AR57,
XT_REG_IDX_AR58,
XT_REG_IDX_AR59,
XT_REG_IDX_AR60,
XT_REG_IDX_AR61,
XT_REG_IDX_AR62,
XT_REG_IDX_AR63,
XT_REG_IDX_LBEG,
XT_REG_IDX_LEND,
XT_REG_IDX_LCOUNT,
XT_REG_IDX_SAR,
XT_REG_IDX_ARLAST = 64, /* Max 64 ARs */
XT_REG_IDX_WINDOWBASE,
XT_REG_IDX_WINDOWSTART,
XT_REG_IDX_CONFIGID0,
XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS,
XT_REG_IDX_THREADPTR,
XT_REG_IDX_BR,
XT_REG_IDX_SCOMPARE1,
XT_REG_IDX_ACCLO,
XT_REG_IDX_ACCHI,
XT_REG_IDX_M0,
XT_REG_IDX_M1,
XT_REG_IDX_M2,
XT_REG_IDX_M3,
XT_REG_IDX_F0,
XT_REG_IDX_F1,
XT_REG_IDX_F2,
XT_REG_IDX_F3,
XT_REG_IDX_F4,
XT_REG_IDX_F5,
XT_REG_IDX_F6,
XT_REG_IDX_F7,
XT_REG_IDX_F8,
XT_REG_IDX_F9,
XT_REG_IDX_F10,
XT_REG_IDX_F11,
XT_REG_IDX_F12,
XT_REG_IDX_F13,
XT_REG_IDX_F14,
XT_REG_IDX_F15,
XT_REG_IDX_FCR,
XT_REG_IDX_FSR,
XT_REG_IDX_MMID,
XT_REG_IDX_IBREAKENABLE,
XT_REG_IDX_MEMCTL,
XT_REG_IDX_ATOMCTL,
XT_REG_IDX_DDR,
XT_REG_IDX_IBREAKA0,
XT_REG_IDX_IBREAKA1,
XT_REG_IDX_DBREAKA0,
XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0,
XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1,
XT_REG_IDX_EPC2,
XT_REG_IDX_EPC3,
XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5,
XT_REG_IDX_EPC6,
XT_REG_IDX_EPC7,
XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2,
XT_REG_IDX_EPS3,
XT_REG_IDX_EPS4,
XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6,
XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1,
XT_REG_IDX_EXCSAVE2,
XT_REG_IDX_EXCSAVE3,
XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5,
XT_REG_IDX_EXCSAVE6,
XT_REG_IDX_EXCSAVE7,
XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT,
XT_REG_IDX_INTSET,
XT_REG_IDX_INTCLEAR,
XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE,
XT_REG_IDX_EXCCAUSE,
XT_REG_IDX_DEBUGCAUSE,
XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID,
XT_REG_IDX_ICOUNT,
XT_REG_IDX_ICOUNTLEVEL,
XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0,
XT_REG_IDX_CCOMPARE1,
XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0,
XT_REG_IDX_MISC1,
XT_REG_IDX_MISC2,
XT_REG_IDX_MISC3,
XT_REG_IDX_LITBASE,
XT_REG_IDX_PTEVADDR,
XT_REG_IDX_RASID,
XT_REG_IDX_ITLBCFG,
XT_REG_IDX_DTLBCFG,
XT_REG_IDX_MEPC,
XT_REG_IDX_MEPS,
XT_REG_IDX_MESAVE,
XT_REG_IDX_MESR,
XT_REG_IDX_MECR,
XT_REG_IDX_MEVADDR,
XT_REG_IDX_A0,
XT_REG_IDX_A1,
XT_REG_IDX_A2,
@ -191,77 +64,72 @@ enum xtensa_reg_id {
XT_REG_IDX_A13,
XT_REG_IDX_A14,
XT_REG_IDX_A15,
XT_REG_IDX_PWRCTL,
XT_REG_IDX_PWRSTAT,
XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL,
XT_REG_IDX_CS_CLAIMSET,
XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS,
XT_REG_IDX_CS_LOCKSTATUS,
XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID,
XT_REG_IDX_TRAX_CTRL,
XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA,
XT_REG_IDX_TRAX_ADDR,
XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH,
XT_REG_IDX_TRAX_DELAY,
XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG,
XT_REG_IDX_PMPC,
XT_REG_IDX_PM0,
XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0,
XT_REG_IDX_PMCTRL1,
XT_REG_IDX_PMSTAT0,
XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID,
XT_REG_IDX_OCD_DCRCLR,
XT_REG_IDX_OCD_DCRSET,
XT_REG_IDX_OCD_DSR,
XT_REG_IDX_OCD_DDR,
XT_NUM_REGS,
/* chip-specific user registers go after ISA-defined ones */
XT_USR_REG_START = XT_NUM_REGS
XT_NUM_REGS
};
typedef uint32_t xtensa_reg_val_t;
#define XT_NUM_A_REGS 16
enum xtensa_reg_type {
XT_REG_GENERAL = 0, /* General-purpose register; part of the windowed register set */
XT_REG_USER = 1, /* User register, needs RUR to read */
XT_REG_SPECIAL = 2, /* Special register, needs RSR to read */
XT_REG_DEBUG = 3, /* Register used for the debug interface. Don't mess with this. */
XT_REG_RELGEN = 4, /* Relative general address. Points to the absolute addresses plus the window
*index */
* index */
XT_REG_FR = 5, /* Floating-point register */
XT_REG_TIE = 6, /* TIE (custom) register */
XT_REG_OTHER = 7, /* Other (typically legacy) register */
XT_REG_TYPE_NUM,
/* enum names must be one of the above types + _VAL or _MASK */
XT_REG_GENERAL_MASK = 0xFFC0,
XT_REG_GENERAL_VAL = 0x0100,
XT_REG_USER_MASK = 0xFF00,
XT_REG_USER_VAL = 0x0300,
XT_REG_SPECIAL_MASK = 0xFF00,
XT_REG_SPECIAL_VAL = 0x0200,
XT_REG_DEBUG_MASK = 0xFF00,
XT_REG_DEBUG_VAL = 0x0200,
XT_REG_RELGEN_MASK = 0xFFE0,
XT_REG_RELGEN_VAL = 0x0000,
XT_REG_FR_MASK = 0xFFF0,
XT_REG_FR_VAL = 0x0030,
XT_REG_TIE_MASK = 0xF000,
XT_REG_TIE_VAL = 0xF000, /* unused */
XT_REG_OTHER_MASK = 0xFFFF,
XT_REG_OTHER_VAL = 0xF000, /* unused */
XT_REG_INDEX_MASK = 0x00FF
};
enum xtensa_reg_flags {
XT_REGF_NOREAD = 0x01, /* Register is write-only */
XT_REGF_COPROC0 = 0x02 /* Can't be read if coproc0 isn't enabled */
XT_REGF_COPROC0 = 0x02, /* Can't be read if coproc0 isn't enabled */
XT_REGF_MASK = 0x03
};
struct xtensa_reg_desc {
const char *name;
bool exist;
unsigned int reg_num; /* ISA register num (meaning depends on register type) */
unsigned int dbreg_num; /* Debugger-visible register num (reg type encoded) */
enum xtensa_reg_type type;
enum xtensa_reg_flags flags;
};
struct xtensa_user_reg_desc {
const char *name;
/* ISA register num (meaning depends on register type) */
unsigned int reg_num;
enum xtensa_reg_flags flags;
uint32_t size;
const struct reg_arch_type *type;
};
#define _XT_MK_DBREGN(reg_num, reg_type) \
((reg_type ## _VAL) | (reg_num))
extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
#define _XT_MK_DBREGN_MASK(reg_num, reg_mask) \
((reg_mask) | (reg_num))
#define XT_MK_REG_DESC(n, r, t, f) \
{ .name = (n), .exist = false, .reg_num = (r), \
.dbreg_num = _XT_MK_DBREGN(r, t), .type = (t), \
.flags = (f) }
extern struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
#endif /* OPENOCD_TARGET_XTENSA_REGS_H */

2
tcl/target/esp32.cfg
View File

@ -68,3 +68,5 @@ if { $_ONLYCPU != 1 } {
}
gdb_breakpoint_override hard
source [find target/xtensa-core-esp32.cfg]

2
tcl/target/esp32s2.cfg
View File

@ -63,3 +63,5 @@ xtensa maskisr on
$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
gdb_breakpoint_override hard
source [find target/xtensa-core-esp32s2.cfg]

2
tcl/target/esp32s3.cfg
View File

@ -124,3 +124,5 @@ if { $_ONLYCPU != 1 } {
}
gdb_breakpoint_override hard
source [find target/xtensa-core-esp32s3.cfg]

260
tcl/target/xtensa-core-esp32.cfg Normal file
View File

@ -0,0 +1,260 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# OpenOCD configuration file for Xtensa ESP32 target
# Core definition and ABI
xtensa xtdef LX
xtensa xtopt arnum 64
xtensa xtopt windowed 1
# Exception/Interrupt Options
xtensa xtopt exceptions 1
xtensa xtopt hipriints 1
xtensa xtopt intlevels 6
xtensa xtopt excmlevel 3
# Cache Options
xtensa xtmem icache 4 0 1
xtensa xtmem dcache 4 0 1 0
# Memory Options
xtensa xtmem irom 0x400D0000 0x330000
xtensa xtmem irom 0x40000000 0x64F00
xtensa xtmem iram 0x40070000 0x30000
xtensa xtmem iram 0x400C0000 0x2000
xtensa xtmem drom 0x3F400000 0x800000
xtensa xtmem dram 0x3FFAE000 0x52000
xtensa xtmem dram 0x3FF80000 0x2000
xtensa xtmem dram 0x3F800000 0x400000
xtensa xtmem dram 0x50000000 0x2000
xtensa xtmem dram 0x3FF00000 0x71000
xtensa xtmem dram 0x60000000 0x20000000
# Memory Protection/Translation Options
# Debug Options
xtensa xtopt debuglevel 6
xtensa xtopt ibreaknum 2
xtensa xtopt dbreaknum 2
xtensa xtopt tracemem 8192
xtensa xtopt tracememrev 1
xtensa xtopt perfcount 2
# Core Registers
# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map.
# Default setting is "sparse" and is used with xt-gdb.
# If contiguous, optional parameter specifies number of registers
# in "Read General Registers" (g-packet) requests.
# NOTE: For contiguous format, registers listed in GDB order.
# xtregs: Total number of Xtensa registers in the system
xtensa xtregs 205
xtensa xtregfmt contiguous 105
xtensa xtreg pc 0x0020
xtensa xtreg ar0 0x0100
xtensa xtreg ar1 0x0101
xtensa xtreg ar2 0x0102
xtensa xtreg ar3 0x0103
xtensa xtreg ar4 0x0104
xtensa xtreg ar5 0x0105
xtensa xtreg ar6 0x0106
xtensa xtreg ar7 0x0107
xtensa xtreg ar8 0x0108
xtensa xtreg ar9 0x0109
xtensa xtreg ar10 0x010a
xtensa xtreg ar11 0x010b
xtensa xtreg ar12 0x010c
xtensa xtreg ar13 0x010d
xtensa xtreg ar14 0x010e
xtensa xtreg ar15 0x010f
xtensa xtreg ar16 0x0110
xtensa xtreg ar17 0x0111
xtensa xtreg ar18 0x0112
xtensa xtreg ar19 0x0113
xtensa xtreg ar20 0x0114
xtensa xtreg ar21 0x0115
xtensa xtreg ar22 0x0116
xtensa xtreg ar23 0x0117
xtensa xtreg ar24 0x0118
xtensa xtreg ar25 0x0119
xtensa xtreg ar26 0x011a
xtensa xtreg ar27 0x011b
xtensa xtreg ar28 0x011c
xtensa xtreg ar29 0x011d
xtensa xtreg ar30 0x011e
xtensa xtreg ar31 0x011f
xtensa xtreg ar32 0x0120
xtensa xtreg ar33 0x0121
xtensa xtreg ar34 0x0122
xtensa xtreg ar35 0x0123
xtensa xtreg ar36 0x0124
xtensa xtreg ar37 0x0125
xtensa xtreg ar38 0x0126
xtensa xtreg ar39 0x0127
xtensa xtreg ar40 0x0128
xtensa xtreg ar41 0x0129
xtensa xtreg ar42 0x012a
xtensa xtreg ar43 0x012b
xtensa xtreg ar44 0x012c
xtensa xtreg ar45 0x012d
xtensa xtreg ar46 0x012e
xtensa xtreg ar47 0x012f
xtensa xtreg ar48 0x0130
xtensa xtreg ar49 0x0131
xtensa xtreg ar50 0x0132
xtensa xtreg ar51 0x0133
xtensa xtreg ar52 0x0134
xtensa xtreg ar53 0x0135
xtensa xtreg ar54 0x0136
xtensa xtreg ar55 0x0137
xtensa xtreg ar56 0x0138
xtensa xtreg ar57 0x0139
xtensa xtreg ar58 0x013a
xtensa xtreg ar59 0x013b
xtensa xtreg ar60 0x013c
xtensa xtreg ar61 0x013d
xtensa xtreg ar62 0x013e
xtensa xtreg ar63 0x013f
xtensa xtreg lbeg 0x0200
xtensa xtreg lend 0x0201
xtensa xtreg lcount 0x0202
xtensa xtreg sar 0x0203
xtensa xtreg windowbase 0x0248
xtensa xtreg windowstart 0x0249
xtensa xtreg configid0 0x02b0
xtensa xtreg configid1 0x02d0
xtensa xtreg ps 0x02e6
xtensa xtreg threadptr 0x03e7
# added by hand for esp32
xtensa xtreg br 0x0204
xtensa xtreg scompare1 0x020c
xtensa xtreg acclo 0x0210
xtensa xtreg acchi 0x0211
xtensa xtreg m0 0x0220
xtensa xtreg m1 0x0221
xtensa xtreg m2 0x0222
xtensa xtreg m3 0x0223
xtensa xtreg expstate 0x03e6
xtensa xtreg f64r_lo 0x03ea
xtensa xtreg f64r_hi 0x03eb
xtensa xtreg f64s 0x03ec
xtensa xtreg f0 0x0030
xtensa xtreg f1 0x0031
xtensa xtreg f2 0x0032
xtensa xtreg f3 0x0033
xtensa xtreg f4 0x0034
xtensa xtreg f5 0x0035
xtensa xtreg f6 0x0036
xtensa xtreg f7 0x0037
xtensa xtreg f8 0x0038
xtensa xtreg f9 0x0039
xtensa xtreg f10 0x003a
xtensa xtreg f11 0x003b
xtensa xtreg f12 0x003c
xtensa xtreg f13 0x003d
xtensa xtreg f14 0x003e
xtensa xtreg f15 0x003f
xtensa xtreg fcr 0x03e8
xtensa xtreg fsr 0x03e9
xtensa xtreg mmid 0x0259
xtensa xtreg ibreakenable 0x0260
xtensa xtreg memctl 0x0261
xtensa xtreg atomctl 0x0263
xtensa xtreg ddr 0x0268
xtensa xtreg ibreaka0 0x0280
xtensa xtreg ibreaka1 0x0281
xtensa xtreg dbreaka0 0x0290
xtensa xtreg dbreaka1 0x0291
xtensa xtreg dbreakc0 0x02a0
xtensa xtreg dbreakc1 0x02a1
xtensa xtreg epc1 0x02b1
xtensa xtreg epc2 0x02b2
xtensa xtreg epc3 0x02b3
xtensa xtreg epc4 0x02b4
xtensa xtreg epc5 0x02b5
xtensa xtreg epc6 0x02b6
xtensa xtreg epc7 0x02b7
xtensa xtreg depc 0x02c0
xtensa xtreg eps2 0x02c2
xtensa xtreg eps3 0x02c3
xtensa xtreg eps4 0x02c4
xtensa xtreg eps5 0x02c5
xtensa xtreg eps6 0x02c6
xtensa xtreg eps7 0x02c7
xtensa xtreg excsave1 0x02d1
xtensa xtreg excsave2 0x02d2
xtensa xtreg excsave3 0x02d3
xtensa xtreg excsave4 0x02d4
xtensa xtreg excsave5 0x02d5
xtensa xtreg excsave6 0x02d6
xtensa xtreg excsave7 0x02d7
xtensa xtreg cpenable 0x02e0
xtensa xtreg interrupt 0x02e2
xtensa xtreg intset 0x02e2
xtensa xtreg intclear 0x02e3
xtensa xtreg intenable 0x02e4
xtensa xtreg vecbase 0x02e7
xtensa xtreg exccause 0x02e8
xtensa xtreg debugcause 0x02e9
xtensa xtreg ccount 0x02ea
xtensa xtreg prid 0x02eb
xtensa xtreg icount 0x02ec
xtensa xtreg icountlevel 0x02ed
xtensa xtreg excvaddr 0x02ee
xtensa xtreg ccompare0 0x02f0
xtensa xtreg ccompare1 0x02f1
xtensa xtreg ccompare2 0x02f2
xtensa xtreg misc0 0x02f4
xtensa xtreg misc1 0x02f5
xtensa xtreg misc2 0x02f6
xtensa xtreg misc3 0x02f7
xtensa xtreg a0 0x0000
xtensa xtreg a1 0x0001
xtensa xtreg a2 0x0002
xtensa xtreg a3 0x0003
xtensa xtreg a4 0x0004
xtensa xtreg a5 0x0005
xtensa xtreg a6 0x0006
xtensa xtreg a7 0x0007
xtensa xtreg a8 0x0008
xtensa xtreg a9 0x0009
xtensa xtreg a10 0x000a
xtensa xtreg a11 0x000b
xtensa xtreg a12 0x000c
xtensa xtreg a13 0x000d
xtensa xtreg a14 0x000e
xtensa xtreg a15 0x000f
xtensa xtreg pwrctl 0x2028
xtensa xtreg pwrstat 0x2029
xtensa xtreg eristat 0x202a
xtensa xtreg cs_itctrl 0x202b
xtensa xtreg cs_claimset 0x202c
xtensa xtreg cs_claimclr 0x202d
xtensa xtreg cs_lockaccess 0x202e
xtensa xtreg cs_lockstatus 0x202f
xtensa xtreg cs_authstatus 0x2030
xtensa xtreg fault_info 0x203f
xtensa xtreg trax_id 0x2040
xtensa xtreg trax_control 0x2041
xtensa xtreg trax_status 0x2042
xtensa xtreg trax_data 0x2043
xtensa xtreg trax_address 0x2044
xtensa xtreg trax_pctrigger 0x2045
xtensa xtreg trax_pcmatch 0x2046
xtensa xtreg trax_delay 0x2047
xtensa xtreg trax_memstart 0x2048
xtensa xtreg trax_memend 0x2049
xtensa xtreg pmg 0x2057
xtensa xtreg pmpc 0x2058
xtensa xtreg pm0 0x2059
xtensa xtreg pm1 0x205a
xtensa xtreg pmctrl0 0x2061
xtensa xtreg pmctrl1 0x2062
xtensa xtreg pmstat0 0x2069
xtensa xtreg pmstat1 0x206a
xtensa xtreg ocdid 0x2071
xtensa xtreg ocd_dcrclr 0x2072
xtensa xtreg ocd_dcrset 0x2073
xtensa xtreg ocd_dsr 0x2074

223
tcl/target/xtensa-core-esp32s2.cfg Normal file
View File

@ -0,0 +1,223 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# OpenOCD configuration file for Xtensa ESP32S2 target
# Core definition and ABI
xtensa xtdef LX
xtensa xtopt arnum 64
xtensa xtopt windowed 1
# Exception/Interrupt Options
xtensa xtopt exceptions 1
xtensa xtopt hipriints 1
xtensa xtopt intlevels 6
xtensa xtopt excmlevel 3
# Cache Options
xtensa xtmem icache 4 0 1
xtensa xtmem dcache 4 0 1 0
# Memory Options
xtensa xtmem irom 0x40080000 0x780000
xtensa xtmem irom 0x40000000 0x20000
xtensa xtmem iram 0x40020000 0x50000
xtensa xtmem iram 0x40070000 0x2000
xtensa xtmem drom 0x3F000000 0x400000
xtensa xtmem drom 0x3F4D3FFC 0xAAC004
xtensa xtmem dram 0x3FFB0000 0x50000
xtensa xtmem dram 0x3FF9E000 0x2000
xtensa xtmem dram 0x50000000 0x2000
xtensa xtmem dram 0x3F500000 0xA80000
xtensa xtmem dram 0x3F400000 0xD3FFC
xtensa xtmem dram 0x60000000 0x20000000
# Memory Protection/Translation Options
# Debug Options
xtensa xtopt debuglevel 6
xtensa xtopt ibreaknum 2
xtensa xtopt dbreaknum 2
xtensa xtopt tracemem 8192
xtensa xtopt tracememrev 1
xtensa xtopt perfcount 2
# Core Registers
# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map.
# Default setting is "sparse" and is used with xt-gdb.
# If contiguous, optional parameter specifies number of registers
# in "Read General Registers" (g-packet) requests.
# NOTE: For contiguous format, registers listed in GDB order.
# xtregs: Total number of Xtensa registers in the system
xtensa xtregs 171
xtensa xtregfmt contiguous 72
xtensa xtreg pc 0x0020
xtensa xtreg ar0 0x0100
xtensa xtreg ar1 0x0101
xtensa xtreg ar2 0x0102
xtensa xtreg ar3 0x0103
xtensa xtreg ar4 0x0104
xtensa xtreg ar5 0x0105
xtensa xtreg ar6 0x0106
xtensa xtreg ar7 0x0107
xtensa xtreg ar8 0x0108
xtensa xtreg ar9 0x0109
xtensa xtreg ar10 0x010a
xtensa xtreg ar11 0x010b
xtensa xtreg ar12 0x010c
xtensa xtreg ar13 0x010d
xtensa xtreg ar14 0x010e
xtensa xtreg ar15 0x010f
xtensa xtreg ar16 0x0110
xtensa xtreg ar17 0x0111
xtensa xtreg ar18 0x0112
xtensa xtreg ar19 0x0113
xtensa xtreg ar20 0x0114
xtensa xtreg ar21 0x0115
xtensa xtreg ar22 0x0116
xtensa xtreg ar23 0x0117
xtensa xtreg ar24 0x0118
xtensa xtreg ar25 0x0119
xtensa xtreg ar26 0x011a
xtensa xtreg ar27 0x011b
xtensa xtreg ar28 0x011c
xtensa xtreg ar29 0x011d
xtensa xtreg ar30 0x011e
xtensa xtreg ar31 0x011f
xtensa xtreg ar32 0x0120
xtensa xtreg ar33 0x0121
xtensa xtreg ar34 0x0122
xtensa xtreg ar35 0x0123
xtensa xtreg ar36 0x0124
xtensa xtreg ar37 0x0125
xtensa xtreg ar38 0x0126
xtensa xtreg ar39 0x0127
xtensa xtreg ar40 0x0128
xtensa xtreg ar41 0x0129
xtensa xtreg ar42 0x012a
xtensa xtreg ar43 0x012b
xtensa xtreg ar44 0x012c
xtensa xtreg ar45 0x012d
xtensa xtreg ar46 0x012e
xtensa xtreg ar47 0x012f
xtensa xtreg ar48 0x0130
xtensa xtreg ar49 0x0131
xtensa xtreg ar50 0x0132
xtensa xtreg ar51 0x0133
xtensa xtreg ar52 0x0134
xtensa xtreg ar53 0x0135
xtensa xtreg ar54 0x0136
xtensa xtreg ar55 0x0137
xtensa xtreg ar56 0x0138
xtensa xtreg ar57 0x0139
xtensa xtreg ar58 0x013a
xtensa xtreg ar59 0x013b
xtensa xtreg ar60 0x013c
xtensa xtreg ar61 0x013d
xtensa xtreg ar62 0x013e
xtensa xtreg ar63 0x013f
xtensa xtreg sar 0x0203
xtensa xtreg windowbase 0x0248
xtensa xtreg windowstart 0x0249
xtensa xtreg configid0 0x02b0
xtensa xtreg configid1 0x02d0
xtensa xtreg ps 0x02e6
xtensa xtreg threadptr 0x03e7
# gpio_out should be 0x0300? Hits an exception on wrover
xtensa xtreg gpio_out 0x0268
xtensa xtreg mmid 0x0259
xtensa xtreg ibreakenable 0x0260
xtensa xtreg ddr 0x0268
xtensa xtreg ibreaka0 0x0280
xtensa xtreg ibreaka1 0x0281
xtensa xtreg dbreaka0 0x0290
xtensa xtreg dbreaka1 0x0291
xtensa xtreg dbreakc0 0x02a0
xtensa xtreg dbreakc1 0x02a1
xtensa xtreg epc1 0x02b1
xtensa xtreg epc2 0x02b2
xtensa xtreg epc3 0x02b3
xtensa xtreg epc4 0x02b4
xtensa xtreg epc5 0x02b5
xtensa xtreg epc6 0x02b6
xtensa xtreg epc7 0x02b7
xtensa xtreg depc 0x02c0
xtensa xtreg eps2 0x02c2
xtensa xtreg eps3 0x02c3
xtensa xtreg eps4 0x02c4
xtensa xtreg eps5 0x02c5
xtensa xtreg eps6 0x02c6
xtensa xtreg eps7 0x02c7
xtensa xtreg excsave1 0x02d1
xtensa xtreg excsave2 0x02d2
xtensa xtreg excsave3 0x02d3
xtensa xtreg excsave4 0x02d4
xtensa xtreg excsave5 0x02d5
xtensa xtreg excsave6 0x02d6
xtensa xtreg excsave7 0x02d7
xtensa xtreg cpenable 0x02e0
xtensa xtreg interrupt 0x02e2
xtensa xtreg intset 0x02e2
xtensa xtreg intclear 0x02e3
xtensa xtreg intenable 0x02e4
xtensa xtreg vecbase 0x02e7
xtensa xtreg exccause 0x02e8
xtensa xtreg debugcause 0x02e9
xtensa xtreg ccount 0x02ea
xtensa xtreg prid 0x02eb
xtensa xtreg icount 0x02ec
xtensa xtreg icountlevel 0x02ed
xtensa xtreg excvaddr 0x02ee
xtensa xtreg ccompare0 0x02f0
xtensa xtreg ccompare1 0x02f1
xtensa xtreg ccompare2 0x02f2
xtensa xtreg misc0 0x02f4
xtensa xtreg misc1 0x02f5
xtensa xtreg misc2 0x02f6
xtensa xtreg misc3 0x02f7
xtensa xtreg a0 0x0000
xtensa xtreg a1 0x0001
xtensa xtreg a2 0x0002
xtensa xtreg a3 0x0003
xtensa xtreg a4 0x0004
xtensa xtreg a5 0x0005
xtensa xtreg a6 0x0006
xtensa xtreg a7 0x0007
xtensa xtreg a8 0x0008
xtensa xtreg a9 0x0009
xtensa xtreg a10 0x000a
xtensa xtreg a11 0x000b
xtensa xtreg a12 0x000c
xtensa xtreg a13 0x000d
xtensa xtreg a14 0x000e
xtensa xtreg a15 0x000f
xtensa xtreg pwrctl 0x2028
xtensa xtreg pwrstat 0x2029
xtensa xtreg eristat 0x202a
xtensa xtreg cs_itctrl 0x202b
xtensa xtreg cs_claimset 0x202c
xtensa xtreg cs_claimclr 0x202d
xtensa xtreg cs_lockaccess 0x202e
xtensa xtreg cs_lockstatus 0x202f
xtensa xtreg cs_authstatus 0x2030
xtensa xtreg fault_info 0x203f
xtensa xtreg trax_id 0x2040
xtensa xtreg trax_control 0x2041
xtensa xtreg trax_status 0x2042
xtensa xtreg trax_data 0x2043
xtensa xtreg trax_address 0x2044
xtensa xtreg trax_pctrigger 0x2045
xtensa xtreg trax_pcmatch 0x2046
xtensa xtreg trax_delay 0x2047
xtensa xtreg trax_memstart 0x2048
xtensa xtreg trax_memend 0x2049
xtensa xtreg pmg 0x2057
xtensa xtreg pmpc 0x2058
xtensa xtreg pm0 0x2059
xtensa xtreg pm1 0x205a
xtensa xtreg pmctrl0 0x2061
xtensa xtreg pmctrl1 0x2062
xtensa xtreg pmstat0 0x2069
xtensa xtreg pmstat1 0x206a
xtensa xtreg ocdid 0x2071
xtensa xtreg ocd_dcrclr 0x2072
xtensa xtreg ocd_dcrset 0x2073
xtensa xtreg ocd_dsr 0x2074

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# SPDX-License-Identifier: GPL-2.0-or-later
# OpenOCD configuration file for Xtensa ESP32S3 target
# Core definition and ABI
xtensa xtdef LX
xtensa xtopt arnum 64
xtensa xtopt windowed 1
# Exception/Interrupt Options
xtensa xtopt exceptions 1
xtensa xtopt hipriints 1
xtensa xtopt intlevels 6
xtensa xtopt excmlevel 3
# Cache Options
# Memory Options
xtensa xtmem irom 0x42000000 0x2000000
xtensa xtmem irom 0x40000000 0x60000
xtensa xtmem iram 0x40370000 0x70000
xtensa xtmem iram 0x600FE000 0x2000
xtensa xtmem drom 0x3C000000 0x1000000
xtensa xtmem dram 0x3FC88000 0x78000
xtensa xtmem dram 0x600FE000 0x2000
xtensa xtmem dram 0x50000000 0x2000
xtensa xtmem dram 0x60000000 0x10000000
# Memory Protection/Translation Options
# Debug Options
xtensa xtopt debuglevel 6
xtensa xtopt ibreaknum 2
xtensa xtopt dbreaknum 2
xtensa xtopt tracemem 16384
xtensa xtopt tracememrev 1
xtensa xtopt perfcount 2
# Core Registers
# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map.
# Default setting is "sparse" and is used with xt-gdb.
# If contiguous, optional parameter specifies number of registers
# in "Read General Registers" (g-packet) requests.
# NOTE: For contiguous format, registers listed in GDB order.
# xtregs: Total number of Xtensa registers in the system
xtensa xtregs 244
xtensa xtregfmt contiguous 128
xtensa xtreg pc 0x0020
xtensa xtreg ar0 0x0100
xtensa xtreg ar1 0x0101
xtensa xtreg ar2 0x0102
xtensa xtreg ar3 0x0103
xtensa xtreg ar4 0x0104
xtensa xtreg ar5 0x0105
xtensa xtreg ar6 0x0106
xtensa xtreg ar7 0x0107
xtensa xtreg ar8 0x0108
xtensa xtreg ar9 0x0109
xtensa xtreg ar10 0x010a
xtensa xtreg ar11 0x010b
xtensa xtreg ar12 0x010c
xtensa xtreg ar13 0x010d
xtensa xtreg ar14 0x010e
xtensa xtreg ar15 0x010f
xtensa xtreg ar16 0x0110
xtensa xtreg ar17 0x0111
xtensa xtreg ar18 0x0112
xtensa xtreg ar19 0x0113
xtensa xtreg ar20 0x0114
xtensa xtreg ar21 0x0115
xtensa xtreg ar22 0x0116
xtensa xtreg ar23 0x0117
xtensa xtreg ar24 0x0118
xtensa xtreg ar25 0x0119
xtensa xtreg ar26 0x011a
xtensa xtreg ar27 0x011b
xtensa xtreg ar28 0x011c
xtensa xtreg ar29 0x011d
xtensa xtreg ar30 0x011e
xtensa xtreg ar31 0x011f
xtensa xtreg ar32 0x0120
xtensa xtreg ar33 0x0121
xtensa xtreg ar34 0x0122
xtensa xtreg ar35 0x0123
xtensa xtreg ar36 0x0124
xtensa xtreg ar37 0x0125
xtensa xtreg ar38 0x0126
xtensa xtreg ar39 0x0127
xtensa xtreg ar40 0x0128
xtensa xtreg ar41 0x0129
xtensa xtreg ar42 0x012a
xtensa xtreg ar43 0x012b
xtensa xtreg ar44 0x012c
xtensa xtreg ar45 0x012d
xtensa xtreg ar46 0x012e
xtensa xtreg ar47 0x012f
xtensa xtreg ar48 0x0130
xtensa xtreg ar49 0x0131
xtensa xtreg ar50 0x0132
xtensa xtreg ar51 0x0133
xtensa xtreg ar52 0x0134
xtensa xtreg ar53 0x0135
xtensa xtreg ar54 0x0136
xtensa xtreg ar55 0x0137
xtensa xtreg ar56 0x0138
xtensa xtreg ar57 0x0139
xtensa xtreg ar58 0x013a
xtensa xtreg ar59 0x013b
xtensa xtreg ar60 0x013c
xtensa xtreg ar61 0x013d
xtensa xtreg ar62 0x013e
xtensa xtreg ar63 0x013f
xtensa xtreg lbeg 0x0200
xtensa xtreg lend 0x0201
xtensa xtreg lcount 0x0202
xtensa xtreg sar 0x0203
xtensa xtreg windowbase 0x0248
xtensa xtreg windowstart 0x0249
xtensa xtreg configid0 0x02b0
xtensa xtreg configid1 0x02d0
xtensa xtreg ps 0x02e6
xtensa xtreg threadptr 0x03e7
xtensa xtreg br 0x0204
xtensa xtreg scompare1 0x020c
xtensa xtreg acclo 0x0210
xtensa xtreg acchi 0x0211
xtensa xtreg m0 0x0220
xtensa xtreg m1 0x0221
xtensa xtreg m2 0x0222
xtensa xtreg m3 0x0223
# TODO: update gpioout address while testing on S3 HW
xtensa xtreg gpioout 0x02f4
xtensa xtreg f0 0x0030
xtensa xtreg f1 0x0031
xtensa xtreg f2 0x0032
xtensa xtreg f3 0x0033
xtensa xtreg f4 0x0034
xtensa xtreg f5 0x0035
xtensa xtreg f6 0x0036
xtensa xtreg f7 0x0037
xtensa xtreg f8 0x0038
xtensa xtreg f9 0x0039
xtensa xtreg f10 0x003a
xtensa xtreg f11 0x003b
xtensa xtreg f12 0x003c
xtensa xtreg f13 0x003d
xtensa xtreg f14 0x003e
xtensa xtreg f15 0x003f
xtensa xtreg fcr 0x03e8
xtensa xtreg fsr 0x03e9
# TODO: update TIE state
xtensa xtreg accx_0 0x02f4
xtensa xtreg accx_1 0x02f4
xtensa xtreg qacc_h_0 0x02f4
xtensa xtreg qacc_h_1 0x02f4
xtensa xtreg qacc_h_2 0x02f4
xtensa xtreg qacc_h_3 0x02f4
xtensa xtreg qacc_h_4 0x02f4
xtensa xtreg qacc_l_0 0x02f4
xtensa xtreg qacc_l_1 0x02f4
xtensa xtreg qacc_l_2 0x02f4
xtensa xtreg qacc_l_3 0x02f4
xtensa xtreg qacc_l_4 0x02f4
xtensa xtreg sar_byte 0x02f4
xtensa xtreg fft_bit_width 0x02f4
xtensa xtreg ua_state_0 0x02f4
xtensa xtreg ua_state_1 0x02f4
xtensa xtreg ua_state_2 0x02f4
xtensa xtreg ua_state_3 0x02f4
xtensa xtreg q0 0x02f4
xtensa xtreg q1 0x02f4
xtensa xtreg q2 0x02f4
xtensa xtreg q3 0x02f4
xtensa xtreg q4 0x02f4
xtensa xtreg q5 0x02f4
xtensa xtreg q6 0x02f4
xtensa xtreg q7 0x02f4
xtensa xtreg mmid 0x0259
xtensa xtreg ibreakenable 0x0260
xtensa xtreg memctl 0x0261
xtensa xtreg atomctl 0x0263
xtensa xtreg ddr 0x0268
xtensa xtreg ibreaka0 0x0280
xtensa xtreg ibreaka1 0x0281
xtensa xtreg dbreaka0 0x0290
xtensa xtreg dbreaka1 0x0291
xtensa xtreg dbreakc0 0x02a0
xtensa xtreg dbreakc1 0x02a1
xtensa xtreg epc1 0x02b1
xtensa xtreg epc2 0x02b2
xtensa xtreg epc3 0x02b3
xtensa xtreg epc4 0x02b4
xtensa xtreg epc5 0x02b5
xtensa xtreg epc6 0x02b6
xtensa xtreg epc7 0x02b7
xtensa xtreg depc 0x02c0
xtensa xtreg eps2 0x02c2
xtensa xtreg eps3 0x02c3
xtensa xtreg eps4 0x02c4
xtensa xtreg eps5 0x02c5
xtensa xtreg eps6 0x02c6
xtensa xtreg eps7 0x02c7
xtensa xtreg excsave1 0x02d1
xtensa xtreg excsave2 0x02d2
xtensa xtreg excsave3 0x02d3
xtensa xtreg excsave4 0x02d4
xtensa xtreg excsave5 0x02d5
xtensa xtreg excsave6 0x02d6
xtensa xtreg excsave7 0x02d7
xtensa xtreg cpenable 0x02e0
xtensa xtreg interrupt 0x02e2
xtensa xtreg intset 0x02e2
xtensa xtreg intclear 0x02e3
xtensa xtreg intenable 0x02e4
xtensa xtreg vecbase 0x02e7
xtensa xtreg exccause 0x02e8
xtensa xtreg debugcause 0x02e9
xtensa xtreg ccount 0x02ea
xtensa xtreg prid 0x02eb
xtensa xtreg icount 0x02ec
xtensa xtreg icountlevel 0x02ed
xtensa xtreg excvaddr 0x02ee
xtensa xtreg ccompare0 0x02f0
xtensa xtreg ccompare1 0x02f1
xtensa xtreg ccompare2 0x02f2
xtensa xtreg misc0 0x02f4
xtensa xtreg misc1 0x02f5
xtensa xtreg misc2 0x02f6
xtensa xtreg misc3 0x02f7
xtensa xtreg pwrctl 0x2025
xtensa xtreg pwrstat 0x2026
xtensa xtreg eristat 0x2027
xtensa xtreg cs_itctrl 0x2028
xtensa xtreg cs_claimset 0x2029
xtensa xtreg cs_claimclr 0x202a
xtensa xtreg cs_lockaccess 0x202b
xtensa xtreg cs_lockstatus 0x202c
xtensa xtreg cs_authstatus 0x202d
xtensa xtreg fault_info 0x203c
xtensa xtreg trax_id 0x203d
xtensa xtreg trax_control 0x203e
xtensa xtreg trax_status 0x203f
xtensa xtreg trax_data 0x2040
xtensa xtreg trax_address 0x2041
xtensa xtreg trax_pctrigger 0x2042
xtensa xtreg trax_pcmatch 0x2043
xtensa xtreg trax_delay 0x2044
xtensa xtreg trax_memstart 0x2045
xtensa xtreg trax_memend 0x2046
xtensa xtreg pmg 0x2054
xtensa xtreg pmpc 0x2055
xtensa xtreg pm0 0x2056
xtensa xtreg pm1 0x2057
xtensa xtreg pmctrl0 0x2058
xtensa xtreg pmctrl1 0x2059
xtensa xtreg pmstat0 0x205a
xtensa xtreg pmstat1 0x205b
xtensa xtreg ocdid 0x205c
xtensa xtreg ocd_dcrclr 0x205d
xtensa xtreg ocd_dcrset 0x205e
xtensa xtreg ocd_dsr 0x205f
xtensa xtreg a0 0x0000
xtensa xtreg a1 0x0001
xtensa xtreg a2 0x0002
xtensa xtreg a3 0x0003
xtensa xtreg a4 0x0004
xtensa xtreg a5 0x0005
xtensa xtreg a6 0x0006
xtensa xtreg a7 0x0007
xtensa xtreg a8 0x0008
xtensa xtreg a9 0x0009
xtensa xtreg a10 0x000a
xtensa xtreg a11 0x000b
xtensa xtreg a12 0x000c
xtensa xtreg a13 0x000d
xtensa xtreg a14 0x000e
xtensa xtreg a15 0x000f
xtensa xtreg b0 0x0010
xtensa xtreg b1 0x0011
xtensa xtreg b2 0x0012
xtensa xtreg b3 0x0013
xtensa xtreg b4 0x0014
xtensa xtreg b5 0x0015
xtensa xtreg b6 0x0016
xtensa xtreg b7 0x0017
xtensa xtreg b8 0x0018
xtensa xtreg b9 0x0019
xtensa xtreg b10 0x001a
xtensa xtreg b11 0x001b
xtensa xtreg b12 0x001c
xtensa xtreg b13 0x001d
xtensa xtreg b14 0x001e
xtensa xtreg b15 0x001f