Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c. There should be no
change in functionality here. (From Magnus.)
Minor style cleanup: whitespace, line length, etc. Update spec
references to use docs which are currently available. (From Dave.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- change SWJDP_IR/DR_APACC to DAP_IR/DR_APACC to conform with ARM_ADI docs.
- add swjdp->memaccess_tck field and code for extra tck clocks before accessing memory bus
- Set default memaccess value to 8 for Cortex-M3.
- Add dap memaccess command.
- document all armv7 dap cmds.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2005 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->run_algorithm.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1961 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Added support for accessport ROM table identification, dap command.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- cleaned up headers to match rest of code
- added missing svn props for previously added files
git-svn-id: svn://svn.berlios.de/openocd/trunk@987 b42882b7-edfa-0310-969c-e2dbd0fdcd60
converts a number of 'simple string lookup tables' into NVP tables.
These NVP tables will be used by various commands coming in the next patch.
git-svn-id: svn://svn.berlios.de/openocd/trunk@962 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- added armv7m dummy cpsr register to stop gdb setting thumb bit
git-svn-id: svn://svn.berlios.de/openocd/trunk@623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon.
- now checks for User Thread Mode and Thread mode when halted.
- removed repeated function declarations from command.c
- cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit
git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- uses packed transfers for 8/16bit read/writes greater than 4bytes
- 8/16bit transfers now use address auto increment
git-svn-id: svn://svn.berlios.de/openocd/trunk@495 b42882b7-edfa-0310-969c-e2dbd0fdcd60
are up and running. The examination and validation is actually
"optional" from the point of view of GDB + telnet servers.
Multiple targets should work fine with this.
- jtag_speed is dropped(divisor is increased), if jtag examination and
validation fails.
- the chain is validated 10x to catch the worst jtag_speed offences
- added LOG_SILENT that can be used to shut up log. Feeble
ersatz for try+catch.
- GDB register packets are now always replied in order to make sure
that GDB connect works. If the target is not halted, then these
packets contain dummy values.
git-svn-id: svn://svn.berlios.de/openocd/trunk@483 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- switch to synchronous halt during connect. This fixes the bug
where poll() was not invoked between halt() and servicing the
'g' register packet
- halt() no longer returns error code when target is already halted, just
logs a warning. Only the halt() implementation can say anything
meaningful about why a halt() failed, so error messages are pushed
up to halt()
- fixed soft_reset_halt infinite loop bug in arm7_9_common.c. The rest
of the implementations are still busted.
- by using USER() instead of command_print() the log gets the
source + line #. Nice.
- no longer invoke exit() if soft_reset_halt fails. A reset can often
fix the problem.
git-svn-id: svn://svn.berlios.de/openocd/trunk@475 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Small cosmetic fixes in the license header to make them all look the
same, fix some typos, update README.
git-svn-id: svn://svn.berlios.de/openocd/trunk@396 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- corrected array overrun in armv7m.c
- corrected breakpoint memory allocation bug
- image read now uses fgets, vastly improves reading of large files
- improved hex file reading, support for Linear Address Record added
git-svn-id: svn://svn.berlios.de/openocd/trunk@208 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Clean up, remove unused variables and code in armv7, cortex_m3 and stellaris code
- Move restore_context from cortex_m3 to armv7m
- Updated halt handling for cortex_m3
git-svn-id: svn://svn.berlios.de/openocd/trunk@206 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- ST STM32x flash support added
- cleaned up armv7m and cortex-m3 support, removed luminary specific code
- cortex-m3 16bit read/write added (required for STM32x flash programming)
git-svn-id: svn://svn.berlios.de/openocd/trunk@177 b42882b7-edfa-0310-969c-e2dbd0fdcd60
