Updated to v2.13.1
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
parent
3969019d6a
commit
aaca3d5613
GPG Key ID:
DB982239424FF8AC
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@ -1,16 +1,15 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<ksdk:manifest xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" id="SDK_2.x_LPC55S69" name="LPC55S69" brief="This is SDK version 2.13.0 manifest file. It describes the content of the LPC55S69 and additional settings for tools that support SDK version 2.13.0" format_version="3.10" api_version="2.0.0" configuration="360b5b2de6f1503d038c8914436668b8" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd http://nxp.com/mcuxpresso/sdk/sdk_manifest_v3.10.xsd">
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<!--Timestamp (UTC): 2023-01-19 16:26:16.460842-->
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<!--This manifest is generated based on sdk repo commit: 9add71d10bd80a4b245f4f3ad49616fb10c8144f-->
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<ksdk:manifest xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" id="SDK_2.x_LPC55S69" name="LPC55S69" brief="This is SDK version 2.13.1 manifest file. It describes the content of the LPC55S69 and additional settings for tools that support SDK version 2.13.1" format_version="3.10" api_version="2.0.0" configuration="e106fe5940864919643d9e4d0df145c5" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd http://nxp.com/mcuxpresso/sdk/sdk_manifest_v3.10.xsd">
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<!--Timestamp (UTC): 2023-05-25 07:34:49.480114-->
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<!--This manifest is generated based on sdk repo commit: 7a3cf97dd3582e3ee8a98ede814ff1f2a45ea519-->
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<defines>
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<define name="CPU_$|package|" value=""/>
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<define name="CPU_$|package|_$|core|" value=""/>
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<define name="CPU_$|package|_$|core_name|" value=""/>
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</defines>
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<ksdk id="MCUXpresso2130" name="MCUXpresso2130" version="2.13.0" revision="667 2023-01-18"/>
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<ksdk id="MCUXpresso2131" name="MCUXpresso2131" version="2.13.1" revision="679 2023-03-27"/>
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<compilers>
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<compiler id="compiler_gcc" name="gcc" type="gcc"/>
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<compiler id="compiler_mwcc56800e" name="mwcc56800e" type="mwcc56800e"/>
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</compilers>
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<core_slave_roles_definitions>
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<slave_role id="M33SLAVE" name="Cortex-M33 core1 acts as slave by default"/>
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@ -39,7 +38,6 @@
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</toolchainSettings>
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<toolchains>
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<toolchain id="armgcc" name="GCC_ARM_Embedded_10-2021.10" version="10.3.1" full_name="GCC ARM Embedded 10-2021.10" compiler="compiler_gcc" type="armgcc" vendor="GCC ARM Embedded" vendor_url="http://launchpad.net/gcc-arm-embedded"/>
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<toolchain id="cwmcu" name="CodeWarrior_Development_Studio" version="11.1" full_name="CodeWarrior Development Studio" compiler="compiler_mwcc56800e" type="cwmcu" vendor="NXP Semiconductors" vendor_url="http://www.nxp.com"/>
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<toolchain id="mcuxpresso" name="MCUXpresso_IDE" version="11.7.0" full_name="MCUXpresso IDE" compiler="compiler_gcc" type="mcuxpresso" vendor="NXP Semiconductors" vendor_url="http://www.nxp.com">
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<debug>
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<debug_configuration id="com.crt.advproject.config.exe.release" name="Release Configuration" probe="LinkServer">
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@ -944,6 +942,11 @@ ${load}</script>
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<files mask="lvgl_guider_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_lvgl_guider_bm" name="lvgl_guider_bm" brief="LVGL project used with GUI Guider on baremetal." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="lvgl_examples" path="boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/cm33_core0">
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<external path="boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/cm33_core0" type="xml">
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<files mask="lvgl_guider_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_maestro_playback" name="maestro_playback" brief="Audio maestro framework demo example." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="audio_examples" path="boards/lpcxpresso55s69/audio_examples/maestro_playback/cm33_core0">
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<external path="boards/lpcxpresso55s69/audio_examples/maestro_playback/cm33_core0" type="xml">
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<files mask="maestro_playback_v3_10.xml"/>
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@ -1159,11 +1162,6 @@ ${load}</script>
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<files mask="rtc_example_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_safety_iec60730b_core0" name="safety_iec60730b_core0" brief="This example demonstrates the core self-test of the IEC60730B." toolchain="mcuxpresso" compiler="compiler_gcc" category="demo_apps" path="boards/lpcxpresso55s69/demo_apps/safety_iec60730b/cm33_core0">
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<external path="boards/lpcxpresso55s69/demo_apps/safety_iec60730b/cm33_core0" type="xml">
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<files mask="safety_iec60730b_core0_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_sctimer_16bit_counter" name="sctimer_16bit_counter" brief="The SCTimer 16-bit counter project is a demonstration program of the SDK SCTimer driver operation when using the SCTimer counteras two 16-bit counters.The example toggles an output per counter when a match occurs." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="driver_examples/sctimer" path="boards/lpcxpresso55s69/driver_examples/sctimer/16bit_counter/cm33_core0">
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<external path="boards/lpcxpresso55s69/driver_examples/sctimer/16bit_counter/cm33_core0" type="xml">
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<files mask="sctimer_16bit_counter_v3_10.xml"/>
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@ -1516,122 +1514,6 @@ ${load}</script>
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</example>
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</examples>
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</board>
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<board id="lpcxpresso55s69_om13790host" name="LPCXpresso55S69-OM13790HOST" href="https://www.nxp.com/pip/OM13790" version="1.0.0" package="LPC55S69JBD100" type="kit">
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<description>LPCXpresso Development Board for LPC55S6x family of MCUs with USB Type-C Host Shield Board Gen 2 with Display Port Alt Mode</description>
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<image path="boards/lpcxpresso55s69_om13790host" type="image">
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<files mask="lpcxpresso55s69_om13790host.png"/>
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</image>
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<examples>
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<example id="lpcxpresso55s69_om13790host_usb_pd_alt_mode_dp_host_bm" name="usb_pd_alt_mode_dp_host_bm" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the shield host board (om13790host) to implement the DisplayPort alternate mode.It recognize attached video adapters (like "Type-C to DisplayPort" or "Type-C to HDMI"), and drive the adapter to work." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_alt_mode_dp_host/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_alt_mode_dp_host/bm/cm33_core0" type="xml">
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<files mask="usb_pd_alt_mode_dp_host_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_alt_mode_dp_host_freertos" name="usb_pd_alt_mode_dp_host_freertos" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the shield host board (om13790host) to implement the DisplayPort alternate mode.It recognize attached video adapters (like "Type-C to DisplayPort" or "Type-C to HDMI"), and drive the adapter to work." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_alt_mode_dp_host/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_alt_mode_dp_host/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_alt_mode_dp_host_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_bm" name="usb_pd_bm" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the board keys and debug console to test the PD functions. The demo works as DRP. When connect, the board can be source or sink." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd/bm/cm33_core0" type="xml">
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<files mask="usb_pd_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_charger_battery_bm" name="usb_pd_charger_battery_bm" brief="the application simulate battery product , it prints the battery percent continually. The demo works as DRP. When connect, the board can be source or sink." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_charger_battery/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_charger_battery/bm/cm33_core0" type="xml">
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<files mask="usb_pd_charger_battery_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_charger_battery_freertos" name="usb_pd_charger_battery_freertos" brief="The application simulate battery product, it prints the battery percent continually. The demo works as sink and get power from partner port" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_charger_battery/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_charger_battery/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_charger_battery_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_freertos" name="usb_pd_freertos" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the board keys and debug console to test the PD functions. The demo works as DRP. When connect, the board can be source or sink." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_sink_battery_bm" name="usb_pd_sink_battery_bm" brief="The application simulate battery product , it prints the battery percent continually. The demo works as sink and get power from partner port" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_sink_battery/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_sink_battery/bm/cm33_core0" type="xml">
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<files mask="usb_pd_sink_battery_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_sink_battery_freertos" name="usb_pd_sink_battery_freertos" brief="The application simulate battery product, it prints the battery percent continually. The demo works as sink and get power from partner port" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_sink_battery/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_sink_battery/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_sink_battery_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_source_charger_bm" name="usb_pd_source_charger_bm" brief="The application simulate charger product. The demo only works as source and is external powered" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_source_charger/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_source_charger/bm/cm33_core0" type="xml">
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<files mask="usb_pd_source_charger_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790host_usb_pd_source_charger_freertos" name="usb_pd_source_charger_freertos" brief="The application simulate charger product. The demo only works as source and is external powered" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_source_charger/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790host/usb_examples/usb_pd_source_charger/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_source_charger_freertos_v3_10.xml"/>
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</external>
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</example>
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</examples>
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</board>
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<board id="lpcxpresso55s69_om13790dock" name="LPCXpresso55S69-OM13790DOCK" href="https://www.nxp.com/pip/OM13790" version="1.0.0" package="LPC55S69JBD100" type="kit">
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<description>LPCXpresso Development Board for LPC55S6x family of MCUs with Sensor Toolbox Development Boards for a 9-Axis Solution using FXAS21002C and FXOS8700CQ</description>
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<image path="boards/lpcxpresso55s69_om13790dock" type="image">
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<files mask="lpcxpresso55s69_om13790dock.png"/>
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</image>
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<examples>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_alt_mode_dp_dock_bm" name="usb_pd_alt_mode_dp_dock_bm" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the shield dock board (om13790dock) to implement the DisplayPort alternate mode.It recognize attached video adapters (like "Type-C to DisplayPort" or "Type-C to HDMI"), and drive the adapter to work." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_alt_mode_dp_dock/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_alt_mode_dp_dock/bm/cm33_core0" type="xml">
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<files mask="usb_pd_alt_mode_dp_dock_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_alt_mode_dp_dock_freertos" name="usb_pd_alt_mode_dp_dock_freertos" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the shield dock board (om13790dock) to implement the DisplayPort alternate mode.It recognize attached video adapters (like "Type-C to DisplayPort" or "Type-C to HDMI"), and drive the adapter to work." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_alt_mode_dp_dock/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_alt_mode_dp_dock/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_alt_mode_dp_dock_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_bm" name="usb_pd_bm" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the board keys and debug console to test the PD functions. The demo works as DRP. When connect, the board can be source or sink." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd/bm/cm33_core0" type="xml">
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<files mask="usb_pd_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_charger_battery_bm" name="usb_pd_charger_battery_bm" brief="the application simulate battery product , it prints the battery percent continually. The demo works as DRP. When connect, the board can be source or sink." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_charger_battery/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_charger_battery/bm/cm33_core0" type="xml">
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<files mask="usb_pd_charger_battery_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_charger_battery_freertos" name="usb_pd_charger_battery_freertos" brief="The application simulate battery product, it prints the battery percent continually. The demo works as sink and get power from partner port" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_charger_battery/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_charger_battery/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_charger_battery_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_freertos" name="usb_pd_freertos" brief="This PD example is a simple demonstration based on the MCUXpresso SDK PD stack. The application use the board keys and debug console to test the PD functions. The demo works as DRP. When connect, the board can be source or sink." toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_sink_battery_bm" name="usb_pd_sink_battery_bm" brief="The application simulate battery product , it prints the battery percent continually. The demo works as sink and get power from partner port" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_sink_battery/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_sink_battery/bm/cm33_core0" type="xml">
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<files mask="usb_pd_sink_battery_bm_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_sink_battery_freertos" name="usb_pd_sink_battery_freertos" brief="The application simulate battery product, it prints the battery percent continually. The demo works as sink and get power from partner port" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_sink_battery/freertos/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_sink_battery/freertos/cm33_core0" type="xml">
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<files mask="usb_pd_sink_battery_freertos_v3_10.xml"/>
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</external>
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</example>
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<example id="lpcxpresso55s69_om13790dock_usb_pd_source_charger_bm" name="usb_pd_source_charger_bm" brief="The application simulate charger product. The demo only works as source and is external powered" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_source_charger/bm/cm33_core0">
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<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_source_charger/bm/cm33_core0" type="xml">
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<files mask="usb_pd_source_charger_bm_v3_10.xml"/>
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</external>
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</example>
|
||||
<example id="lpcxpresso55s69_om13790dock_usb_pd_source_charger_freertos" name="usb_pd_source_charger_freertos" brief="The application simulate charger product. The demo only works as source and is external powered" toolchain="armgcc mcuxpresso" compiler="compiler_gcc" category="usb_examples" path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_source_charger/freertos/cm33_core0">
|
||||
<external path="boards/lpcxpresso55s69_om13790dock/usb_examples/usb_pd_source_charger/freertos/cm33_core0" type="xml">
|
||||
<files mask="usb_pd_source_charger_freertos_v3_10.xml"/>
|
||||
</external>
|
||||
</example>
|
||||
</examples>
|
||||
</board>
|
||||
</boards>
|
||||
<devices>
|
||||
<device id="LPC55S69" name="LPC55S69" version="1.0.0" full_name="LPC55S69" family="LPC55S6x" platform="LPC">
|
||||
|
|
@ -1732,72 +1614,6 @@ ${load}</script>
|
|||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="project_template.lpcxpresso55s69_om13790dock.LPC55S69" name="lpcxpresso55s69_om13790dock" brief="BOARD_Project_Template lpcxpresso55s69_om13790dock" version="1.0.0" full_name="BOARD_Project_Template lpcxpresso55s69_om13790dock" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="Board Support/SDK Project Template" user_visible="true" type="project_template" package_base_path="boards/lpcxpresso55s69_om13790dock/project_template" project_base_path="lpcxpresso55s69_om13790dock/project_template">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="platform.drivers.flexcomm_usart.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.flexcomm.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.lpc_iocon.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.lpc_gpio.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.common.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.clock.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.power.LPC55S69"/>
|
||||
<component_dependency value="utility.debug_console.LPC55S69"/>
|
||||
<component_dependency value="platform.devices.LPC55S69_startup.LPC55S69"/>
|
||||
<component_dependency value="component.usart_adapter.LPC55S69"/>
|
||||
<component_dependency value="component.serial_manager_uart.LPC55S69"/>
|
||||
<component_dependency value="component.serial_manager.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="./" type="src">
|
||||
<files mask="board.c"/>
|
||||
<files mask="clock_config.c"/>
|
||||
<files mask="pin_mux.c"/>
|
||||
<files mask="peripherals.c"/>
|
||||
</source>
|
||||
<source relative_path="./" type="c_include">
|
||||
<files mask="board.h"/>
|
||||
<files mask="clock_config.h"/>
|
||||
<files mask="pin_mux.h"/>
|
||||
<files mask="peripherals.h"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="project_template.lpcxpresso55s69_om13790host.LPC55S69" name="lpcxpresso55s69_om13790host" brief="BOARD_Project_Template lpcxpresso55s69_om13790host" version="1.0.0" full_name="BOARD_Project_Template lpcxpresso55s69_om13790host" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="Board Support/SDK Project Template" user_visible="true" type="project_template" package_base_path="boards/lpcxpresso55s69_om13790host/project_template" project_base_path="lpcxpresso55s69_om13790host/project_template">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="platform.drivers.flexcomm_usart.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.flexcomm.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.lpc_iocon.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.lpc_gpio.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.common.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.clock.LPC55S69"/>
|
||||
<component_dependency value="platform.drivers.power.LPC55S69"/>
|
||||
<component_dependency value="utility.debug_console.LPC55S69"/>
|
||||
<component_dependency value="platform.devices.LPC55S69_startup.LPC55S69"/>
|
||||
<component_dependency value="component.usart_adapter.LPC55S69"/>
|
||||
<component_dependency value="component.serial_manager_uart.LPC55S69"/>
|
||||
<component_dependency value="component.serial_manager.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="./" type="src">
|
||||
<files mask="board.c"/>
|
||||
<files mask="clock_config.c"/>
|
||||
<files mask="pin_mux.c"/>
|
||||
<files mask="peripherals.c"/>
|
||||
</source>
|
||||
<source relative_path="./" type="c_include">
|
||||
<files mask="board.h"/>
|
||||
<files mask="clock_config.h"/>
|
||||
<files mask="pin_mux.h"/>
|
||||
<files mask="peripherals.h"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="CMSIS_DSP_Include.LPC55S69" name="CMSIS_DSP_Library_Header" brief="CMSIS-DSP Library Header" version="1.9.0" full_name="CMSIS DSP Library Header" devices="LPC55S69" user_visible="true" type="CMSIS_driver" package_base_path="CMSIS/DSP" project_base_path="CMSIS/DSP">
|
||||
<source exclude="true" relative_path="./" type="other">
|
||||
<files mask="README.md" hidden="true"/>
|
||||
|
|
@ -27681,8 +27497,6 @@ ${load}</script>
|
|||
<files mask="MCUXpresso SDK USB Stack Device Reference Manual.pdf"/>
|
||||
<files mask="MCUXpresso SDK USB Stack Composite Device User's Guide.pdf"/>
|
||||
<files mask="MCUXpresso SDK USB Stack Composite Host User's Guide.pdf"/>
|
||||
<files mask="MCUXpresso SDK USB Type-C PD Stack Reference Manual.pdf"/>
|
||||
<files mask="MCUXpresso SDK USB Type-C Power Delivery Stack User's Guide.pdf"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="docs.fmstr.LPC55S69" name="FreeMASTER" brief="Driver code enabling communication between FreeMASTER or FreeMASTER Lite tools and MCU application. Supports Serial, CAN and BDM/JTAG physical interface." version="3.0.2" full_name="FreeMASTER communication driver" devices="LPC55S69" user_visible="true" type="documentation" package_base_path="middleware/freemaster" project_base_path="freemaster">
|
||||
|
|
@ -27718,17 +27532,6 @@ ${load}</script>
|
|||
<files mask="eRPC Getting Started User's Guide.pdf"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="docs.safety.lpc55sxx.LPC55S69" name="lpc55sxx" brief="Docs safety lpc55sxx" version="1.0.0" full_name="Docs safety lpc55sxx" devices="LPC55S69" user_visible="true" type="documentation" package_base_path="docs/safety" project_base_path="safety">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.safety.LPC55S69"/>
|
||||
</dependencies>
|
||||
<source relative_path="./" type="doc">
|
||||
<files mask="IEC60730B_Example_Release_Notes_v4_3.pdf"/>
|
||||
<files mask="IEC60730B_Example_User_Guide_LPC55Sxx_v4_3.pdf"/>
|
||||
<files mask="IEC60730B_Library_Release_Notes_CM33_v4_3.pdf"/>
|
||||
<files mask="IEC60730B_Library_User_Guide_CM33_v4_3.pdf"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="docs_external.LPC55S69.LPC55S69" name="docs_external.LPC55S69" brief="External documentation for LPC55S69." version="1.0.0" full_name="External documentation" devices="LPC55S69" user_visible="true" type="documentation" package_base_path="docs" project_base_path="docs">
|
||||
<source relative_path="./" type="doc">
|
||||
<files mask="MCUXpresso SDK ChangeLog_LPC55S69.pdf"/>
|
||||
|
|
@ -30351,7 +30154,7 @@ ${load}</script>
|
|||
<files mask="project.yml"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.aws_iot.device_shadow.LPC55S69" name="device-shadow-for-aws-iot-embedded-sdk" brief="Client library for using the AWS IoT Device Shadow service on embedded devices." version="1.0.2" full_name="Device-Shadow-for-AWS-IoT-embedded-sdk" devices="LPC55S69" category="AWS IoT/Device-Shadow-for-AWS-IoT-embedded-sdk" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/device-shadow" project_base_path="aws_iot/device-shadow">
|
||||
<component id="middleware.aws_iot.device_shadow.LPC55S69" name="device_shadow" brief="Client library for using the AWS IoT Device Shadow service on embedded devices." version="1.0.2" full_name="Device Shadow" devices="LPC55S69" category="AWS IoT/Device Shadow" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/device-shadow" project_base_path="aws_iot/device-shadow">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.aws_iot.device_shadow.template.LPC55S69"/>
|
||||
</dependencies>
|
||||
|
|
@ -30370,7 +30173,10 @@ ${load}</script>
|
|||
<include_path relative_path="source/interface" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.aws_iot.device_shadow.template.LPC55S69" name="device_shadow configuration template" brief="Template configuration file to be edited by user." version="1.0.0" full_name="device_shadow configuration template" devices="LPC55S69" category="AWS IoT/Device-Shadow-for-AWS-IoT-embedded-sdk" user_visible="false" type="project_template" package_base_path="middleware/aws_iot/device-shadow" project_base_path="aws_iot/device-shadow">
|
||||
<component id="middleware.aws_iot.device_shadow.template.LPC55S69" name="device_shadow configuration template" brief="Template configuration file to be edited by user." version="1.0.0" full_name="device_shadow configuration template" devices="LPC55S69" category="AWS IoT/Device Shadow" user_visible="false" type="project_template" package_base_path="middleware/aws_iot/device-shadow" project_base_path="aws_iot/device-shadow">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.iot_reference.logging.LPC55S69"/>
|
||||
</dependencies>
|
||||
<source relative_path="template" type="c_include">
|
||||
<files mask="shadow_config.h"/>
|
||||
</source>
|
||||
|
|
@ -30378,7 +30184,7 @@ ${load}</script>
|
|||
<include_path relative_path="template" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.aws_iot.device_shadow.unused.LPC55S69" name="AWS IoT device shadow for_aws - unused files" brief="Client library for using the AWS IoT Device Shadow service on embedded devices. Unused files." version="1.0.2" full_name="Device-Shadow-for-AWS-IoT-embedded-sdk - unused files" devices="LPC55S69" category="AWS IoT/Device-Shadow-for-AWS-IoT-embedded-sdk" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/device-shadow" project_base_path="aws_iot/device-shadow">
|
||||
<component id="middleware.aws_iot.device_shadow.unused.LPC55S69" name="AWS IoT device shadow for_aws - unused files" brief="Client library for using the AWS IoT Device Shadow service on embedded devices. Unused files." version="1.0.2" full_name="Device Shadow - unused files" devices="LPC55S69" category="AWS IoT/Device Shadow" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/device-shadow" project_base_path="aws_iot/device-shadow">
|
||||
<source relative_path="./" type="other">
|
||||
<files mask="CHANGELOG.md"/>
|
||||
<files mask="LICENSE"/>
|
||||
|
|
@ -30501,7 +30307,7 @@ ${load}</script>
|
|||
<files mask="README.md"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.aws_iot.ota.LPC55S69" name="ota-for-aws-iot-embedded-sdk" brief="Client library for using the AWS Over-the-air Update service on embedded devices." version="3.4.0" full_name="ota-for-aws-iot-embedded-sdk" devices="LPC55S69" category="AWS IoT/ota-for-aws-iot-embedded-sdk" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/ota" project_base_path="aws_iot/ota">
|
||||
<component id="middleware.aws_iot.ota.LPC55S69" name="ota-for-aws-iot-embedded-sdk" brief="Client library for using the AWS Over-the-air Update service on embedded devices." version="3.4.0" full_name="ota-for-aws-iot-embedded-sdk" devices="LPC55S69" category="AWS IoT/ota-for-aws-iot-embedded-sdk" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/ota" project_base_path="aws_iot/ota">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="middleware.freertos.corejson.LPC55S69"/>
|
||||
|
|
@ -30539,7 +30345,7 @@ ${load}</script>
|
|||
<include_path relative_path="source/include" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.aws_iot.ota.freertos.LPC55S69" name="ota-for-aws-iot-embedded-sdk - freertos" brief="Client library for using the AWS Over-the-air Update service on embedded devices. FreeRTOS port." version="3.4.0" full_name="ota-for-aws-iot-embedded-sdk - FreeRTOS" devices="LPC55S69" category="AWS IoT/ota-for-aws-iot-embedded-sdk" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/ota" project_base_path="aws_iot/ota">
|
||||
<component id="middleware.aws_iot.ota.freertos.LPC55S69" name="ota-for-aws-iot-embedded-sdk - freertos" brief="Client library for using the AWS Over-the-air Update service on embedded devices. FreeRTOS port." version="3.4.0" full_name="ota-for-aws-iot-embedded-sdk - FreeRTOS" devices="LPC55S69" category="AWS IoT/ota-for-aws-iot-embedded-sdk" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/ota" project_base_path="aws_iot/ota">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
</dependencies>
|
||||
|
|
@ -41848,7 +41654,7 @@ ${load}</script>
|
|||
<include_path relative_path="portable/GCC/ARM_CM33_NTZ/non_secure" toolchain="armgcc mcuxpresso" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.backoffalgorithm.LPC55S69" name="backoffalgorithm" brief="Algorithm for calculating exponential backoff with jitter for network retry attempts." version="1.3.0" full_name="backoffalgorithm" devices="LPC55S69" category="backoffalgorithm/backoffalgorithm" user_visible="true" type="middleware" package_base_path="rtos/freertos/backoffalgorithm" project_base_path="freertos/backoffalgorithm">
|
||||
<component id="middleware.freertos.backoffalgorithm.LPC55S69" name="backoff_algorithm" brief="Algorithm for calculating exponential backoff with jitter for network retry attempts." version="1.3.0" full_name="Backoff Algorithm" devices="LPC55S69" category="AWS IoT/Backoff Algorithm" user_visible="true" type="middleware" package_base_path="rtos/freertos/backoffalgorithm" project_base_path="freertos/backoffalgorithm">
|
||||
<source relative_path="source" type="src">
|
||||
<files mask="backoff_algorithm.c"/>
|
||||
</source>
|
||||
|
|
@ -41862,7 +41668,7 @@ ${load}</script>
|
|||
<include_path relative_path="source/include" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.backoffalgorithm.unused.LPC55S69" name="backoffalgorithm - unused files" brief="Algorithm for calculating exponential backoff with jitter for network retry attempts. Unused files." version="1.3.0" full_name="backoffalgorithm - unused files" devices="LPC55S69" category="backoffalgorithm/backoffalgorithm" user_visible="false" type="middleware" package_base_path="rtos/freertos/backoffalgorithm" project_base_path="freertos/backoffalgorithm">
|
||||
<component id="middleware.freertos.backoffalgorithm.unused.LPC55S69" name="Backoff Algorithm - unused files" brief="Algorithm for calculating exponential backoff with jitter for network retry attempts. Unused files." version="1.3.0" full_name="Backoff Algorithm - unused files" devices="LPC55S69" category="AWS IoT/Backoff Algorithm" user_visible="false" type="middleware" package_base_path="rtos/freertos/backoffalgorithm" project_base_path="freertos/backoffalgorithm">
|
||||
<source relative_path="./" type="script">
|
||||
<files mask="backoffAlgorithmFilePaths.cmake"/>
|
||||
</source>
|
||||
|
|
@ -41924,7 +41730,7 @@ ${load}</script>
|
|||
<files mask="project.yml"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.freertos.corehttp.LPC55S69" name="corehttp" brief="Client implementation of the HTTP/1.1 specification for embedded devices." version="3.0.0" full_name="coreHTTP" devices="LPC55S69" category="AWS IoT/coreHTTP" user_visible="true" type="middleware" package_base_path="rtos/freertos/corehttp" project_base_path="freertos/corehttp">
|
||||
<component id="middleware.freertos.corehttp.LPC55S69" name="corehttp" brief="Client implementation of the HTTP/1.1 specification for embedded devices." version="3.0.0" full_name="coreHTTP" devices="LPC55S69" category="AWS IoT/coreHTTP" user_visible="false" type="middleware" package_base_path="rtos/freertos/corehttp" project_base_path="freertos/corehttp">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.llhttp.LPC55S69"/>
|
||||
</dependencies>
|
||||
|
|
@ -41944,7 +41750,7 @@ ${load}</script>
|
|||
<include_path relative_path="source/interface" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.corehttp.unused.LPC55S69" name="corehttp" brief="Client implementation of the HTTP/1.1 specification for embedded devices." version="3.0.0" full_name="coreHTTP" devices="LPC55S69" category="AWS IoT/coreHTTP" user_visible="true" type="middleware" package_base_path="rtos/freertos/corehttp" project_base_path="freertos/corehttp">
|
||||
<component id="middleware.freertos.corehttp.unused.LPC55S69" name="corehttp" brief="Client implementation of the HTTP/1.1 specification for embedded devices." version="3.0.0" full_name="coreHTTP" devices="LPC55S69" category="AWS IoT/coreHTTP" user_visible="false" type="middleware" package_base_path="rtos/freertos/corehttp" project_base_path="freertos/corehttp">
|
||||
<source relative_path="./" type="other">
|
||||
<files mask="CHANGELOG.md"/>
|
||||
<files mask="LICENSE"/>
|
||||
|
|
@ -42476,7 +42282,7 @@ ${load}</script>
|
|||
<files mask="project.yml"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.freertos.coremqtt.LPC55S69" name="coremqtt" brief="Client implementation of the MQTT 3.1.1 specification for embedded devices." version="2.1.0" full_name="coreMQTT" devices="LPC55S69" category="AWS IoT/coreMQTT" user_visible="true" type="middleware" package_base_path="rtos/freertos/coremqtt" project_base_path="freertos/coremqtt">
|
||||
<component id="middleware.freertos.coremqtt.LPC55S69" name="coremqtt" brief="Client implementation of the MQTT 3.1.1 specification for embedded devices." version="2.1.0" full_name="coreMQTT" devices="LPC55S69" category="AWS IoT/coreMQTT" user_visible="false" type="middleware" package_base_path="rtos/freertos/coremqtt" project_base_path="freertos/coremqtt">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.freertos.coremqtt.template.LPC55S69"/>
|
||||
</dependencies>
|
||||
|
|
@ -42503,7 +42309,7 @@ ${load}</script>
|
|||
<include_path relative_path="source/interface" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.coremqtt-agent.LPC55S69" name="coremqtt-agent" brief="Agent for thread-safe use of coreMQTT." version="1.2.0" full_name="coreMQTT-Agent" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="true" type="middleware" package_base_path="rtos/freertos/coremqtt-agent" project_base_path="freertos/coremqtt-agent">
|
||||
<component id="middleware.freertos.coremqtt-agent.LPC55S69" name="coremqtt-agent" brief="Agent for thread-safe use of coreMQTT." version="1.2.0" full_name="coreMQTT-Agent" devices="LPC55S69" category="AWS IoT/coreMQTT-Agent" user_visible="false" type="middleware" package_base_path="rtos/freertos/coremqtt-agent" project_base_path="freertos/coremqtt-agent">
|
||||
<defines>
|
||||
<define name="MQTT_AGENT_DO_NOT_USE_CUSTOM_CONFIG" value=""/>
|
||||
</defines>
|
||||
|
|
@ -42528,7 +42334,7 @@ ${load}</script>
|
|||
<include_path relative_path="source/include" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.coremqtt-agent.unused.LPC55S69" name="coremqtt-agent - unused files" brief="Agent for thread-safe use of coreMQTT. Unused files." version="1.2.0" full_name="coreMQTT-Agent - unused files" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="false" type="middleware" package_base_path="rtos/freertos/coremqtt-agent" project_base_path="freertos/coremqtt-agent">
|
||||
<component id="middleware.freertos.coremqtt-agent.unused.LPC55S69" name="coremqtt-agent - unused files" brief="Agent for thread-safe use of coreMQTT. Unused files." version="1.2.0" full_name="coreMQTT-Agent - unused files" devices="LPC55S69" category="AWS IoT/coreMQTT-Agent" user_visible="false" type="middleware" package_base_path="rtos/freertos/coremqtt-agent" project_base_path="freertos/coremqtt-agent">
|
||||
<source relative_path="./" type="other">
|
||||
<files mask="CHANGELOG.md"/>
|
||||
<files mask="CODE_OF_CONDUCT.md"/>
|
||||
|
|
@ -43245,7 +43051,7 @@ ${load}</script>
|
|||
<include_path relative_path="source/interface" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.corepkcs11.LPC55S69" name="corepkcs11" brief="Software implementation of the PKCS #11 standard." version="3.5.0" full_name="corePKCS11" devices="LPC55S69" category="AWS IoT/corePKCS11" user_visible="true" type="middleware" package_base_path="rtos/freertos/corepkcs11" project_base_path="freertos/corepkcs11">
|
||||
<component id="middleware.freertos.corepkcs11.LPC55S69" name="corepkcs11" brief="Software implementation of the PKCS #11 standard." version="3.5.0" full_name="corePKCS11" devices="LPC55S69" category="AWS IoT/corePKCS11" user_visible="false" type="middleware" package_base_path="rtos/freertos/corepkcs11" project_base_path="freertos/corepkcs11">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="middleware.pkcs11.LPC55S69"/>
|
||||
|
|
@ -43269,11 +43075,11 @@ ${load}</script>
|
|||
<include_path relative_path="source/include" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.freertos.corepkcs11.mbedtls.LPC55S69" name="corepkcs11 mbedtls" brief="PKCS #11, mbedtls port." version="3.5.0" full_name="corePKCS11 mbedtls" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="AWS IoT/corePKCS11" user_visible="true" type="middleware" package_base_path="rtos/freertos/corepkcs11" project_base_path="freertos/corepkcs11">
|
||||
<component id="middleware.freertos.corepkcs11.mbedtls.LPC55S69" name="corepkcs11 mbedtls" brief="PKCS #11, mbedtls port." version="3.5.0" full_name="corePKCS11 mbedtls" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="AWS IoT/corePKCS11" user_visible="false" type="middleware" package_base_path="rtos/freertos/corepkcs11" project_base_path="freertos/corepkcs11">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="middleware.pkcs11.LPC55S69"/>
|
||||
<component_dependency value="middleware.mbedtls.LPC55S69"/>
|
||||
<component_dependency value="middleware.mbedtls.port.ksdk.LPC55S69"/>
|
||||
<component_dependency value="middleware.freertos.corepkcs11.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="source/portable/mbedtls" type="src">
|
||||
|
|
@ -43283,11 +43089,11 @@ ${load}</script>
|
|||
<files mask="middleware_freertos_corepkcs11_mbedtls_LPC55S69_cm33_core0.cmake" hidden="true"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.freertos.corepkcs11.mbedtls_utils.LPC55S69" name="corepkcs11 mbedtls_utils" brief="PKCS #11, mbedtls_utils" version="3.5.0" full_name="corePKCS11 mbedtls_utils" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="AWS IoT/corePKCS11" user_visible="true" type="middleware" package_base_path="rtos/freertos/corepkcs11" project_base_path="freertos/corepkcs11">
|
||||
<component id="middleware.freertos.corepkcs11.mbedtls_utils.LPC55S69" name="corepkcs11 mbedtls_utils" brief="PKCS #11, mbedtls_utils" version="3.5.0" full_name="corePKCS11 mbedtls_utils" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="AWS IoT/corePKCS11" user_visible="false" type="middleware" package_base_path="rtos/freertos/corepkcs11" project_base_path="freertos/corepkcs11">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="middleware.pkcs11.LPC55S69"/>
|
||||
<component_dependency value="middleware.mbedtls.LPC55S69"/>
|
||||
<component_dependency value="middleware.mbedtls.port.ksdk.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="source/dependency/3rdparty/mbedtls_utils" type="src">
|
||||
|
|
@ -43813,7 +43619,7 @@ ${load}</script>
|
|||
<files mask="README.md"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.iot_reference.cli.LPC55S69" name="cli" brief="CLI, IoT reference common example component" version="1.0.0" full_name="CLI" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/iot-reference/examples/common/cli" project_base_path="aws_iot/iot-reference/examples/common/cli">
|
||||
<component id="middleware.iot_reference.cli.LPC55S69" name="cli" brief="CLI, IoT reference common example component" version="1.0.0" full_name="CLI" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/iot-reference/examples/common/cli" project_base_path="aws_iot/iot-reference/examples/common/cli">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
</dependencies>
|
||||
|
|
@ -43831,9 +43637,13 @@ ${load}</script>
|
|||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.iot_reference.kvstore.LPC55S69" name="kvstore" brief="kvstore, IoT reference common example component" version="1.0.0" full_name="kvstore" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/iot-reference/examples/common/kvstore" project_base_path="aws_iot/iot-reference/examples/common/kvstore">
|
||||
<component id="middleware.iot_reference.kvstore.LPC55S69" name="kvstore" brief="kvstore, IoT reference common example component" version="1.0.0" full_name="kvstore" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="AWS IoT/AWS common libraries" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/iot-reference/examples/common/kvstore" project_base_path="aws_iot/iot-reference/examples/common/kvstore">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
<all>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
<component_dependency value="middleware.iot_reference.template.LPC55S69"/>
|
||||
<component_dependency value="component.mflash_file.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="./" type="src">
|
||||
<files mask="kvstore.c"/>
|
||||
|
|
@ -43866,12 +43676,16 @@ ${load}</script>
|
|||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.iot_reference.mqtt_agent.LPC55S69" name="mqtt_agent" brief="mqtt_agent, IoT reference common example component" version="1.0.0" full_name="mqtt_agent" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/iot-reference/examples/common/mqtt_agent" project_base_path="aws_iot/iot-reference/examples/common/mqtt_agent">
|
||||
<component id="middleware.iot_reference.mqtt_agent.LPC55S69" name="mqtt_agent" brief="mqtt_agent, IoT reference common example component" version="1.0.0" full_name="mqtt_agent" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="AWS IoT/AWS common libraries" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/iot-reference/examples/common/mqtt_agent" project_base_path="aws_iot/iot-reference/examples/common/mqtt_agent">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
<component_dependency value="middleware.iot_reference.mqtt_agent_interface.LPC55S69"/>
|
||||
<component_dependency value="middleware.freertos.backoffalgorithm.LPC55S69"/>
|
||||
<component_dependency value="middleware.freertos.coremqtt-agent.LPC55S69"/>
|
||||
<component_dependency value="middleware.freertos.corepkcs11.LPC55S69"/>
|
||||
<component_dependency value="middleware.iot_reference.kvstore.LPC55S69"/>
|
||||
<component_dependency value="middleware.iot_reference.mqtt_agent_interface.LPC55S69"/>
|
||||
<component_dependency value="middleware.iot_reference.template.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="./" type="src">
|
||||
|
|
@ -43887,9 +43701,12 @@ ${load}</script>
|
|||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.iot_reference.mqtt_agent_interface.LPC55S69" name="mqtt-agent-interface" brief="mqtt-agent-interface, IoT reference common example component" version="1.0.0" full_name="mqtt-agent-interface" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="true" type="middleware" package_base_path="middleware/aws_iot/iot-reference/Middleware/FreeRTOS/mqtt-agent-interface" project_base_path="aws_iot/iot-reference/mqtt-agent-interface">
|
||||
<component id="middleware.iot_reference.mqtt_agent_interface.LPC55S69" name="mqtt-agent-interface" brief="mqtt-agent-interface, IoT reference common example component" version="1.0.0" full_name="mqtt-agent-interface" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="false" type="middleware" package_base_path="middleware/aws_iot/iot-reference/Middleware/FreeRTOS/mqtt-agent-interface" project_base_path="aws_iot/iot-reference/mqtt-agent-interface">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.freertos.coremqtt-agent.LPC55S69"/>
|
||||
<all>
|
||||
<component_dependency value="middleware.freertos.coremqtt-agent.LPC55S69"/>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="./" type="src">
|
||||
<files mask="freertos_agent_message.c"/>
|
||||
|
|
@ -43962,6 +43779,24 @@ ${load}</script>
|
|||
<files mask="middleware_iot_reference_shadow_tasks_LPC55S69_cm33_core0.cmake" hidden="true"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.iot_reference.template.LPC55S69" name="AWS IoT configuration template" brief="Template configuration file to be edited by user." version="1.0.0" full_name="AWS IoT configuration template" devices="LPC55S69" category="AWS IoT/AWS common libraries" user_visible="false" type="project_template" package_base_path="middleware/aws_iot/iot-reference" project_base_path="aws_iot/iot-reference">
|
||||
<defines>
|
||||
<define name="LWIP_DNS" value="1"/>
|
||||
</defines>
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="middleware.freertos-kernel.LPC55S69"/>
|
||||
<component_dependency value="middleware.iot_reference.logging.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="template" type="c_include">
|
||||
<files mask="demo_config.h"/>
|
||||
<files mask="kvstore_config.h"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="template" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.drivers.ads_lpc.LPC55S69" name="ads_lpc" brief="ISSDK Auto Detection Service for LPC Kits" version="1.7.0" full_name="Middleware issdk drivers ads_lpc" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="ads">
|
||||
<source relative_path="drivers/ads/lpc" project_relative_path="./" type="src">
|
||||
<files mask="auto_detection_service.c"/>
|
||||
|
|
@ -43977,7 +43812,7 @@ ${load}</script>
|
|||
<include_path relative_path="drivers/ads" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="cmsis.drivers.include.LPC55S69" name="issdk_cmsis_drivers" brief="CMSIS Core header files" version="1.7.0" full_name="Middleware issdk drivers cmsis_drivers" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="CMSIS/Driver/Include" project_base_path="CMSIS_driver">
|
||||
<component id="cmsis.drivers.include.LPC55S69" name="issdk_cmsis_drivers" brief="CMSIS Core header files" version="1.7.0" full_name="Middleware issdk drivers cmsis_drivers" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="CMSIS/Driver/Include" project_base_path="CMSIS_driver">
|
||||
<source relative_path="./" type="c_include">
|
||||
<files mask="Driver_SPI.h"/>
|
||||
<files mask="Driver_I2C.h"/>
|
||||
|
|
@ -43991,7 +43826,7 @@ ${load}</script>
|
|||
<include_path relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.drivers.gpio_lpc.LPC55S69" name="gpio_lpc" brief="ISSDK GPIO Driver for LPC" version="1.8.0" full_name="Middleware issdk drivers gpio_lpc" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="gpio_driver">
|
||||
<component id="middleware.issdk.drivers.gpio_lpc.LPC55S69" name="gpio_lpc" brief="ISSDK GPIO Driver for LPC" version="1.8.0" full_name="Middleware issdk drivers gpio_lpc" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="gpio_driver">
|
||||
<dependencies>
|
||||
<component_dependency value="cmsis.drivers.include.LPC55S69"/>
|
||||
</dependencies>
|
||||
|
|
@ -44013,7 +43848,7 @@ ${load}</script>
|
|||
<include_path relative_path="drivers/gpio" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.drivers.host.LPC55S69" name="issdk_host" brief="ISSDK Host Interface Service" version="1.7.0" full_name="Middleware issdk drivers host" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="host">
|
||||
<component id="middleware.issdk.drivers.host.LPC55S69" name="issdk_host" brief="ISSDK Host Interface Service" version="1.7.0" full_name="Middleware issdk drivers host" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="host">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="platform.drivers.common.LPC55S69"/>
|
||||
|
|
@ -44058,7 +43893,7 @@ ${load}</script>
|
|||
<include_path relative_path="drivers/systick" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.allregdefs.LPC55S69" name="issdk_allregdefs" brief="ISSDK Sensors RegDefs" version="1.8.0" full_name="Middleware issdk sensor allregdefs" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.allregdefs.LPC55S69" name="issdk_allregdefs" brief="ISSDK Sensors RegDefs" version="1.8.0" full_name="Middleware issdk sensor allregdefs" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44511,7 +44346,7 @@ ${load}</script>
|
|||
<files mask="fxls8974cf_spi.c"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxas21002.LPC55S69" name="issdk_fxas21002" brief="ISSDK FXAS21002 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxas21002" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxas21002.LPC55S69" name="issdk_fxas21002" brief="ISSDK FXAS21002 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxas21002" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44532,7 +44367,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxlc95000.LPC55S69" name="issdk_fxlc95000" brief="ISSDK FXLC95000 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxlc95000" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxlc95000.LPC55S69" name="issdk_fxlc95000" brief="ISSDK FXLC95000 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxlc95000" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44550,7 +44385,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxls8471q.LPC55S69" name="issdk_fxls8471q" brief="ISSDK FXLS8471 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxls8471q" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxls8471q.LPC55S69" name="issdk_fxls8471q" brief="ISSDK FXLS8471 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxls8471q" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44568,7 +44403,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxls8962.LPC55S69" name="issdk_fxls8962" brief="ISSDK FXLS8962 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxls8962" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxls8962.LPC55S69" name="issdk_fxls8962" brief="ISSDK FXLS8962 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxls8962" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44586,7 +44421,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxls896xaf.LPC55S69" name="issdk_fxls896xaf" brief="ISSDK FXLS896xAF Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor FXLS896xAF" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxls896xaf.LPC55S69" name="issdk_fxls896xaf" brief="ISSDK FXLS896xAF Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor FXLS896xAF" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44604,7 +44439,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxls8974cf.LPC55S69" name="issdk_fxls8974cf" brief="ISSDK FXLS8974CF Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor FXLS8974CF" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxls8974cf.LPC55S69" name="issdk_fxls8974cf" brief="ISSDK FXLS8974CF Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor FXLS8974CF" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44622,7 +44457,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxos8700.LPC55S69" name="issdk_fxos8700" brief="ISSDK FXOS8700 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxos8700" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxos8700.LPC55S69" name="issdk_fxos8700" brief="ISSDK FXOS8700 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxos8700" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44643,7 +44478,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.fxpq3115.LPC55S69" name="issdk_fxpq3115" brief="ISSDK FXPQ3115 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxpq3115" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.fxpq3115.LPC55S69" name="issdk_fxpq3115" brief="ISSDK FXPQ3115 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor fxpq3115" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44679,7 +44514,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.interface.common.LPC55S69" name="issdk_interfaces" brief="ISSDK Sensor Interface Common" version="1.7.0" full_name="Middleware issdk sensor interface common" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="interfaces">
|
||||
<component id="middleware.issdk.sensor.interface.common.LPC55S69" name="issdk_interfaces" brief="ISSDK Sensor Interface Common" version="1.7.0" full_name="Middleware issdk sensor interface common" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="interfaces">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44724,7 +44559,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.mag3110.LPC55S69" name="issdk_mag3110" brief="ISSDK MAG3110 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mag3110" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.mag3110.LPC55S69" name="issdk_mag3110" brief="ISSDK MAG3110 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mag3110" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44742,7 +44577,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.mma845x.LPC55S69" name="issdk_mma845x" brief="ISSDK MMA845x Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma845x" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.mma845x.LPC55S69" name="issdk_mma845x" brief="ISSDK MMA845x Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma845x" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44760,7 +44595,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.mma8491q.LPC55S69" name="issdk_mma8491q" brief="ISSDK MMA8491 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma8491q" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.mma8491q.LPC55S69" name="issdk_mma8491q" brief="ISSDK MMA8491 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma8491q" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44778,7 +44613,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.mma865x.LPC55S69" name="issdk_mma865x" brief="ISSDK MMA865x Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma865x" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.mma865x.LPC55S69" name="issdk_mma865x" brief="ISSDK MMA865x Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma865x" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44796,7 +44631,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.mma9553.LPC55S69" name="issdk_mma9553" brief="ISSDK MMA9553 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma9553" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.mma9553.LPC55S69" name="issdk_mma9553" brief="ISSDK MMA9553 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mma9553" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -44814,7 +44649,7 @@ ${load}</script>
|
|||
<include_path relative_path="sensors" project_relative_path="./" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.issdk.sensor.mpl3115.LPC55S69" name="issdk_mpl3115" brief="ISSDK MPL3115 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mpl3115" devices="LPC55S69" user_visible="true" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<component id="middleware.issdk.sensor.mpl3115.LPC55S69" name="issdk_mpl3115" brief="ISSDK MPL3115 Sensor Driver Files" version="1.8.0" full_name="Middleware issdk sensor mpl3115" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/issdk" project_base_path="sensors">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
|
|
@ -53314,95 +53149,6 @@ ${load}</script>
|
|||
<files mask="lpcxpresso55s69_log.txt" hidden="true"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.safety.LPC55S69" name="safety" brief="NXP Safety IEC60730B Library" version="1.0.0" full_name="Middleware safety" devices="LPC55S69" user_visible="true" type="other" package_base_path="middleware/safety_iec60730b" project_base_path="safety_iec60730b">
|
||||
<source relative_path="safety/v4_3/core_test/cm33/register" project_relative_path="safety/register" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_cm33_reg.h"/>
|
||||
<files mask="iec60730b_cm33_reg_dsp_fpu.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/core_test/cm33/ram" project_relative_path="safety/ram" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_cm33_ram.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/core_test/cm33/flash" project_relative_path="safety/flash" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_cm33_flash.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/core_test/cm33/stack" project_relative_path="safety/stack" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_cm33_stack.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/core_test/cm33/programCounter" project_relative_path="safety/programCounter" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_cm33_pc.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/core_test/cm33/programCounter" project_relative_path="safety/programCounter" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_cm33_pc_object.S"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/core_test/cm33" project_relative_path="safety/" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="iec60730b_core.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3" project_relative_path="safety" type="c_include">
|
||||
<files mask="iec60730b.h"/>
|
||||
<files mask="iec60730b_types.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/compiler" project_relative_path="safety/compiler" type="c_include">
|
||||
<files mask="asm_mac_common.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/wdog" project_relative_path="safety/wdog" type="src">
|
||||
<files mask="iec60730b_wdog.c"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/wdog" project_relative_path="safety/wdog" type="c_include">
|
||||
<files mask="iec60730b_wdog.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/tsi" project_relative_path="safety/tsi" type="c_include">
|
||||
<files mask="iec60730b_tsi.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/dio" project_relative_path="safety/dio" type="c_include">
|
||||
<files mask="iec60730b_dio_ext.h"/>
|
||||
<files mask="iec60730b_dio.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/clock" project_relative_path="safety/clock" type="c_include">
|
||||
<files mask="iec60730b_clock.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/aio" project_relative_path="safety/aio" type="c_include">
|
||||
<files mask="iec60730b_aio.h"/>
|
||||
</source>
|
||||
<source relative_path="safety/v4_3/common_test/flash" project_relative_path="safety/flash" type="c_include">
|
||||
<files mask="iec60730b_invariable_memory.h"/>
|
||||
</source>
|
||||
<source toolchain="mcuxpresso" relative_path="safety/v4_3" project_relative_path="safety" type="lib" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="libIEC60730B_M33_MCUX_v4_3.a"/>
|
||||
</source>
|
||||
<source toolchain="mcuxpresso" relative_path="safety/v4_3" project_relative_path="safety" type="lib" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69">
|
||||
<files mask="libIEC60730B_M33_COM_MCUX_v4_3.a"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/register" project_relative_path="safety/register" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/ram" project_relative_path="safety/ram" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/flash" project_relative_path="safety/flash" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/stack" project_relative_path="safety/stack" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/programCounter" project_relative_path="safety/programCounter" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33" project_relative_path="safety/" type="c_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3" project_relative_path="safety/" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/compiler" project_relative_path="safety/compiler" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/wdog" project_relative_path="safety/wdog" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/tsi" project_relative_path="safety/tsi" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/dio" project_relative_path="safety/dio" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/clock" project_relative_path="safety/clock" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/flash" project_relative_path="safety/flash" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/aio" project_relative_path="safety/aio" type="c_include"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/register" project_relative_path="safety/register" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/ram" project_relative_path="safety/ram" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/flash" project_relative_path="safety/flash" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/stack" project_relative_path="safety/stack" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33/programCounter" project_relative_path="safety/programCounter" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3/core_test/cm33" project_relative_path="safety/" type="asm_include" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69"/>
|
||||
<include_path relative_path="safety/v4_3" project_relative_path="safety/" type="asm_include"/>
|
||||
<include_path relative_path="safety/v4_3/compiler" project_relative_path="safety/compiler" type="asm_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/wdog" project_relative_path="safety/wdog" type="asm_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/tsi" project_relative_path="safety/tsi" type="asm_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/dio" project_relative_path="safety/dio" type="asm_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/clock" project_relative_path="safety/clock" type="asm_include"/>
|
||||
<include_path relative_path="safety/v4_3/common_test/aio" project_relative_path="safety/aio" type="asm_include"/>
|
||||
<include_path relative_path="devices/LPC55S69" project_relative_path="LPC55S69" type="asm_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.sdmmc.common.LPC55S69" name="sdmmc_common" brief="Middleware sdmmc common" version="2.3.0" full_name="SDMMC common stack" devices="LPC55S69" category="Memories/SDMMC Stack" user_visible="false" type="middleware" package_base_path="middleware/sdmmc" project_base_path="sdmmc">
|
||||
<source relative_path="common" project_relative_path="inc" type="c_include">
|
||||
<files mask="fsl_sdmmc_spec.h"/>
|
||||
|
|
@ -56283,7 +56029,7 @@ ${load}</script>
|
|||
<files mask="tfm_ipc_client_test.yaml" hidden="true"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.tinycbor.LPC55S69" name="tinycbor" brief="Concise Binary Object Representation (CBOR) Library" version="0.6.0" full_name="TinyCBOR" devices="LPC55S69" category="TinyCBOR/TinyCBOR" user_visible="true" type="middleware" package_base_path="middleware/tinycbor" project_base_path="tinycbor">
|
||||
<component id="middleware.tinycbor.LPC55S69" name="tinycbor" brief="Concise Binary Object Representation (CBOR) Library" version="0.6.0" full_name="TinyCBOR" devices="LPC55S69" category="AWS IoT/TinyCBOR" user_visible="true" type="middleware" package_base_path="middleware/tinycbor" project_base_path="tinycbor">
|
||||
<source relative_path="src" type="c_include">
|
||||
<files mask="cbor.h"/>
|
||||
<files mask="cborinternal_p.h"/>
|
||||
|
|
@ -56304,7 +56050,7 @@ ${load}</script>
|
|||
<include_path relative_path="src" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.tinycbor.unused.LPC55S69" name="tinycbor - unused files" brief="Concise Binary Object Representation (CBOR) Library. Unused files." version="0.6.0" full_name="TinyCBOR - unused files" devices="LPC55S69" category="TinyCBOR/TinyCBOR" user_visible="false" type="middleware" package_base_path="middleware/tinycbor" project_base_path="tinycbor">
|
||||
<component id="middleware.tinycbor.unused.LPC55S69" name="tinycbor - unused files" brief="Concise Binary Object Representation (CBOR) Library. Unused files." version="0.6.0" full_name="TinyCBOR - unused files" devices="LPC55S69" category="AWS IoT/TinyCBOR" user_visible="false" type="middleware" package_base_path="middleware/tinycbor" project_base_path="tinycbor">
|
||||
<source relative_path="./" type="other">
|
||||
<files mask="Doxyfile"/>
|
||||
<files mask="LICENSE"/>
|
||||
|
|
@ -56985,143 +56731,6 @@ ${load}</script>
|
|||
<include_path relative_path="phy" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.usb.pd.LPC55S69" name="PD Stack" brief="Middleware usb_pd" version="2.8.4" full_name="USB Type-C PD Stack" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="USB/USB Type-C PD Stack" user_visible="true" type="middleware" package_base_path="middleware/usb" project_base_path="usb">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.usb.pd.phy.ptn5110.LPC55S69"/>
|
||||
</dependencies>
|
||||
<source relative_path="pd" type="c_include">
|
||||
<files mask="usb_pd.h"/>
|
||||
<files mask="usb_pd_interface.h"/>
|
||||
<files mask="usb_pd_phy.h"/>
|
||||
<files mask="usb_pd_spec.h"/>
|
||||
<files mask="usb_pd_timer.h"/>
|
||||
<files mask="usb_pd_auto_policy.h"/>
|
||||
</source>
|
||||
<source relative_path="pd" type="src">
|
||||
<files mask="usb_pd_connect.c"/>
|
||||
<files mask="usb_pd_interface.c"/>
|
||||
<files mask="usb_pd_msg.c"/>
|
||||
<files mask="usb_pd_policy.c"/>
|
||||
<files mask="usb_pd_timer.c"/>
|
||||
</source>
|
||||
<source toolchain="armgcc" relative_path="." type="workspace" device_cores="cm33_core0_LPC55S69">
|
||||
<files mask="middleware_usb_pd_LPC55S69_cm33_core0.cmake" hidden="true"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="pd" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.usb.pd.altmode.LPC55S69" name="PD Alternate Mode" brief="Middleware usb_pd altmode" version="2.8.4" full_name="USB Type-C PD Alternate Mode" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="USB/USB Type-C PD Stack" user_visible="true" type="middleware" package_base_path="middleware/usb" project_base_path="usb">
|
||||
<dependencies>
|
||||
<component_dependency value="middleware.usb.pd.LPC55S69"/>
|
||||
</dependencies>
|
||||
<source relative_path="pd/alt_mode" project_relative_path="pd/altmode" type="src">
|
||||
<files mask="usb_pd_alt_mode.c"/>
|
||||
<files mask="usb_pd_alt_mode_dp.c"/>
|
||||
</source>
|
||||
<source relative_path="pd/alt_mode" project_relative_path="pd/altmode" type="c_include">
|
||||
<files mask="usb_pd_alt_mode.h"/>
|
||||
<files mask="usb_pd_alt_mode_dp.h"/>
|
||||
</source>
|
||||
<source toolchain="armgcc" relative_path="." type="workspace" device_cores="cm33_core0_LPC55S69">
|
||||
<files mask="middleware_usb_pd_altmode_LPC55S69_cm33_core0.cmake" hidden="true"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="pd/alt_mode" project_relative_path="pd/altmode" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.usb_pd.common_header.LPC55S69" name="USB PD Common Header" brief="Middleware usb pd common_header" version="2.8.4" full_name="USB PD Common Header" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="USB/USB PD Common Header" user_visible="true" type="middleware" package_base_path="middleware/usb" project_base_path="usb">
|
||||
<dependencies>
|
||||
<component_dependency value="component.osa.LPC55S69"/>
|
||||
</dependencies>
|
||||
<source relative_path="include" type="c_include">
|
||||
<files mask="usb.h"/>
|
||||
<files mask="usb_misc.h"/>
|
||||
<files mask="usb_spec.h"/>
|
||||
</source>
|
||||
<source toolchain="armgcc" relative_path="." type="workspace" device_cores="cm33_core0_LPC55S69">
|
||||
<files mask="middleware_usb_pd_common_header_LPC55S69_cm33_core0.cmake" hidden="true"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="include" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.usb.pd.compliance_test_report.LPC55S69" name="PD Compliance Test Report" brief="Middleware usb_pd compliance_test_report" version="2.8.4" full_name="USB Type-C PD Stack" devices="LPC55S69" user_visible="false" type="middleware" package_base_path="middleware/usb" project_base_path="./">
|
||||
<source relative_path="pd/compliance_test_report/ellisys/consumer_provider" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
<source relative_path="pd/compliance_test_report/ellisys/drp" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
<source relative_path="pd/compliance_test_report/ellisys/drp_try_snk" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
<source relative_path="pd/compliance_test_report/ellisys/drp_try_src" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
<source relative_path="pd/compliance_test_report/ellisys/provider_consumer" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
<source relative_path="pd/compliance_test_report/ellisys/displayport_dock" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
<source relative_path="pd/compliance_test_report/ellisys/displayport_host" project_relative_path="./" type="doc">
|
||||
<files mask="USB Compliance Report.html"/>
|
||||
</source>
|
||||
</component>
|
||||
<component id="middleware.usb_pd.config_header.LPC55S69" name="PD Config Header" brief="USB Type-C PD Stack" version="2.8.4" full_name="USB Type-C PD Stack" devices="LPC55S69" user_visible="true" type="project_template" package_base_path="middleware/usb" project_base_path="source">
|
||||
<source relative_path="output/npw/pd_config" project_relative_path="generated" type="c_include">
|
||||
<files mask="usb_pd_config.h"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="output/npw/pd_config" project_relative_path="generated" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="middleware.usb.pd.phy.ptn5110.LPC55S69" name="PD PTN5110 Driver" brief="Middleware usb_pd phy ptn5110" version="2.8.4" full_name="USB Type-C PD Stack" devices="LPC55S69" device_cores="cm33_core0_LPC55S69 cm33_core1_LPC55S69" slave_roles="M33SLAVE" category="USB/USB Type-C PD Stack" user_visible="true" type="middleware" package_base_path="middleware/usb" project_base_path="usb">
|
||||
<dependencies>
|
||||
<all>
|
||||
<component_dependency value="component.flexcomm_i2c_adapter.LPC55S69"/>
|
||||
<component_dependency value="component.lpc_gpio_adapter.LPC55S69"/>
|
||||
<component_dependency value="component.osa.LPC55S69"/>
|
||||
<component_dependency value="middleware.usb_pd.config_header.LPC55S69"/>
|
||||
<component_dependency value="middleware.usb_pd.common_header.LPC55S69"/>
|
||||
</all>
|
||||
</dependencies>
|
||||
<source relative_path="pd/ptn5110" project_relative_path="ptn5110" type="c_include">
|
||||
<files mask="usb_pd_ptn5110.h"/>
|
||||
<files mask="usb_pd_ptn5110_register.h"/>
|
||||
</source>
|
||||
<source relative_path="pd/ptn5110" project_relative_path="ptn5110" type="src">
|
||||
<files mask="usb_pd_ptn5110_connect.c"/>
|
||||
<files mask="usb_pd_ptn5110_hal.c"/>
|
||||
<files mask="usb_pd_ptn5110_interface.c"/>
|
||||
<files mask="usb_pd_ptn5110_msg.c"/>
|
||||
</source>
|
||||
<source relative_path="pd" type="c_include">
|
||||
<files mask="usb_pd.h"/>
|
||||
<files mask="usb_pd_interface.h"/>
|
||||
<files mask="usb_pd_phy.h"/>
|
||||
<files mask="usb_pd_spec.h"/>
|
||||
<files mask="usb_pd_timer.h"/>
|
||||
</source>
|
||||
<source relative_path="pd" type="src">
|
||||
<files mask="usb_pd_timer.c"/>
|
||||
</source>
|
||||
<source relative_path="pd/phy_interface" project_relative_path="phy_interface" type="c_include">
|
||||
<files mask="usb_pd_i2c.h"/>
|
||||
</source>
|
||||
<source relative_path="pd/phy_interface" project_relative_path="phy_interface" type="src">
|
||||
<files mask="usb_pd_i2c.c"/>
|
||||
</source>
|
||||
<source toolchain="armgcc" relative_path="." type="workspace" device_cores="cm33_core0_LPC55S69">
|
||||
<files mask="middleware_usb_pd_phy_ptn5110_LPC55S69_cm33_core0.cmake" hidden="true"/>
|
||||
</source>
|
||||
<include_paths>
|
||||
<include_path relative_path="pd/ptn5110" project_relative_path="ptn5110" type="c_include"/>
|
||||
<include_path relative_path="pd" type="c_include"/>
|
||||
<include_path relative_path="pd/phy_interface" project_relative_path="phy_interface" type="c_include"/>
|
||||
</include_paths>
|
||||
</component>
|
||||
<component id="platform.utilities.misc_utilities.LPC55S69" name="misc_utilities" brief="Utilities which is needed for particular toolchain like the SBRK function required to address limitation between HEAP and STACK in GCC toolchain library." version="1.1.1" full_name="Utilities miscellaneous" devices="LPC55S69" user_visible="true" type="utilities" package_base_path="devices/LPC55S69/utilities" project_base_path="utilities">
|
||||
<source toolchain="armgcc" relative_path="./" type="src">
|
||||
<files mask="fsl_sbrk.c"/>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Release Name: MCUXpresso Software Development Kit (SDK)
|
||||
Release Version: 2.13.0
|
||||
Release Version: 2.13.1
|
||||
Package License: LA_OPT_NXP_Software_License.txt v39 August 2022- Additional Distribution License granted, license in Section 2.3 applies
|
||||
|
||||
SDK_Peripheral_Driver Name: SDK Peripheral Driver
|
||||
|
|
@ -271,29 +271,6 @@ lvgl Name: LVGL
|
|||
Origin: Gabor Kiss-Vamosi
|
||||
Url: https://github.com/lvgl/lvgl
|
||||
|
||||
safety_iec60730b Name: safety iec60730b
|
||||
Version: 4.2
|
||||
Outgoing License: LA_OPT_NXP_Software_License.txt
|
||||
v39 August 2022 - Additional distribution license
|
||||
granted - License in Section 2.3 applies
|
||||
License File: LA_OPT_NXP_Software_License.txt
|
||||
Format: source code & object code & header files
|
||||
Description: Safety IEC60730b Example
|
||||
Location: middleware/safety_iec60730b
|
||||
Origin: NXP
|
||||
|
||||
srecord Name: SRecord 1.64 For Windows
|
||||
Version: 1.64
|
||||
Outgoing License: GPL-3.0
|
||||
License File:
|
||||
tool/srecord/srecord-1.64.zip/srecord-1.64/LICENSE
|
||||
Format: source code & binary
|
||||
Description: Utility for manipulating EPROM load
|
||||
files, is used for postbuild CRC calculation.
|
||||
Location: tools/srecord
|
||||
Origin: Peter Miller
|
||||
Url: http://srecord.sourceforge.net/index.html
|
||||
|
||||
maestro Name: Maestro Audio Framework
|
||||
Version: 1.5.0
|
||||
Outgoing License: LA_OPT_NXP_Software_License.txt
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
// @formatter:off
|
||||
LVM_EQNB_BandDef_t EQNB_BandDefs_UserEq1_internal[LVM_EQNB_MAX_BANDS_NBR] = {
|
||||
{-15, 50, 50}, // gain(dB), freq(Hz) , Qfactor *100
|
||||
|
|
@ -217,7 +217,7 @@ eap_att_control_t att_control = {.attVersion = 4,
|
|||
.volume = 75,
|
||||
.seek_time = 0,
|
||||
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
.controlParam = &ControlParamSet_internal,
|
||||
.instParams = &InstParams_internal,
|
||||
.headroomParams = &HeadroomParams_internal,
|
||||
|
|
@ -232,7 +232,7 @@ eap_att_control_t *get_eap_att_control(void)
|
|||
|
||||
void eap_att_process(void)
|
||||
{
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
if (attProcessIterator++ == 0)
|
||||
{
|
||||
LVM_VersionInfo_st eapVersionInfo;
|
||||
|
|
@ -271,7 +271,6 @@ void eap_att_process(void)
|
|||
}
|
||||
|
||||
att_control.status = kAttRunning;
|
||||
|
||||
att_control.logme("[EAP_ATT] Playback started for %s\r\n", att_control.input);
|
||||
|
||||
break;
|
||||
|
|
@ -308,7 +307,7 @@ void eap_att_process(void)
|
|||
case kAttCmdSeek:
|
||||
att_control.lastError = seek_wrapper(att_control.seek_time);
|
||||
break;
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
case kAttCmdSetConfig:
|
||||
{
|
||||
att_control.logme("[EAP_ATT] Set config\r\n");
|
||||
|
|
@ -355,10 +354,15 @@ void eap_att_process(void)
|
|||
att_control.logme("[EAP_ATT] Error occurred %d for command %d\r\n", att_control.lastError, att_control.command);
|
||||
if (att_control.status == kAttRunning)
|
||||
{
|
||||
att_control.logme("[EAP_ATT] Error occurred, trying to stop...\r\n");
|
||||
stop_wrapper();
|
||||
att_control.logme("[EAP_ATT] Error occurred, playback stopped\r\n");
|
||||
att_control.lastError = kEapAttCodeOk;
|
||||
att_control.status = kAttIdle;
|
||||
}
|
||||
else
|
||||
{
|
||||
att_control.status = kAttError;
|
||||
}
|
||||
att_control.status = kAttError;
|
||||
}
|
||||
|
||||
att_control.command = kAttCmdNone;
|
||||
|
|
@ -449,7 +453,7 @@ eap_att_code_t set_volume(int value)
|
|||
return kEapAttCodeOk; // let implementation on user if needed
|
||||
}
|
||||
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
|
||||
static eap_att_code_t update_wrapper(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -45,10 +45,12 @@
|
|||
#ifndef _EAP_ATT_H_
|
||||
#define _EAP_ATT_H_
|
||||
|
||||
#if defined EAP_PROC
|
||||
#include <EAP16.h>
|
||||
#elif defined EAP32_PROC
|
||||
#ifdef EAP_PROC
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
#include <EAP32.h>
|
||||
#else
|
||||
#include <EAP16.h>
|
||||
#endif
|
||||
#endif
|
||||
#include <stdint.h>
|
||||
|
||||
|
|
@ -61,7 +63,7 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#ifndef MAX_FILE_NAME_LENGTH
|
||||
#define MAX_FILE_NAME_LENGTH 32
|
||||
#define MAX_FILE_NAME_LENGTH 64
|
||||
#endif
|
||||
|
||||
enum
|
||||
|
|
@ -145,7 +147,7 @@ typedef struct _eap_att_control
|
|||
eap_att_code_t (*update)(void); /* This is called when EAP config structures were changed by the tool. */
|
||||
int (*logme)(const char *fmt_s, ...); /* This function is mapped to stdio::printf() by default. */
|
||||
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
eap_att_code_t (*normalize_params)(void); /* Normalizes params definition structures i.e. bands elements count. */
|
||||
|
||||
// EAP references
|
||||
|
|
@ -169,7 +171,7 @@ eap_att_control_t *get_eap_att_control(void);
|
|||
*/
|
||||
void eap_att_process(void);
|
||||
|
||||
#if (defined EAP_PROC || defined EAP32_PROC)
|
||||
#ifdef EAP_PROC
|
||||
/*
|
||||
* Register the LVM handle into EAP ATT control structure when this handle will be available.
|
||||
* Be sure that handle is registered at least immediately after eap_att_control_t.play() handler will be called.
|
||||
|
|
|
|||
|
|
@ -23,6 +23,9 @@ typedef struct _app_data
|
|||
int lastPreset; // buffer for last active preset selection
|
||||
int logEnabled; // enable log to increase debug verbosity
|
||||
ext_proc_args eap_args;
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
uint8_t num_channels; // number of channels set with cli
|
||||
#endif
|
||||
} app_data_t;
|
||||
|
||||
app_data_t *get_app_data();
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include "app_data.h"
|
||||
#include "app_streamer.h"
|
||||
#include "streamer_pcm_app.h"
|
||||
#include "app_definitions.h"
|
||||
#include "main.h"
|
||||
#include "maestro_logging.h"
|
||||
|
||||
|
|
@ -194,7 +195,92 @@ void STREAMER_Stop(streamer_handle_t *handle)
|
|||
ringbuf_clear(audioBuffer);
|
||||
}
|
||||
}
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
status_t STREAMER_PCM_Create(char *filename, int volume)
|
||||
{
|
||||
STREAMER_CREATE_PARAM params;
|
||||
osa_task_def_t thread_attr;
|
||||
ELEMENT_PROPERTY_T prop;
|
||||
int ret;
|
||||
|
||||
eap_att_control_t *control = get_eap_att_control();
|
||||
|
||||
/* Create message process thread */
|
||||
thread_attr.tpriority = OSA_PRIORITY_HIGH;
|
||||
thread_attr.tname = (uint8_t *)STREAMER_MESSAGE_TASK_NAME;
|
||||
thread_attr.pthread = &STREAMER_MessageTask;
|
||||
thread_attr.stacksize = STREAMER_MESSAGE_TASK_STACK_SIZE;
|
||||
ret = OSA_TaskCreate(&msg_thread, &thread_attr, (void *)control);
|
||||
if (KOSA_StatusSuccess != ret)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Create streamer */
|
||||
strcpy(params.out_mq_name, APP_STREAMER_MSG_QUEUE);
|
||||
params.stack_size = STREAMER_TASK_STACK_SIZE;
|
||||
params.task_name = STREAMER_TASK_NAME;
|
||||
#ifdef EAP_PROC
|
||||
if (get_app_data()->num_channels == 2)
|
||||
{
|
||||
params.pipeline_type = STREAM_PIPELINE_PCM_AUDIO_PROC_AUDIO;
|
||||
}
|
||||
else
|
||||
{
|
||||
params.pipeline_type = STREAM_PIPELINE_PCM_AUDIO;
|
||||
}
|
||||
#else
|
||||
params.pipeline_type = STREAM_PIPELINE_PCM_AUDIO;
|
||||
#endif /* EAP_PROC */
|
||||
params.task_name = STREAMER_TASK_NAME;
|
||||
params.in_dev_name = "";
|
||||
params.out_dev_name = "";
|
||||
|
||||
streamer = streamer_create(¶ms);
|
||||
if (!streamer)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
prop.prop = PROP_FILESRC_SET_LOCATION;
|
||||
prop.val = (uintptr_t)filename;
|
||||
|
||||
streamer_set_property(streamer, prop, true);
|
||||
|
||||
prop.prop = PROP_FILESRC_SET_SAMPLE_RATE;
|
||||
prop.val = DEMO_SAMPLE_RATE;
|
||||
|
||||
streamer_set_property(streamer, prop, true);
|
||||
|
||||
prop.prop = PROP_FILESRC_SET_NUM_CHANNELS;
|
||||
prop.val = get_app_data()->num_channels;
|
||||
|
||||
streamer_set_property(streamer, prop, true);
|
||||
|
||||
prop.prop = PROP_FILESRC_SET_BIT_WIDTH;
|
||||
prop.val = DEMO_BIT_WIDTH;
|
||||
|
||||
streamer_set_property(streamer, prop, true);
|
||||
|
||||
prop.prop = PROP_FILESRC_SET_CHUNK_SIZE;
|
||||
prop.val = get_app_data()->num_channels * DEMO_BYTE_WIDTH * DEMO_SAMPLE_RATE / 100;
|
||||
|
||||
streamer_set_property(streamer, prop, true);
|
||||
|
||||
prop.prop = PROP_AUDIOSINK_SET_VOLUME;
|
||||
prop.val = volume;
|
||||
streamer_set_property(streamer, prop, true);
|
||||
|
||||
#ifdef EAP_PROC
|
||||
if (get_app_data()->num_channels == 2)
|
||||
{
|
||||
register_post_process(streamer);
|
||||
}
|
||||
#endif
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
#else
|
||||
status_t STREAMER_file_Create(char *filename, int volume)
|
||||
{
|
||||
STREAMER_CREATE_PARAM params;
|
||||
|
|
@ -217,15 +303,15 @@ status_t STREAMER_file_Create(char *filename, int volume)
|
|||
|
||||
/* Create streamer */
|
||||
strcpy(params.out_mq_name, APP_STREAMER_MSG_QUEUE);
|
||||
params.stack_size = STREAMER_TASK_STACK_SIZE;
|
||||
params.stack_size = STREAMER_TASK_STACK_SIZE;
|
||||
#ifdef EAP_PROC
|
||||
params.pipeline_type = STREAM_PIPELINE_AUDIO_PROC;
|
||||
#else
|
||||
params.pipeline_type = STREAM_PIPELINE_FILESYSTEM;
|
||||
#endif
|
||||
params.task_name = STREAMER_TASK_NAME;
|
||||
params.in_dev_name = "";
|
||||
params.out_dev_name = "";
|
||||
params.task_name = STREAMER_TASK_NAME;
|
||||
params.in_dev_name = "";
|
||||
params.out_dev_name = "";
|
||||
|
||||
streamer = streamer_create(¶ms);
|
||||
if (!streamer)
|
||||
|
|
@ -245,7 +331,7 @@ status_t STREAMER_file_Create(char *filename, int volume)
|
|||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
#endif
|
||||
/* EAP Audio Tuning Tool control integration - START */
|
||||
/* this functions should not be called internally to prevent possible issues caused by broken state machine */
|
||||
eap_att_code_t play()
|
||||
|
|
@ -257,9 +343,12 @@ eap_att_code_t play()
|
|||
// set_debug_level(LOGLVL_DEBUG);
|
||||
// get_debug_state();
|
||||
streamer_pcm_init();
|
||||
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
if (STREAMER_PCM_Create((char *)get_eap_att_control()->input, DEMO_VOLUME) == kStatus_Success)
|
||||
#else
|
||||
if (STREAMER_file_Create((char *)get_eap_att_control()->input, (int)get_eap_att_control()->volume) ==
|
||||
kStatus_Success)
|
||||
#endif
|
||||
{
|
||||
if (streamer_set_state(streamer, 0, STATE_PLAYING, true) == 0)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -51,6 +51,20 @@ extern "C" {
|
|||
*/
|
||||
void STREAMER_Init(void);
|
||||
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
/*!
|
||||
* @brief Create an Maestro streamer interface handle
|
||||
*
|
||||
* This function creates an Maestro streamer interface and starts a task for
|
||||
* handling pcm files
|
||||
*
|
||||
* @param handle Pointer to input handle
|
||||
* @param out sink type
|
||||
* @return kStatus_Success on success, otherwise an error.
|
||||
*/
|
||||
|
||||
status_t STREAMER_PCM_Create(char *filename, int volume);
|
||||
#else
|
||||
/*!
|
||||
* @brief Create an Maestro streamer interface handle
|
||||
*
|
||||
|
|
@ -63,6 +77,7 @@ void STREAMER_Init(void);
|
|||
*/
|
||||
|
||||
status_t STREAMER_file_Create(char *filename, int volume);
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Destroy an Maestro streamer interface handle
|
||||
|
|
|
|||
|
|
@ -80,9 +80,9 @@ set(CMAKE_MODULE_PATH
|
|||
${SdkRootDirPath}/components/i2c
|
||||
${SdkRootDirPath}/middleware/sdmmc
|
||||
${SdkRootDirPath}/devices/LPC55S69/utilities
|
||||
${SdkRootDirPath}/middleware/EAP
|
||||
${SdkRootDirPath}/middleware/maestro
|
||||
${SdkRootDirPath}/middleware/fatfs
|
||||
${SdkRootDirPath}/middleware/EAP
|
||||
${SdkRootDirPath}/middleware/maestro/mcu-audio/opus
|
||||
${SdkRootDirPath}/middleware/maestro/mcu-audio/opusfile
|
||||
${SdkRootDirPath}/middleware/maestro/mcu-audio/ogg
|
||||
|
|
@ -134,6 +134,8 @@ include(driver_lpc_dma_LPC55S69_cm33_core0)
|
|||
|
||||
include(driver_flexcomm_i2s_dma_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_eap_arm_lib_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_freertos-kernel_heap_4_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_maestro_framework_LPC55S69_cm33_core0)
|
||||
|
|
@ -144,8 +146,6 @@ include(middleware_fatfs_sd_LPC55S69_cm33_core0)
|
|||
|
||||
include(middleware_eap_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_eap_arm_lib_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_maestro_framework_opus_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_maestro_framework_opusfile_LPC55S69_cm33_core0)
|
||||
|
|
@ -190,13 +190,13 @@ include(component_osa_free_rtos_LPC55S69_cm33_core0)
|
|||
|
||||
include(driver_sdif_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_maestro_framework_doc_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_maestro_framework_streamer_LPC55S69_cm33_core0)
|
||||
include(middleware_eap16_header_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_eap_exapp_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_eap16_header_LPC55S69_cm33_core0)
|
||||
include(middleware_maestro_framework_doc_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_maestro_framework_streamer_LPC55S69_cm33_core0)
|
||||
|
||||
include(utilities_misc_utilities_LPC55S69_cm33_core0)
|
||||
|
||||
|
|
@ -211,6 +211,10 @@ TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
|
|||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
|
||||
|
||||
if(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/EAP/EAP_Library/libEAP16_3_0_12_FP2_CM33.a)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
|
||||
if(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/maestro/libs/cm33f/armgcc/release/libmp3.a)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
|
|
@ -227,9 +231,9 @@ if(CMAKE_BUILD_TYPE STREQUAL debug)
|
|||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/maestro/libs/cm33f/armgcc/release/libflac.a)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
|
||||
if(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
if(CMAKE_BUILD_TYPE STREQUAL release)
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/EAP/EAP_Library/libEAP16_3_0_12_FP2_CM33.a)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL debug)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL release)
|
||||
|
||||
if(CMAKE_BUILD_TYPE STREQUAL release)
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/maestro/libs/cm33f/armgcc/release/libmp3.a)
|
||||
|
|
@ -247,10 +251,6 @@ if(CMAKE_BUILD_TYPE STREQUAL release)
|
|||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/maestro/libs/cm33f/armgcc/release/libflac.a)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL release)
|
||||
|
||||
if(CMAKE_BUILD_TYPE STREQUAL release)
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../../middleware/EAP/EAP_Library/libEAP16_3_0_12_FP2_CM33.a)
|
||||
endif(CMAKE_BUILD_TYPE STREQUAL release)
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -43,9 +43,9 @@ SET(CMAKE_C_FLAGS_DEBUG " \
|
|||
-DALGORITHM_LIMP=1 \
|
||||
-DALGORITHM_LIMR=1 \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DEAP_PROC \
|
||||
-DSTREAMER_ENABLE_AUDIO_PROC \
|
||||
-DSTREAMER_ENABLE_VIT_SINK \
|
||||
-DEAP_PROC \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DPRINTF_FLOAT_ENABLE=1 \
|
||||
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
|
||||
|
|
@ -102,9 +102,9 @@ SET(CMAKE_C_FLAGS_RELEASE " \
|
|||
-DALGORITHM_LIMP=1 \
|
||||
-DALGORITHM_LIMR=1 \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DEAP_PROC \
|
||||
-DSTREAMER_ENABLE_AUDIO_PROC \
|
||||
-DSTREAMER_ENABLE_VIT_SINK \
|
||||
-DEAP_PROC \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DPRINTF_FLOAT_ENABLE=1 \
|
||||
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include "fsl_shell.h"
|
||||
#include "ff.h"
|
||||
|
||||
#include "app_definitions.h"
|
||||
#include "app_streamer.h"
|
||||
|
||||
#include "eap_att.h"
|
||||
|
|
@ -49,17 +50,25 @@ SHELL_COMMAND_DEFINE(
|
|||
file,
|
||||
"\r\n\"file\": Perform audio file decode and playback\r\n"
|
||||
"\r\n"
|
||||
" USAGE: file [start|stop|pause|seek|volume|"
|
||||
" USAGE: file [start|stop|pause|volume|"
|
||||
#ifndef MULTICHANNEL_EXAMPLE
|
||||
"seek|"
|
||||
#endif
|
||||
#ifdef EAP_PROC
|
||||
"update|set|get|"
|
||||
#endif
|
||||
"track|list|info]\r\n"
|
||||
" start Play default (first found) or specified audio track file.\r\n"
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
" start Play default (first found) file with default (8) channels.\r\n"
|
||||
#else
|
||||
" start Play default (first found) or specified audio track file.\r\n"
|
||||
#endif
|
||||
" stop Stops actual playback.\r\n"
|
||||
" pause Pause actual track or resume if already paused.\r\n"
|
||||
" seek=<seek_time> Seek currently paused track. Seek time is absolute time in milliseconds.\r\n"
|
||||
" volume=<volume> Set volume. The volume can be set from 0 to 100.\r\n"
|
||||
|
||||
#ifndef MULTICHANNEL_EXAMPLE
|
||||
" seek=<seek_time> Seek currently paused track. Seek time is absolute time in milliseconds.\r\n"
|
||||
#endif
|
||||
#ifdef EAP_PROC
|
||||
" update=<preset> Apply current EAP parameters without attribute value\r\n"
|
||||
" or switch to preset 1-"TO_STR(EAP_MAX_PRESET)"\r\n"
|
||||
|
|
@ -68,16 +77,29 @@ SHELL_COMMAND_DEFINE(
|
|||
" get Sync actual EAP parameters from library to ATT config structures.\r\n"
|
||||
|
||||
#endif
|
||||
" track=<filename> Select audio track to play.\r\n"
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
" track <filename> [num_channels] Select audio track to play. Select 2 or 8 channels. \r\n"
|
||||
" - If channel number not specified, default 8 is used. \r\n"
|
||||
#else
|
||||
" track=<filename> Select audio track to play.\r\n"
|
||||
#endif
|
||||
" list List audio files available on mounted SD card.\r\n"
|
||||
" info Prints playback info.\r\n",
|
||||
|
||||
" info Prints playback info.\r\n"
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
" NOTE: Selected audio track must always meet the following parameters:\r\n"
|
||||
" - Sample rate: 96 kHz\r\n"
|
||||
" - Width: 32 bit\r\n"
|
||||
" - Number of channels: Depending on the [num_channels] parameter\r\n"
|
||||
#ifdef EAP_PROC
|
||||
" NOTE: Only when 2 channels are selected EAP can be applied to the audio track."
|
||||
#endif
|
||||
#endif
|
||||
,
|
||||
shellFile,
|
||||
SHELL_IGNORE_PARAMETER_COUNT);
|
||||
|
||||
SDK_ALIGN(static uint8_t s_shellHandleBuffer[SHELL_HANDLE_SIZE], 4);
|
||||
static shell_handle_t s_shellHandle;
|
||||
|
||||
extern serial_handle_t g_serialHandle;
|
||||
extern app_handle_t app;
|
||||
streamer_handle_t streamerHandle;
|
||||
|
|
@ -155,7 +177,9 @@ static shell_status_t shellEcho(shell_handle_t shellHandle, int32_t argc, char *
|
|||
static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char **argv)
|
||||
{
|
||||
char *dot;
|
||||
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
uint8_t num_channels = DEMO_CHANNEL_NUM; // default number of channels is 8
|
||||
#endif
|
||||
shell_status_t retVal = kStatus_SHELL_Success;
|
||||
|
||||
if (!app.sdcardInserted)
|
||||
|
|
@ -166,10 +190,15 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
|
||||
// lock ATT mutex if needed, but based on major usecase it is not necessary
|
||||
// be sure that this routine is as short as possible without any complex logic
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
if (argc >= 2)
|
||||
{
|
||||
#endif
|
||||
if (strcmp(argv[1], "start") == 0)
|
||||
{
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
get_app_data()->num_channels = DEMO_CHANNEL_NUM; // set default channel number = 8
|
||||
#endif
|
||||
get_eap_att_control()->command = kAttCmdStart;
|
||||
}
|
||||
else if (strcmp(argv[1], "stop") == 0)
|
||||
|
|
@ -180,6 +209,7 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
{
|
||||
get_eap_att_control()->command = kAttCmdPause;
|
||||
}
|
||||
#ifndef MULTICHANNEL_EXAMPLE
|
||||
else if (strcmp(argv[1], "seek") == 0)
|
||||
{
|
||||
if ((get_eap_att_control()->status != kAttPaused) && (get_eap_att_control()->status != kAttRunning))
|
||||
|
|
@ -223,6 +253,7 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if defined(EAP_PROC) && (ALGORITHM_XO == 1)
|
||||
else if (strcmp(argv[1], "xo") == 0) // this option is good for testing but could be removed for production
|
||||
{
|
||||
|
|
@ -290,10 +321,10 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
if (argc == 3)
|
||||
{
|
||||
int preset = abs(atoi((argv[2])));
|
||||
if (preset < 0 || preset > EAP_MAX_PRESET)
|
||||
if (preset <= 0 || preset > EAP_MAX_PRESET)
|
||||
{
|
||||
PRINTF("[CMD] EAP preset number out of range, setting EAP all effects OFF.\r\n");
|
||||
preset = 0;
|
||||
preset = 1;
|
||||
}
|
||||
get_eap_att_control()->eapPreset = preset;
|
||||
}
|
||||
|
|
@ -314,19 +345,24 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
{
|
||||
dot = strrchr(argv[2], '.');
|
||||
if (
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
(dot && strncmp(dot + 1, "pcm", 4) == 0)
|
||||
#else
|
||||
#if (OGG_OPUS_DEC == 1)
|
||||
(dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
|
||||
(dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
|
||||
#endif
|
||||
#if (AAC_DEC == 1)
|
||||
(dot && strncmp(dot + 1, "aac", 3) == 0) ||
|
||||
(dot && strncmp(dot + 1, "aac", 3) == 0) ||
|
||||
#endif
|
||||
#if (WAV_DEC == 1)
|
||||
(dot && strncmp(dot + 1, "wav", 3) == 0) ||
|
||||
(dot && strncmp(dot + 1, "wav", 3) == 0) ||
|
||||
#endif
|
||||
#if (FLAC_DEC == 1)
|
||||
(dot && strncmp(dot + 1, "flac", 3) == 0) ||
|
||||
(dot && strncmp(dot + 1, "flac", 3) == 0) ||
|
||||
#endif
|
||||
(dot && strncmp(dot + 1, "mp3", 3) == 0))
|
||||
(dot && strncmp(dot + 1, "mp3", 3) == 0)
|
||||
#endif
|
||||
)
|
||||
{
|
||||
strcpy(get_eap_att_control()->input, argv[2]);
|
||||
get_eap_att_control()->command = kAttCmdStart;
|
||||
|
|
@ -334,22 +370,47 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
else
|
||||
{
|
||||
PRINTF(
|
||||
"[CMD] Input audio file name has to match one of the .mp3"
|
||||
"[CMD] Input audio file name has to match one of the"
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
" .pcm"
|
||||
#else
|
||||
" .mp3"
|
||||
#if (OGG_OPUS_DEC == 1)
|
||||
"|.opus|.ogg"
|
||||
"|.opus|.ogg"
|
||||
#endif
|
||||
#if (AAC_DEC == 1)
|
||||
"|.aac"
|
||||
"|.aac"
|
||||
#endif
|
||||
#if (WAV_DEC == 1)
|
||||
"|.wav"
|
||||
"|.wav"
|
||||
#endif
|
||||
#if (FLAC_DEC == 1)
|
||||
"|.flac"
|
||||
"|.flac"
|
||||
#endif
|
||||
" formats.\r\n");
|
||||
#endif
|
||||
" format.\r\n");
|
||||
|
||||
retVal = kStatus_SHELL_Error;
|
||||
}
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
if (argc == 4)
|
||||
{
|
||||
num_channels = abs(atoi((argv[3])));
|
||||
if (num_channels == 2 || num_channels == 8)
|
||||
{
|
||||
get_app_data()->num_channels = num_channels;
|
||||
}
|
||||
else
|
||||
{
|
||||
PRINTF("Number of channels not allowed (2 or 8 allowed).\r\n");
|
||||
retVal = kStatus_SHELL_Error;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
get_app_data()->num_channels = num_channels;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -387,12 +448,14 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
|
|||
PRINTF("[CMD] Undefined att command option. \r\n");
|
||||
retVal = kStatus_SHELL_Error;
|
||||
}
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
}
|
||||
else
|
||||
{
|
||||
PRINTF("[CMD] Enter correct command option. \r\n");
|
||||
retVal = kStatus_SHELL_Error;
|
||||
}
|
||||
#endif
|
||||
// unlock APP mutex
|
||||
return retVal;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -324,14 +324,14 @@ int EAP_Init(void *arg)
|
|||
|
||||
int EAP_Execute(void *arg, void *inputBuffer, int size)
|
||||
{
|
||||
StreamBuffer *buf = (StreamBuffer *)inputBuffer;
|
||||
int8_t *pkt_hdr_size = arg;
|
||||
AudioPacketHeader *data_packet = NULL;
|
||||
int8_t *data_ptr = NULL;
|
||||
int8_t num_channel = 0;
|
||||
int8_t byte_width = 0;
|
||||
int8_t *outBuffer[NUM_OUT_BUFFES] = {NULL, NULL};
|
||||
LVM_ReturnStatus_en LVM_Status = LVM_SUCCESS;
|
||||
StreamBuffer *buf = (StreamBuffer *)inputBuffer;
|
||||
int8_t *pkt_hdr_size = arg;
|
||||
AudioPacketHeader *data_packet = NULL;
|
||||
int8_t *data_ptr = NULL;
|
||||
int8_t num_channel = 0;
|
||||
int8_t byte_width = 0;
|
||||
int8_t *outBuffer[NUM_OUT_BUFFERS] = {NULL, NULL};
|
||||
LVM_ReturnStatus_en LVM_Status = LVM_SUCCESS;
|
||||
|
||||
if ((buf == NULL) || (pkt_hdr_size == NULL))
|
||||
{
|
||||
|
|
@ -382,7 +382,7 @@ int EAP_Execute(void *arg, void *inputBuffer, int size)
|
|||
}
|
||||
|
||||
eap_xo_out_buf_size = (uint16_t)size;
|
||||
eap_xo_out_buffer = (int8_t *)OSA_MemoryAllocate(size * NUM_OUT_BUFFES + *pkt_hdr_size);
|
||||
eap_xo_out_buffer = (int8_t *)OSA_MemoryAllocate(size * NUM_OUT_BUFFERS + *pkt_hdr_size);
|
||||
if (eap_xo_out_buffer == NULL)
|
||||
{
|
||||
return LVM_NULLADDRESS;
|
||||
|
|
@ -398,11 +398,16 @@ int EAP_Execute(void *arg, void *inputBuffer, int size)
|
|||
|
||||
EAP_AudioTime += LVM_FRAME_SIZE_MS;
|
||||
|
||||
LVM_Status = LVM_Process(EAP_hInstance, /* Instance handle */
|
||||
LVM_Status = LVM_Process(EAP_hInstance, /* Instance handle */
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
(LVM_INT32 *)data_ptr, /* Input buffer */
|
||||
(LVM_INT32 **)outBuffer, /* Output buffer */
|
||||
#else
|
||||
(LVM_INT16 *)data_ptr, /* Input buffer */
|
||||
(LVM_INT16 **)outBuffer, /* Output buffer */
|
||||
size / num_channel, /* Number of samples to process */
|
||||
EAP_AudioTime); /* Audio Time*/
|
||||
#endif
|
||||
size / num_channel, /* Number of samples to process */
|
||||
EAP_AudioTime); /* Audio Time*/
|
||||
|
||||
#if (ALGORITHM_XO == 1)
|
||||
|
||||
|
|
@ -516,9 +521,11 @@ LVM_ReturnStatus_en EAP_SetFSandChannels(ext_proc_args *args)
|
|||
case 48000:
|
||||
control->controlParam->SampleRate = LVM_FS_48000;
|
||||
break;
|
||||
case 96000:
|
||||
control->controlParam->SampleRate = LVM_FS_96000;
|
||||
break;
|
||||
case 64000:
|
||||
case 88200:
|
||||
case 96000:
|
||||
case 128000:
|
||||
case 176400:
|
||||
case 192000:
|
||||
|
|
|
|||
|
|
@ -8,8 +8,13 @@
|
|||
#ifndef _EAP_PROC_H_
|
||||
#define _EAP_PROC_H_
|
||||
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
#include "EAP32.h" // EAP library
|
||||
#else
|
||||
#include "EAP16.h" // EAP library
|
||||
#endif
|
||||
#include "eap_att.h"
|
||||
#include "app_definitions.h"
|
||||
|
||||
#define LVM_FRAME_SIZE_MS (10)
|
||||
|
||||
|
|
@ -17,9 +22,13 @@
|
|||
#define MAX_SAMPLE_SIZE (1024)
|
||||
#endif
|
||||
|
||||
#define NUM_OUT_BUFFES (2)
|
||||
// #define XO_USE_FULL_STEREO /* Define for the full output range of the EAP crossover options when applied to a stereo
|
||||
// audio input file */
|
||||
#define NUM_OUT_BUFFERS (2)
|
||||
|
||||
/* Define for the full output range of the EAP crossover options when applied to a stereo audio input file */
|
||||
// #define XO_USE_FULL_STEREO
|
||||
#if (defined(XO_USE_FULL_STEREO) && (DEMO_CODEC_CS42448 != 1))
|
||||
#error "When full stereo mode is enabled, the CS42448 codec must also be enabled"
|
||||
#endif
|
||||
|
||||
int EAP_Init(void *arg);
|
||||
int EAP_Execute(void *arg, void *inputBuffer, int size);
|
||||
|
|
|
|||
|
|
@ -21,12 +21,12 @@
|
|||
<definition extID="platform.drivers.flexcomm_usart.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpc_dma.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_i2s_dma.LPC55S69"/>
|
||||
<definition extID="middleware.eap.arm.lib.LPC55S69"/>
|
||||
<definition extID="middleware.freertos-kernel.heap_4.LPC55S69"/>
|
||||
<definition extID="middleware.maestro_framework.LPC55S69"/>
|
||||
<definition extID="middleware.fatfs.LPC55S69"/>
|
||||
<definition extID="middleware.fatfs.sd.LPC55S69"/>
|
||||
<definition extID="middleware.eap.LPC55S69"/>
|
||||
<definition extID="middleware.eap.arm.lib.LPC55S69"/>
|
||||
<definition extID="middleware.maestro_framework.opus.LPC55S69"/>
|
||||
<definition extID="middleware.maestro_framework.opusfile.LPC55S69"/>
|
||||
<definition extID="middleware.maestro_framework.ogg.LPC55S69"/>
|
||||
|
|
@ -49,10 +49,10 @@
|
|||
<definition extID="middleware.sdmmc.osa.freertos.LPC55S69"/>
|
||||
<definition extID="component.osa_free_rtos.LPC55S69"/>
|
||||
<definition extID="platform.drivers.sdif.LPC55S69"/>
|
||||
<definition extID="middleware.eap16.header.LPC55S69"/>
|
||||
<definition extID="middleware.eap.exapp.LPC55S69"/>
|
||||
<definition extID="middleware.maestro_framework.doc.LPC55S69"/>
|
||||
<definition extID="middleware.maestro_framework.streamer.LPC55S69"/>
|
||||
<definition extID="middleware.eap.exapp.LPC55S69"/>
|
||||
<definition extID="middleware.eap16.header.LPC55S69"/>
|
||||
<definition extID="platform.utilities.misc_utilities.LPC55S69"/>
|
||||
<definition extID="platform.devices.LPC55S69_system.LPC55S69"/>
|
||||
<definition extID="iar"/>
|
||||
|
|
@ -61,7 +61,7 @@
|
|||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
<definition extID="mdk"/>
|
||||
</externalDefinitions>
|
||||
<example id="lpcxpresso55s69_maestro_playback" name="maestro_playback" device_core="cm33_core0_LPC55S69" dependency="middleware.freertos-kernel.cm33_nonsecure_port.LPC55S69 driver.wm8904.LPC55S69 driver.codec.LPC55S69 platform.drivers.common.LPC55S69 component.wm8904_adapter.LPC55S69 component.codec_i2c.LPC55S69 component.flexcomm_i2c_adapter.LPC55S69 platform.drivers.sysctl.LPC55S69 middleware.sdmmc.sd.LPC55S69 middleware.sdmmc.common.LPC55S69 middleware.sdmmc.host.sdif.LPC55S69 middleware.sdmmc.host.sdif.freertos.LPC55S69 platform.drivers.lpc_iocon.LPC55S69 platform.drivers.flexcomm_i2c.LPC55S69 platform.drivers.flexcomm_i2s.LPC55S69 utility.shell.LPC55S69 platform.drivers.flexcomm_usart.LPC55S69 platform.drivers.lpc_dma.LPC55S69 platform.drivers.flexcomm_i2s_dma.LPC55S69 middleware.freertos-kernel.heap_4.LPC55S69 middleware.maestro_framework.LPC55S69 middleware.fatfs.LPC55S69 middleware.fatfs.sd.LPC55S69 middleware.eap.LPC55S69 middleware.eap.arm.lib.LPC55S69 middleware.maestro_framework.opus.LPC55S69 middleware.maestro_framework.opusfile.LPC55S69 middleware.maestro_framework.ogg.LPC55S69 platform.drivers.clock.LPC55S69 platform.drivers.power.LPC55S69 platform.devices.LPC55S69_CMSIS.LPC55S69 platform.devices.LPC55S69_startup.LPC55S69 platform.drivers.flexcomm.LPC55S69 platform.drivers.lpc_gpio.LPC55S69 platform.utilities.assert.LPC55S69 utility.debug_console.LPC55S69 component.usart_adapter.LPC55S69 component.serial_manager.LPC55S69 component.lists.LPC55S69 component.serial_manager_uart.LPC55S69 middleware.freertos-kernel.LPC55S69 middleware.freertos-kernel.extension.LPC55S69 platform.drivers.reset.LPC55S69 CMSIS_Include_core_cm.LPC55S69 middleware.sdmmc.osa.freertos.LPC55S69 component.osa_free_rtos.LPC55S69 platform.drivers.sdif.LPC55S69 middleware.maestro_framework.doc.LPC55S69 middleware.maestro_framework.streamer.LPC55S69 middleware.eap.exapp.LPC55S69 middleware.eap16.header.LPC55S69 platform.utilities.misc_utilities.LPC55S69 platform.devices.LPC55S69_system.LPC55S69" category="audio_examples">
|
||||
<example id="lpcxpresso55s69_maestro_playback" name="maestro_playback" device_core="cm33_core0_LPC55S69" dependency="middleware.freertos-kernel.cm33_nonsecure_port.LPC55S69 driver.wm8904.LPC55S69 driver.codec.LPC55S69 platform.drivers.common.LPC55S69 component.wm8904_adapter.LPC55S69 component.codec_i2c.LPC55S69 component.flexcomm_i2c_adapter.LPC55S69 platform.drivers.sysctl.LPC55S69 middleware.sdmmc.sd.LPC55S69 middleware.sdmmc.common.LPC55S69 middleware.sdmmc.host.sdif.LPC55S69 middleware.sdmmc.host.sdif.freertos.LPC55S69 platform.drivers.lpc_iocon.LPC55S69 platform.drivers.flexcomm_i2c.LPC55S69 platform.drivers.flexcomm_i2s.LPC55S69 utility.shell.LPC55S69 platform.drivers.flexcomm_usart.LPC55S69 platform.drivers.lpc_dma.LPC55S69 platform.drivers.flexcomm_i2s_dma.LPC55S69 middleware.eap.arm.lib.LPC55S69 middleware.freertos-kernel.heap_4.LPC55S69 middleware.maestro_framework.LPC55S69 middleware.fatfs.LPC55S69 middleware.fatfs.sd.LPC55S69 middleware.eap.LPC55S69 middleware.maestro_framework.opus.LPC55S69 middleware.maestro_framework.opusfile.LPC55S69 middleware.maestro_framework.ogg.LPC55S69 platform.drivers.clock.LPC55S69 platform.drivers.power.LPC55S69 platform.devices.LPC55S69_CMSIS.LPC55S69 platform.devices.LPC55S69_startup.LPC55S69 platform.drivers.flexcomm.LPC55S69 platform.drivers.lpc_gpio.LPC55S69 platform.utilities.assert.LPC55S69 utility.debug_console.LPC55S69 component.usart_adapter.LPC55S69 component.serial_manager.LPC55S69 component.lists.LPC55S69 component.serial_manager_uart.LPC55S69 middleware.freertos-kernel.LPC55S69 middleware.freertos-kernel.extension.LPC55S69 platform.drivers.reset.LPC55S69 CMSIS_Include_core_cm.LPC55S69 middleware.sdmmc.osa.freertos.LPC55S69 component.osa_free_rtos.LPC55S69 platform.drivers.sdif.LPC55S69 middleware.eap16.header.LPC55S69 middleware.eap.exapp.LPC55S69 middleware.maestro_framework.doc.LPC55S69 middleware.maestro_framework.streamer.LPC55S69 platform.utilities.misc_utilities.LPC55S69 platform.devices.LPC55S69_system.LPC55S69" category="audio_examples">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
|
|
@ -82,9 +82,9 @@
|
|||
<value>ALGORITHM_LIMP=1</value>
|
||||
<value>ALGORITHM_LIMR=1</value>
|
||||
<value>CPU_LPC55S69JBD100_cm33_core0</value>
|
||||
<value>EAP_PROC</value>
|
||||
<value>STREAMER_ENABLE_AUDIO_PROC</value>
|
||||
<value>STREAMER_ENABLE_VIT_SINK</value>
|
||||
<value>EAP_PROC</value>
|
||||
<value>PRINTF_ADVANCED_ENABLE=1</value>
|
||||
<value>PRINTF_FLOAT_ENABLE=1</value>
|
||||
<value>DEBUG_CONSOLE_TRANSFER_NON_BLOCKING</value>
|
||||
|
|
|
|||
|
|
@ -151,6 +151,9 @@ status_t list_files(bool autoInput)
|
|||
/* Check file for supported audio extension */
|
||||
dot = strrchr(fileInformation.fname, '.');
|
||||
if (
|
||||
#ifdef MULTICHANNEL_EXAMPLE
|
||||
(dot && strncmp(dot + 1, "pcm", 4) == 0)
|
||||
#else
|
||||
#if (OGG_OPUS_DEC == 1)
|
||||
(dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
|
||||
#endif
|
||||
|
|
@ -163,12 +166,15 @@ status_t list_files(bool autoInput)
|
|||
#if (FLAC_DEC == 1)
|
||||
(dot && strncmp(dot + 1, "flac", 3) == 0) ||
|
||||
#endif
|
||||
(dot && strncmp(dot + 1, "mp3", 3) == 0))
|
||||
(dot && strncmp(dot + 1, "mp3", 3) == 0)
|
||||
#endif
|
||||
)
|
||||
{
|
||||
if (count < MAX_FILES_LIST)
|
||||
{
|
||||
strcpy(get_eap_att_control()->availableInputs[count], fileInformation.fname);
|
||||
PRINTF(" %s\r\n", fileInformation.fname);
|
||||
strncpy(get_eap_att_control()->availableInputs[count], fileInformation.fname,
|
||||
sizeof(get_eap_att_control()->availableInputs[count]));
|
||||
PRINTF(" %s\r\n", get_eap_att_control()->availableInputs[count]);
|
||||
count++;
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -24,6 +24,9 @@
|
|||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#if defined(AAC_DEC) && defined(__ICCARM__)
|
||||
#error "AAC decoder is not enabled in IAR."
|
||||
#endif
|
||||
|
||||
typedef struct _app_handle
|
||||
{
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ Depending on target platform there are different features of the demo enabled.
|
|||
|
||||
- File decoding and playback
|
||||
- EAP effects during file playback
|
||||
- Multi-channel playback
|
||||
|
||||
The application is controlled by commands from a shell interface using serial console.
|
||||
|
||||
|
|
@ -84,6 +85,7 @@ There is limited RAM on this platform, which brings following limitations:
|
|||
- To enable FLAC decoding and playback it is necessary to disable EAP:
|
||||
1. Define FLAC_DEC=1 in the project settings
|
||||
2. Undefine EAP_PROC in the project settings
|
||||
- When playing FLAC audio files with too small frame size (block size), the audio output may be distorted because the board is not fast enough.
|
||||
- The AAC decoder is only supported in MCUXpresso and ARMGCC.
|
||||
Running the demo
|
||||
================
|
||||
|
|
@ -100,3 +102,7 @@ Copyright 2022 NXP
|
|||
[APP_Shell_Task] start
|
||||
|
||||
>> [APP_SDCARD_Task] SD card drive mounted
|
||||
|
||||
Known issues
|
||||
|
||||
1. MP3 decoder has issues with some of the files. One of the channels can be sometimes distorted or missing parts of the signal.
|
||||
|
|
|
|||
|
|
@ -72,25 +72,39 @@ int streamer_pcm_write(pcm_rtos_t *pcm, uint8_t *data, uint32_t size)
|
|||
{
|
||||
/* Ensure write size is a multiple of 32, otherwise EDMA will assert
|
||||
* failure. Round down for the last chunk of a file/stream. */
|
||||
pcm->i2sTxTransfer.dataSize = size - (size % 32);
|
||||
pcm->i2sTxTransfer.data = data;
|
||||
int32_t local_size = size - (size % 32);
|
||||
uint32_t offset = 0;
|
||||
uint16_t dataSize = 0;
|
||||
|
||||
/* Start the consecutive transfer */
|
||||
while (I2S_TxTransferSendDMA(DEMO_I2S_TX, &pcm->i2sTxHandle, pcm->i2sTxTransfer) == kStatus_I2S_Busy)
|
||||
while (local_size > 0)
|
||||
{
|
||||
/* Wait for transfer to finish */
|
||||
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
|
||||
/* Make sure the data size is not larger than 2048 bytes for a oneChannel configuration, as the I2S EDMA driver
|
||||
* does not allow this yet. */
|
||||
dataSize =
|
||||
((pcm->num_channels == 1) && (local_size > 2048)) ? ((local_size - 2048) > 1024 ? 2048 : 1024) : local_size;
|
||||
pcm->i2sTxTransfer.dataSize = pcm->isFirstTx ? (dataSize / 2) : dataSize;
|
||||
pcm->i2sTxTransfer.data = data + offset;
|
||||
local_size -= dataSize;
|
||||
offset += dataSize;
|
||||
|
||||
/* Start the consecutive transfer */
|
||||
while (I2S_TxTransferSendDMA(DEMO_I2S_TX, &pcm->i2sTxHandle, pcm->i2sTxTransfer) == kStatus_I2S_Busy)
|
||||
{
|
||||
return -1;
|
||||
/* Wait for transfer to finish */
|
||||
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (pcm->isFirstTx)
|
||||
{
|
||||
/* Need to queue two transmit buffers so when the first one
|
||||
* finishes transfer, the other immediatelly starts */
|
||||
I2S_TxTransferSendDMA(DEMO_I2S_TX, &pcm->i2sTxHandle, pcm->i2sTxTransfer);
|
||||
pcm->isFirstTx = 0;
|
||||
if (pcm->isFirstTx)
|
||||
{
|
||||
pcm->i2sTxTransfer.data += pcm->i2sTxTransfer.dataSize;
|
||||
/* Need to queue two transmit buffers so when the first one
|
||||
* finishes transfer, the other immediatelly starts */
|
||||
I2S_TxTransferSendDMA(DEMO_I2S_TX, &pcm->i2sTxHandle, pcm->i2sTxTransfer);
|
||||
pcm->isFirstTx = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@
|
|||
#define configSUPPORT_STATIC_ALLOCATION 0
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 1
|
||||
#if ((defined(MIMXRT1051_SERIES) || defined(MIMXRT1052_SERIES) || defined(MIMXRT1041_SERIES) || defined(MIMXRT1042_SERIES)) && defined(VIT_PROC))
|
||||
#define configTOTAL_HEAP_SIZE ((size_t) (478 * 1024))
|
||||
#define configTOTAL_HEAP_SIZE ((size_t) (446 * 1024))
|
||||
#elif ((defined(MIMXRT1051_SERIES) || defined(MIMXRT1052_SERIES) || defined(MIMXRT1041_SERIES) || defined(MIMXRT1042_SERIES)) && !defined(VIT_PROC))
|
||||
#define configTOTAL_HEAP_SIZE ((size_t) (252 * 1024))
|
||||
#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(RW610_SERIES))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* Copyright 2020-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -257,6 +257,17 @@ status_t STREAMER_mic_Create(streamer_handle_t *handle, out_sink_t out_sink, cha
|
|||
}
|
||||
#endif // VIT_PROC
|
||||
|
||||
#if (defined(PLATFORM_RT1170) || defined(PLATFORM_RT1160) || DEMO_CODEC_CS42448)
|
||||
#ifndef VOICE_SEEKER_PROC
|
||||
if (params.pipeline_type == STREAM_PIPELINE_VIT)
|
||||
{
|
||||
PRINTF(
|
||||
"[STREAMER] Please enable VoiceSeeker, it must be used if more than one channel is used and VIT is "
|
||||
"enabled.\r\n");
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(PLATFORM_RT1170) || defined(PLATFORM_RT1160))
|
||||
prop.prop = PROP_AUDIOSRC_SET_FRAME_MS;
|
||||
prop.val = 30;
|
||||
|
|
@ -265,21 +276,19 @@ status_t STREAMER_mic_Create(streamer_handle_t *handle, out_sink_t out_sink, cha
|
|||
prop.prop = PROP_AUDIOSRC_SET_NUM_CHANNELS;
|
||||
prop.val = 2;
|
||||
streamer_set_property(handle->streamer, prop, true);
|
||||
|
||||
prop.prop = PROP_AUDIOSRC_SET_BITS_PER_SAMPLE;
|
||||
prop.val = 32;
|
||||
streamer_set_property(handle->streamer, prop, true);
|
||||
#endif
|
||||
|
||||
#if DEMO_CODEC_CS42448
|
||||
prop.prop = PROP_AUDIOSRC_SET_NUM_CHANNELS;
|
||||
prop.val = 8;
|
||||
streamer_set_property(handle->streamer, prop, true);
|
||||
#endif
|
||||
|
||||
prop.prop = PROP_AUDIOSRC_SET_BITS_PER_SAMPLE;
|
||||
prop.val = 32;
|
||||
streamer_set_property(handle->streamer, prop, true);
|
||||
#endif
|
||||
|
||||
prop.prop = PROP_AUDIOSRC_SET_SAMPLE_RATE;
|
||||
prop.val = 16000;
|
||||
streamer_set_property(handle->streamer, prop, true);
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ SET(CMAKE_C_FLAGS_DEBUG " \
|
|||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DSTREAMER_ENABLE_AUDIO_PROC \
|
||||
-DSTREAMER_ENABLE_VIT_SINK \
|
||||
-DI2S_NUM_BUFFERS=3 \
|
||||
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
|
||||
-DOSA_USED \
|
||||
-DSHELL_TASK_STACK_SIZE=4000 \
|
||||
|
|
@ -42,7 +43,6 @@ SET(CMAKE_C_FLAGS_DEBUG " \
|
|||
-DDEBUG_CONSOLE_RX_ENABLE=0 \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DPRINTF_FLOAT_ENABLE=1 \
|
||||
-DI2S_NUM_BUFFERS=2 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DSDK_OS_FREE_RTOS \
|
||||
-DCASCFG_PLATFORM_FREERTOS \
|
||||
|
|
@ -76,6 +76,7 @@ SET(CMAKE_C_FLAGS_RELEASE " \
|
|||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DSTREAMER_ENABLE_AUDIO_PROC \
|
||||
-DSTREAMER_ENABLE_VIT_SINK \
|
||||
-DI2S_NUM_BUFFERS=3 \
|
||||
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
|
||||
-DOSA_USED \
|
||||
-DSHELL_TASK_STACK_SIZE=4000 \
|
||||
|
|
@ -86,7 +87,6 @@ SET(CMAKE_C_FLAGS_RELEASE " \
|
|||
-DDEBUG_CONSOLE_RX_ENABLE=0 \
|
||||
-DPRINTF_ADVANCED_ENABLE=1 \
|
||||
-DPRINTF_FLOAT_ENABLE=1 \
|
||||
-DI2S_NUM_BUFFERS=2 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DSDK_OS_FREE_RTOS \
|
||||
-DCASCFG_PLATFORM_FREERTOS \
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@
|
|||
<value>CPU_LPC55S69JBD100_cm33_core0</value>
|
||||
<value>STREAMER_ENABLE_AUDIO_PROC</value>
|
||||
<value>STREAMER_ENABLE_VIT_SINK</value>
|
||||
<value>I2S_NUM_BUFFERS=3</value>
|
||||
<value>DEBUG_CONSOLE_TRANSFER_NON_BLOCKING</value>
|
||||
<value>OSA_USED</value>
|
||||
<value>SHELL_TASK_STACK_SIZE=4000</value>
|
||||
|
|
@ -74,7 +75,6 @@
|
|||
<value>DEBUG_CONSOLE_RX_ENABLE=0</value>
|
||||
<value>PRINTF_ADVANCED_ENABLE=1</value>
|
||||
<value>PRINTF_FLOAT_ENABLE=1</value>
|
||||
<value>I2S_NUM_BUFFERS=2</value>
|
||||
<value>SERIAL_PORT_TYPE_UART=1</value>
|
||||
<value>SDK_OS_FREE_RTOS</value>
|
||||
<value>CASCFG_PLATFORM_FREERTOS</value>
|
||||
|
|
|
|||
|
|
@ -40,6 +40,10 @@ Type "help" to see the command list. Similar description will be displayed on se
|
|||
|
||||
For custom VIT model generation (defining own wake words and voice commands) please use https://vit.nxp.com/
|
||||
|
||||
Note:
|
||||
- If more than one channel is used and VIT is enabled, please enable VoiceSeeker.
|
||||
- The VoiceSeeker that combines multiple channels into one must be used, as VIT can only work with one channel.
|
||||
|
||||
|
||||
Toolchain supported
|
||||
===================
|
||||
|
|
|
|||
|
|
@ -60,6 +60,10 @@ void streamer_pcm_start(pcm_rtos_t *pcm)
|
|||
{
|
||||
/* Interrupts already enabled - nothing to do.
|
||||
* App/streamer can begin writing data to SAI. */
|
||||
if (pcm->isFirstTx == 1)
|
||||
{
|
||||
I2S_Enable(DEMO_I2S_TX);
|
||||
}
|
||||
}
|
||||
|
||||
void streamer_pcm_close(pcm_rtos_t *pcm)
|
||||
|
|
@ -129,7 +133,9 @@ int streamer_pcm_read(pcm_rtos_t *pcm, uint8_t *data, uint32_t size)
|
|||
{
|
||||
/* Wait for the previous transfer to finish */
|
||||
if (xSemaphoreTake(pcm->semaphoreRX, portMAX_DELAY) != pdTRUE)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Start the consecutive transfer */
|
||||
|
|
@ -232,7 +238,7 @@ int streamer_pcm_setparams(
|
|||
I2S_TxInit(DEMO_I2S_TX, &pcmHandle.tx_config);
|
||||
}
|
||||
}
|
||||
ret = CODEC_SetMute(&codecHandle, kCODEC_PlayChannelHeadphoneLeft | kCODEC_PlayChannelHeadphoneRight, true);
|
||||
|
||||
ret = streamer_pcm_set_volume(pcm, 0);
|
||||
if (ret != kStatus_Success)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -28,13 +28,9 @@ After running the "usb_mic" command, the USB device will be enumerated on your h
|
|||
User will see the volume levels obtained from the USB host as in the example below.
|
||||
This is just an example application. To leverage the values, the demo has to be modified.
|
||||
|
||||
Note
|
||||
1. When connected to MacBook, change the PCM format from (0x02,0x00,) to (0x01,0x00, ) in
|
||||
g_config_descriptor[CONFIG_DESC_SIZE] in the usb_descriptor.c. Otherwise, it can't be enumerated and
|
||||
noise is present when recording with the QuickTime player because the sampling frequency and bit resolution
|
||||
do not match.
|
||||
2. When device functionality is changed, please uninstall the previous PC driver to make sure the device with changed functionality can run normally.
|
||||
3. If you're having audio problems on Windows 10 for recorder, please disable signal enhancement as the following if it is enabled and have a try again.
|
||||
Notes
|
||||
1. When device functionality is changed, please uninstall the previous PC driver to make sure the device with changed functionality can run normally.
|
||||
2. If you're having audio problems on Windows 10 for recorder, please disable signal enhancement as the following if it is enabled and have a try again.
|
||||
|
||||
|
||||
Toolchain supported
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,117 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2007-2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2018-2019 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* FreeMASTER Communication Driver - User Configuration File
|
||||
*/
|
||||
|
||||
#ifndef FREEMASTER_CFG_H
|
||||
#define FREEMASTER_CFG_H
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define FMSTR_PLATFORM_CORTEX_M 1 /* Cortex-M platform (see freemaster.h for list of all supported platforms) */
|
||||
|
||||
//! Set the demo configuration
|
||||
#define FMSTR_DEMO_ENOUGH_ROM 1 /* Platform has enough ROM to show most of the FreeMASTER features */
|
||||
#define FMSTR_DEMO_LARGE_ROM \
|
||||
1 /* Platform has large ROM enough to store the extended data structures used in FreeMASTER demo */
|
||||
#define FMSTR_DEMO_SUPPORT_I64 1 /* support for long long type */
|
||||
#define FMSTR_DEMO_SUPPORT_FLT 1 /* support for float type */
|
||||
#define FMSTR_DEMO_SUPPORT_DBL 1 /* support for double type */
|
||||
|
||||
//! Enable/Disable FreeMASTER functionalities
|
||||
#define FMSTR_DISABLE 0 //!< To disable all FreeMASTER functionalities
|
||||
|
||||
//! Select interrupt or poll-driven serial communication
|
||||
#define FMSTR_LONG_INTR 0 //!< Complete message processing in interrupt
|
||||
#define FMSTR_SHORT_INTR 0 //!< Queuing done in interrupt
|
||||
#define FMSTR_POLL_DRIVEN 1 //!< No interrupt needed, polling only
|
||||
|
||||
//! Select communication interface
|
||||
|
||||
//! List of implemented standard FreeMASTER transports and its drivers
|
||||
//!< FMSTR_SERIAL - Standard serial transport protocol (Used by various types of UART peripherals as USB CDC
|
||||
//!< implementation)
|
||||
//!< FMSTR_SERIAL_MCUX_UART - MCUXSDK driver for UART peripheral
|
||||
//!< FMSTR_SERIAL_MCUX_LPUART - MCUXSDK driver for LPUART peripheral
|
||||
//!< FMSTR_SERIAL_MCUX_USART - MCUXSDK driver for USART peripheral
|
||||
//!< FMSTR_SERIAL_MCUX_MINIUSART -MCUXSDK driver for MINIUSART peripheral
|
||||
//!< FMSTR_SERIAL_MCUX_USB - MCUXSDK driver for USB peripheral with CDC class
|
||||
//!< FMSTR_CAN - Standard CAN transport protocol (Used by various types of CAN peripherals)
|
||||
//!< FMSTR_CAN_MCUX_FLEXCAN - MCUXSDK driver for FlexCAN peripheral
|
||||
//!< FMSTR_CAN_MCUX_MCAN - MCUXSDK driver for MCAN peripheral
|
||||
//!< FMSTR_CAN_MCUX_MSCAN - MCUXSDK driver for msCAN peripheral
|
||||
//!< FMSTR_PDBDM - Packet Driven BDM (Background debug memory access using JTAG, SWD or BDM debug probes). This
|
||||
//!< transport does not use low-level driver.
|
||||
|
||||
#define FMSTR_TRANSPORT FMSTR_SERIAL //!< Use serial transport layer */
|
||||
#define FMSTR_SERIAL_DRV FMSTR_SERIAL_MCUX_USART //!< Use serial driver for USART */
|
||||
|
||||
//! Define communication interface base address or leave undefined for runtime setting
|
||||
// #undef FMSTR_SERIAL_BASE //!< Serial base will be assigned in runtime (when FMSTR_USE_UART)
|
||||
// #undef FMSTR_CAN_BASE //!< CAN base will be assigned in runtime (when FMSTR_USE_FLEXCAN)
|
||||
|
||||
//! FlexCAN-specific, communication message buffers
|
||||
#define FMSTR_FLEXCAN_TXMB 0
|
||||
#define FMSTR_FLEXCAN_RXMB 1
|
||||
|
||||
//! Input/output communication buffer size
|
||||
#define FMSTR_COMM_BUFFER_SIZE 0 //!< Set to 0 for "automatic"
|
||||
|
||||
//! Receive FIFO queue size (use with FMSTR_SHORT_INTR only)
|
||||
#define FMSTR_COMM_RQUEUE_SIZE 32 //!< Set to 0 for "default"
|
||||
|
||||
//! Support for Application Commands
|
||||
#define FMSTR_USE_APPCMD 1 //!< Enable/disable App.Commands support
|
||||
#define FMSTR_APPCMD_BUFF_SIZE 32 //!< App.Command data buffer size
|
||||
#define FMSTR_MAX_APPCMD_CALLS 4 //!< How many app.cmd callbacks? (0=disable)
|
||||
|
||||
//! Oscilloscope support
|
||||
#define FMSTR_USE_SCOPE 2 //!< Specify number of supported oscilloscopes
|
||||
#define FMSTR_MAX_SCOPE_VARS 8 //!< Specify maximum number of scope variables per one oscilloscope
|
||||
|
||||
//! Recorder support
|
||||
#define FMSTR_USE_RECORDER 2 //!< Specify number of supported recorders
|
||||
|
||||
//! Built-in recorder buffer
|
||||
#define FMSTR_REC_BUFF_SIZE 1024 //!< Built-in buffer size. Set to zero to disable using embedded buffer for recorder 0.
|
||||
|
||||
//! Recorder time base, specifies how often the recorder is called in the user app.
|
||||
#define FMSTR_REC_TIMEBASE FMSTR_REC_BASE_MILLISEC(0) //!< 0 = "unknown"
|
||||
#define FMSTR_REC_FLOAT_TRIG 1 //!< Enable/disable floating point triggering
|
||||
|
||||
//!< Target-side address translation (TSA)
|
||||
#define FMSTR_USE_TSA 0 //!< Enable TSA functionality
|
||||
#define FMSTR_USE_TSA_INROM 1 //!< TSA tables declared as const (put to ROM)
|
||||
#define FMSTR_USE_TSA_SAFETY 1 //!< Enable/Disable TSA memory protection
|
||||
#define FMSTR_USE_TSA_DYNAMIC 1 //!< Enable/Disable TSA entries to be added also in runtime
|
||||
|
||||
//!< Pipes as data streaming over FreeMASTER protocol
|
||||
#define FMSTR_USE_PIPES 3 //!< Specify number of supported pipe objects
|
||||
|
||||
//!< Enable/Disable read/write memory commands
|
||||
#define FMSTR_USE_READMEM 1 //!< Enable read memory commands
|
||||
#define FMSTR_USE_WRITEMEM 1 //!< Enable write memory commands
|
||||
#define FMSTR_USE_WRITEMEMMASK 1 //!< Enable write memory bits commands
|
||||
|
||||
// Define password for access levels to protect them. AVOID SHORT PASSWORDS in production version.
|
||||
// Passwords should be at least 20 characters long to prevent dictionary attacks.
|
||||
// #define FMSTR_RESTRICTED_ACCESS_RWF_PASSWORD "rwf"
|
||||
// #define FMSTR_RESTRICTED_ACCESS_RW_PASSWORD "rw"
|
||||
// #define FMSTR_RESTRICTED_ACCESS_R_PASSWORD "r"
|
||||
|
||||
// Storing cleartext passwords in Flash memory is not safe, consider storing their SHA1 hash instead
|
||||
// Even with this option, the hash must be generated from reasonably complex password to prevent dictionary attack.
|
||||
#define FMSTR_USE_HASHED_PASSWORDS \
|
||||
0 //!< When non-zero, the passwords above are specified as a pointer to 20-byte SHA1 hash of password text
|
||||
|
||||
#endif /* FREEMASTER_CFG_H */
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _ISR_H_
|
||||
#define _ISR_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#undef VECTOR_015
|
||||
#define VECTOR_015 SYSTICK_Isr
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
extern void SYSTICK_Isr(void);
|
||||
|
||||
#endif /* _ISR_H_ */
|
||||
|
|
@ -1,368 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "safety_config.h"
|
||||
#if FMSTR_SERIAL_ENABLE
|
||||
#include "freemaster.h"
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
void SYSTICK_Isr(void);
|
||||
void safety_dio_runtime(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* Start and end addresses for March test applied to Stack area */
|
||||
extern const uint32_t c_stackTestFirstAddress; /* defined in safety_*.c */
|
||||
extern const uint32_t c_stackTestSecondAddress; /* defined in safety_*.c */
|
||||
|
||||
/* Test variable */
|
||||
volatile uint32_t counter = 0;
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__) /* IAR */
|
||||
#pragma section = ".safety_ram"
|
||||
#pragma section = ".pctest"
|
||||
|
||||
wd_test_t g_sSafetyWdTest @ ".safety_ram";
|
||||
safety_common_t g_sSafetyCommon @ ".safety_ram";
|
||||
fs_flash_runtime_test_parameters_t g_sFlashCrc @ ".safety_ram";
|
||||
fs_flash_configuration_parameters_t g_sFlashConfig @ ".safety_ram";
|
||||
fs_ram_test_t g_sSafetyRamTest @ ".safety_ram";
|
||||
fs_ram_test_t g_sSafetyRamStackTest @ ".safety_ram";
|
||||
fs_clock_test_t g_sSafetyClockTest @ ".safety_ram";
|
||||
|
||||
#elif (defined(__GNUC__) && ( __ARMCC_VERSION >= 6010050)) /* KEIL */
|
||||
#include "linker_config.h"
|
||||
|
||||
/* The safety-related RAM border marker. */
|
||||
extern uint32_t Image$$SafetyRam_region$$Limit;
|
||||
|
||||
uint32_t stack_pointer_addr = (uint32_t)__BOOT_STACK_ADDRESS;
|
||||
|
||||
uint16_t crcPostbuild; /* Checksum result calculated by srec_cat.exe in post-build phase */
|
||||
|
||||
wd_test_t g_sSafetyWdTest __attribute__((section(".safety_ram")));
|
||||
safety_common_t g_sSafetyCommon __attribute__((section(".safety_ram")));
|
||||
fs_clock_test_t g_sSafetyClockTest __attribute__((section(".safety_ram")));
|
||||
fs_ram_test_t g_sSafetyRamTest __attribute__((section(".safety_ram")));
|
||||
fs_ram_test_t g_sSafetyRamStackTest __attribute__((section(".safety_ram")));
|
||||
fs_flash_runtime_test_parameters_t g_sFlashCrc __attribute__((section(".safety_ram")));
|
||||
fs_flash_configuration_parameters_t g_sFlashConfig __attribute__((section(".safety_ram")));
|
||||
|
||||
#else /* MCUXpresso */
|
||||
|
||||
uint16_t crcPostbuild; /* Checksum result calculated by srec_cat.exe in post-build phase */
|
||||
|
||||
extern uint32_t __BOOT_STACK_ADDRESS; /* from Linker command file */
|
||||
uint32_t stack_pointer_addr = (uint32_t)&__BOOT_STACK_ADDRESS;
|
||||
|
||||
extern uint32_t m_sec_fs_ram_start; /* from Linker command file */
|
||||
uint32_t pui32SafetyRamSectionStart = (uint32_t)&m_sec_fs_ram_start;
|
||||
|
||||
extern uint32_t m_sec_fs_ram_end; /* from Linker command file */
|
||||
uint32_t pui32SafetyRamSectionEnd = (uint32_t)&m_sec_fs_ram_end;
|
||||
|
||||
wd_test_t g_sSafetyWdTest __attribute__((section(".safety_ram")));
|
||||
safety_common_t g_sSafetyCommon __attribute__((section(".safety_ram")));
|
||||
fs_clock_test_t g_sSafetyClockTest __attribute__((section(".safety_ram")));
|
||||
fs_ram_test_t g_sSafetyRamTest __attribute__((section(".safety_ram")));
|
||||
fs_ram_test_t g_sSafetyRamStackTest __attribute__((section(".safety_ram")));
|
||||
fs_flash_runtime_test_parameters_t g_sFlashCrc __attribute__((section(".safety_ram")));
|
||||
fs_flash_configuration_parameters_t g_sFlashConfig __attribute__((section(".safety_ram")));
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief main function
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
int32_t main(void)
|
||||
{
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
/* Clock initialization */
|
||||
ClockInit();
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
/* Pin initialization */
|
||||
BOARD_InitBootPins();
|
||||
|
||||
/* Watchdog test */
|
||||
SafetyWatchdogTest(&g_sSafetyCommon, &g_sSafetyWdTest);
|
||||
|
||||
g_sSafetyCommon.safetyErrors = 0; /* clear the variable that records safety error codes */
|
||||
g_sSafetyCommon.fastIsrSafetySwitch = 0;
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__) /* IAR */
|
||||
uint32_t *safetyRamStart = __section_begin(".safety_ram");
|
||||
uint32_t *safetyRamEnd = __section_end(".safety_ram");
|
||||
|
||||
#elif (defined(__GNUC__) && (__ARMCC_VERSION >= 6010050)) /* KEIL */
|
||||
uint32_t *safetyRamStart = (uint32_t *)m_safety_ram_start;
|
||||
uint32_t *safetyRamEnd = (uint32_t *)&Image$$SafetyRam_region$$Limit;
|
||||
|
||||
#else /* MCUXpresso */
|
||||
uint32_t *safetyRamStart = (uint32_t *)pui32SafetyRamSectionStart;
|
||||
uint32_t *safetyRamEnd = (uint32_t *)pui32SafetyRamSectionEnd;
|
||||
#endif
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
#if FMSTR_SERIAL_ENABLE
|
||||
SerialInit();
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
FMSTR_Init();/* initialize freemaster */
|
||||
#endif /* FMSTR_SERIAL_ENABLE */
|
||||
|
||||
/* Flash test init */
|
||||
SafetyFlashTestInit(&g_sFlashCrc, &g_sFlashConfig);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
#if FLASH_TEST_ENABLED
|
||||
/* After-reset flash test */
|
||||
SafetyFlashAfterResetTest(&g_sSafetyCommon, &g_sFlashConfig);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
#endif /* FLASH_TEST_ENABLED */
|
||||
|
||||
/* Ram test init for Safety related RAM space */
|
||||
SafetyRamTestInit(&g_sSafetyRamTest, safetyRamStart, safetyRamEnd);
|
||||
|
||||
/* Ram test init for Stack memory */
|
||||
SafetyRamTestInit(&g_sSafetyRamStackTest, (uint32_t *)c_stackTestFirstAddress,
|
||||
(uint32_t *)c_stackTestSecondAddress);
|
||||
|
||||
/* Ram after-reset test for safety related memory*/
|
||||
SafetyRamAfterResetTest(&g_sSafetyCommon, &g_sSafetyRamTest);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
/* Ram after-reset test for Stack area */
|
||||
SafetyRamAfterResetTest(&g_sSafetyCommon, &g_sSafetyRamStackTest);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
#if PC_TEST_ENABLED
|
||||
/* Program Counter test */
|
||||
SafetyPcTest(&g_sSafetyCommon, PC_TEST_PATTERN);
|
||||
#endif
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
/* CPU test after */
|
||||
SafetyCpuAfterResetTest(&g_sSafetyCommon);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
/* initialize Stack test */
|
||||
SafetyStackTestInit();
|
||||
|
||||
/* Stack overflow and underflow test */
|
||||
SafetyStackTest(&g_sSafetyCommon);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
#if ADC_TEST_ENABLED
|
||||
AdcInit();
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
/* After-reset ADC test */
|
||||
for (uint8_t i = 0; i < 6; i++) /* each odd iteration is init phase */
|
||||
{
|
||||
for (uint8_t y = 0; y < 40; y++)
|
||||
__asm("nop"); /* delay because of conversion time */
|
||||
SafetyAnalogTest(&g_sSafetyCommon);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
}
|
||||
#endif /* ADC_TEST_ENABLED */
|
||||
|
||||
#if DIO_TEST_ENABLED
|
||||
/* Digital I/O test */
|
||||
|
||||
for (int i = 0; g_dio_safety_test_items[i] != 0; i++)
|
||||
{
|
||||
|
||||
#ifndef _MIMXRT1189_CM33_H_
|
||||
SafetyDigitalOutputTest(&g_sSafetyCommon, g_dio_safety_test_items[i]);
|
||||
#endif
|
||||
|
||||
SafetyDigitalInputOutput_ShortSupplyTest(&g_sSafetyCommon, g_dio_safety_test_items[i], DIO_SHORT_TO_GND_TEST);
|
||||
SafetyDigitalInputOutput_ShortSupplyTest(&g_sSafetyCommon, g_dio_safety_test_items[i], DIO_SHORT_TO_VDD_TEST);
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
}
|
||||
|
||||
SafetyDigitalInputOutput_ShortAdjTest(&g_sSafetyCommon, g_dio_safety_test_items[0], g_dio_safety_test_items[1],
|
||||
LOGICAL_ONE);
|
||||
SafetyDigitalInputOutput_ShortAdjTest(&g_sSafetyCommon, g_dio_safety_test_items[0], g_dio_safety_test_items[1],
|
||||
LOGICAL_ZERO);
|
||||
#endif /* DIO_TEST_ENABLED */
|
||||
|
||||
#if WATCHDOG_ENABLED
|
||||
Watchdog_refresh; /* refreshing the watchdog */
|
||||
#endif
|
||||
|
||||
#if CLOCK_TEST_ENABLED
|
||||
/* Initialize Clock test */
|
||||
SafetyClockTestInit(&g_sSafetyCommon, &g_sSafetyClockTest);
|
||||
#endif
|
||||
|
||||
/* Initialize SysTick */
|
||||
SystickInit(SYSTICK_RELOAD_VALUE);
|
||||
|
||||
/* Enable interrupts */
|
||||
__asm("CPSIE i");
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* Interruptable CPU registers test */
|
||||
SafetyCpuBackgroundTest(&g_sSafetyCommon);
|
||||
|
||||
/* safety test of CPU CONTROL register, it cannot be placed in interrupt, thus interrupts must be disabled for a
|
||||
* while */
|
||||
/* - see IEC60730 library documentation for CPU errors handling ! */
|
||||
__asm("CPSID i");
|
||||
#if (defined(_LPC55S69_CM33_CORE0_H_) || defined(_LPC55S06_H_) || defined(_MIMXRT1189_CM33_H_)) /* If device supports TrustZone */
|
||||
g_sSafetyCommon.CPU_control_s_test_result = FS_CM33_CPU_Control_S();
|
||||
#else
|
||||
g_sSafetyCommon.CPU_control_s_test_result = FS_CM33_CPU_Control();
|
||||
#endif /* If device supports TrustZone */
|
||||
__asm("CPSIE i");
|
||||
if (g_sSafetyCommon.CPU_control_s_test_result == FS_FAIL_CPU_CONTROL)
|
||||
{
|
||||
g_sSafetyCommon.safetyErrors |= CPU_CONTROL_ERROR;
|
||||
SafetyErrorHandling(&g_sSafetyCommon);
|
||||
}
|
||||
|
||||
/* safety test of CPU SP_PROCESS register, it cannot be placed in interrupt, thus interrupts must be disabled
|
||||
* for a while */
|
||||
/* - see IEC60730 library documentation for CPU errors handling ! */
|
||||
__asm("CPSID i");
|
||||
FS_CM33_CPU_SPprocess_S();
|
||||
__asm("CPSIE i");
|
||||
|
||||
#if FLASH_TEST_ENABLED
|
||||
/* Runtime Flash test */
|
||||
SafetyFlashRuntimeTest(&g_sSafetyCommon, &g_sFlashCrc, &g_sFlashConfig);
|
||||
#endif
|
||||
|
||||
#if CLOCK_TEST_ENABLED
|
||||
/* Runtime Clock test */
|
||||
SafetyClockTestCheck(&g_sSafetyCommon, &g_sSafetyClockTest);
|
||||
#endif
|
||||
|
||||
/* Stack overflow and underflow test */
|
||||
SafetyStackTest(&g_sSafetyCommon);
|
||||
|
||||
#if ADC_TEST_ENABLED
|
||||
/* Runtime ADC test */
|
||||
SafetyAnalogTest(&g_sSafetyCommon);
|
||||
#endif
|
||||
|
||||
#if DIO_TEST_ENABLED
|
||||
/* Digital I/O test */
|
||||
safety_dio_runtime();
|
||||
#endif
|
||||
|
||||
#if FMSTR_SERIAL_ENABLE
|
||||
|
||||
FMSTR_Poll(); /* Freemaster cummunication */
|
||||
#endif /* FMSTR_SERIAL_ENABLE */
|
||||
|
||||
development_test_terminate(); /* For example validation during development */
|
||||
}
|
||||
}
|
||||
|
||||
void safety_dio_runtime(void)
|
||||
{
|
||||
/* Static variable for indexing in items array */
|
||||
static uint8_t dio_cnt_number = 0;
|
||||
|
||||
if (g_dio_safety_test_items[dio_cnt_number] != NULL)
|
||||
{
|
||||
#ifndef _MIMXRT1189_CM33_H_
|
||||
SafetyDigitalOutputTest(&g_sSafetyCommon, g_dio_safety_test_items[dio_cnt_number]);
|
||||
#endif
|
||||
SafetyDigitalInputOutput_ShortSupplyTest(&g_sSafetyCommon, g_dio_safety_test_items[dio_cnt_number],
|
||||
DIO_SHORT_TO_GND_TEST);
|
||||
SafetyDigitalInputOutput_ShortSupplyTest(&g_sSafetyCommon, g_dio_safety_test_items[dio_cnt_number],
|
||||
DIO_SHORT_TO_VDD_TEST);
|
||||
|
||||
/* In next call, test next DIO channel */
|
||||
dio_cnt_number++;
|
||||
}
|
||||
else
|
||||
{
|
||||
dio_cnt_number = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Systick interrupt function
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void SYSTICK_Isr(void)
|
||||
{
|
||||
counter++;
|
||||
|
||||
#if CLOCK_TEST_ENABLED
|
||||
/* Clock test function */
|
||||
SafetyClockTestIsr(&g_sSafetyClockTest);
|
||||
#endif
|
||||
|
||||
/* Safety tests which cannot be interrupted */
|
||||
SafetyIsrFunction(&g_sSafetyCommon, &g_sSafetyRamTest, &g_sSafetyRamStackTest);
|
||||
|
||||
/* Refreshing the watchdog. For short period of interrupts, choose higher refresh ratio parameter */
|
||||
SafetyWatchdogRuntimeRefresh(&g_sSafetyWdTest);
|
||||
}
|
||||
|
|
@ -1,184 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*
|
||||
* Processors: LPC55S69JBD100_cm33_core0
|
||||
* LPC55S69JBD64_cm33_core0
|
||||
* LPC55S69JEV98_cm33_core0
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/****************** LIBRARY *******************************************/
|
||||
/******************************************************************************/
|
||||
GROUP (
|
||||
"libcr_semihost_nf.a"
|
||||
"libcr_c.a"
|
||||
"libcr_eabihelpers.a"
|
||||
"libgcc.a"
|
||||
)
|
||||
|
||||
/******************************************************************************/
|
||||
/****************** USER CONFIGURATION PART ***************************/
|
||||
/******************************************************************************/
|
||||
/* FLASH memory boundaries. */
|
||||
__ROM_start__ = 0x00000000;
|
||||
__ROM_end__ = 0x00071FFF;
|
||||
|
||||
/* RAM memory boundaries. */
|
||||
__RAM_start__ = 0x20000000;
|
||||
__RAM_end__ = 0x200317FF;
|
||||
|
||||
/* Sizes of objects in RAM. */
|
||||
__size_cstack__ = 0x0400; /* Stack size. */
|
||||
stack_test_block_size = 0x10; /* Safety stack test pattern. */
|
||||
ram_test_backup_size = 0x20; /* Safety RAM test backup size. */
|
||||
wd_test_backup_size = 0x20; /* Safety WDOG test data size. */
|
||||
|
||||
/* Sizes of objects in FLASH. */
|
||||
__vector_table_size__ = 0x130;
|
||||
__PC_test_size = 0x20;
|
||||
__size_flash_crc__ = 0x10;
|
||||
__flash_cfg_size = 0x10;
|
||||
|
||||
__VECTOR_TABLE = __ROM_start__;
|
||||
__size_heap__ = 0x40; /* 2x heap and heap2stackfill */
|
||||
|
||||
/******************************************************************************/
|
||||
/****************** SYMBOLS *******************************************/
|
||||
/******************************************************************************/
|
||||
/* Assemble RAM addresses. */
|
||||
m_ram_test_backup = (__RAM_end__ - ram_test_backup_size + 0x1);
|
||||
m_wd_test_backup = (m_ram_test_backup - wd_test_backup_size);
|
||||
m_pc_test_flag = (m_wd_test_backup - 0x4);
|
||||
m_safety_error_code = (m_pc_test_flag - 0x4);
|
||||
m_stack_test_p_4 = (m_safety_error_code - 0x4);
|
||||
m_stack_test_p_3 = (m_stack_test_p_4 - stack_test_block_size +0x4);
|
||||
__BOOT_STACK_ADDRESS = (m_stack_test_p_3 - 0x4);
|
||||
m_stack_test_p_2 = (__BOOT_STACK_ADDRESS - __size_cstack__);
|
||||
m_stack_test_p_1 = (m_stack_test_p_2 - stack_test_block_size + 0x4);
|
||||
|
||||
m_safety_ram_start = __RAM_start__;
|
||||
|
||||
/* Assemble FLASH addresses. */
|
||||
m_intvec_table_start = (__ROM_start__);
|
||||
m_intvec_table_end = (m_intvec_table_start + __vector_table_size__ - 0x1);
|
||||
__PC_test_start__ = (m_intvec_table_end + 0x1);
|
||||
__PC_test_end__ = (__PC_test_start__ + __PC_test_size - 0x1);
|
||||
m_flash_start = (__PC_test_end__ + 0x1);
|
||||
|
||||
m_fs_flash_crc_end = (__ROM_end__);
|
||||
m_fs_flash_crc_start = (m_fs_flash_crc_end - __size_flash_crc__ + 0x1);
|
||||
m_flash_end = (m_fs_flash_crc_start - 0x1);
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MEM_FLASH (rx) : ORIGIN = __ROM_start__, LENGTH = (__ROM_end__ - __ROM_start__ + 1)
|
||||
MEM_RAM (rwx) : ORIGIN = __RAM_start__, LENGTH = (__RAM_end__ - __RAM_start__ + 1)
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/****************** PLACING *******************************************/
|
||||
/******************************************************************************/
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Safety-related code and read-only data section. */
|
||||
.SEC_FS_ROM : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
|
||||
/* The interrupt vector table. */
|
||||
. = m_intvec_table_start;
|
||||
KEEP(*(.intvec*))
|
||||
|
||||
/* PC test object. */
|
||||
. = __PC_test_start__;
|
||||
KEEP(*iec60730b_cm33_pc_object.o(.text*))
|
||||
|
||||
/* Safety-related FLASH code and RO data. */
|
||||
. = m_flash_start;
|
||||
*(.rodata*)
|
||||
. = . + 1;
|
||||
. = ALIGN(4);
|
||||
} >MEM_FLASH
|
||||
|
||||
/* The safety-related RAM. */
|
||||
.SEC_FS_RAM m_safety_ram_start : AT (ADDR(.SEC_FS_ROM) + SIZEOF(.SEC_FS_ROM))
|
||||
{
|
||||
m_sec_fs_ram_load_start = LOADADDR(.SEC_FS_RAM);
|
||||
m_sec_fs_ram_start = .;
|
||||
*(.safety_ram*)
|
||||
*main.o(.data*)
|
||||
*safety_test_items.o(.data*)
|
||||
. = . + 1;
|
||||
. = ALIGN(4);
|
||||
m_sec_fs_ram_load_end = LOADADDR (.SEC_FS_RAM) + SIZEOF(.SEC_FS_RAM);
|
||||
m_sec_fs_ram_end = .;
|
||||
|
||||
/* The end of safety-related FLASH memory. */
|
||||
m_safety_flash_end = LOADADDR (.SEC_FS_RAM) + SIZEOF(.SEC_FS_RAM);
|
||||
} >MEM_RAM
|
||||
|
||||
|
||||
/* The non-safety RW data. */
|
||||
.SEC_RWRAM m_sec_fs_ram_end : AT (m_safety_flash_end)
|
||||
{
|
||||
m_sec_rwram_load_start = LOADADDR(.SEC_RWRAM);
|
||||
m_sec_rwram_start = .;
|
||||
*(.data*)
|
||||
. = . + 1;
|
||||
. = ALIGN(4);
|
||||
m_sec_rwram_load_end = LOADADDR(.SEC_RWRAM) + SIZEOF(.SEC_RWRAM);
|
||||
m_sec_rwram_end = .;
|
||||
} >MEM_RAM
|
||||
|
||||
/* The non-safety code and RO data. */
|
||||
.SEC_ROM m_sec_rwram_load_end : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.text*)
|
||||
KEEP(*(.rodata .rodata.* .constdata .constdata.*))
|
||||
. = . + 1;
|
||||
. = ALIGN(4);
|
||||
} >MEM_FLASH
|
||||
|
||||
/* The safety FLASH CRC. */
|
||||
.SEC_CRC m_fs_flash_crc_start : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
KEEP(*(.flshcrc*))
|
||||
} >MEM_FLASH
|
||||
|
||||
/* Stack memory. */
|
||||
stack (__BOOT_STACK_ADDRESS - __size_cstack__) : ALIGN(4)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
} > MEM_RAM
|
||||
|
||||
/* The zero-initialized RW data. */
|
||||
.SEC_BSS m_sec_rwram_end : ALIGN(4)
|
||||
{
|
||||
m_sec_bss_start = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = . + 1;
|
||||
. = ALIGN(4);
|
||||
m_sec_bss_end = .;
|
||||
} >MEM_RAM
|
||||
|
||||
/* Reserve and place Heap within memory map */
|
||||
_HeapSize = __size_heap__;
|
||||
.heap : ALIGN(4)
|
||||
{
|
||||
_pvHeapStart = .;
|
||||
. += _HeapSize;
|
||||
. = ALIGN(4);
|
||||
_pvHeapLimit = .;
|
||||
} > MEM_RAM
|
||||
}
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v8.0
|
||||
processor: LPC55S69
|
||||
package_id: LPC55S69JBD100
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 8.0.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iocon.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
|
||||
mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
|
||||
|
||||
const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -1,337 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "project_setup_lpcxpresso55s69.h"
|
||||
#include "board.h"
|
||||
|
||||
#include "fsl_lpadc.h"
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_usart.h"
|
||||
#include "fsl_iocon.h"
|
||||
#include "freemaster.h"
|
||||
#include "freemaster_serial.h"
|
||||
#include "freemaster_serial_usart.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Watchdog configuration function
|
||||
*
|
||||
* Enables the watchdog. Also in Wait and Stop mode. Updates are allowed
|
||||
*
|
||||
* @param wd_setup_value //watchdog setup value for timeout
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void WatchdogEnable(uint32_t wd_setup_value)
|
||||
{
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK; /* Enable FRO_1MHz */
|
||||
SYSCON->WDTCLKDIV = 0; /* WD clock 1MHz */
|
||||
SYSCON->AHBCLKCTRL.AHBCLKCTRL0 |= SYSCON_AHBCLKCTRL0_WWDT_MASK; /* Enable clock to WDT */
|
||||
|
||||
uint32_t bitMask = 0x400000;
|
||||
|
||||
/* reset register is in SYSCON */
|
||||
/* set bit */
|
||||
SYSCON->PRESETCTRLSET[0] = bitMask;
|
||||
/* wait until it reads 0b1 */
|
||||
while (0u == (SYSCON->PRESETCTRLX[0] & bitMask))
|
||||
{
|
||||
}
|
||||
|
||||
/* clear bit */
|
||||
SYSCON->PRESETCTRLCLR[0] = bitMask;
|
||||
/* wait until it reads 0b0 */
|
||||
while (bitMask == (SYSCON->PRESETCTRLX[0] & bitMask))
|
||||
{
|
||||
}
|
||||
|
||||
USED_WDOG->TC = WWDT_TC_COUNT(wd_setup_value); /* refresh value */
|
||||
USED_WDOG->MOD = WWDT_MOD_WDRESET(1) | WWDT_MOD_WDEN(1);
|
||||
USED_WDOG->WINDOW = 0xFFFFFF; /* Disable Window mode */
|
||||
|
||||
__asm("CPSID i");
|
||||
USED_WDOG->FEED = 0xAA; /* Start WDOG */
|
||||
USED_WDOG->FEED = 0x55;
|
||||
__asm("CPSIE i");
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Watchdog disabling function
|
||||
*
|
||||
* @param *WDOGx - pointer to the base address of the periphery
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void WatchdogDisable(void)
|
||||
{
|
||||
/* Wdog is disabled on LPCdisabled after reset by default */
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initialization of Systick timer
|
||||
*
|
||||
* This function configures the Systick as a source of interrupt
|
||||
*
|
||||
* @param reload_value - defines the period of counter refresh
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void SystickInit(uint32_t reload_value)
|
||||
{
|
||||
// SYSCON->SYSTICKCLKSEL.SYSTICKCLKSEL0 = 0; /*Main clock select */
|
||||
// SYSCON->SYSTICKCLKDIV0 &= ~(SYSCON_SYSTICKCLKDIV0_DIV_MASK); /*0 = div 1 */
|
||||
|
||||
SysTick->VAL = 0;
|
||||
SysTick->LOAD = reload_value;
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/* Second timer for CLOCK TEST */
|
||||
void second_timer_inicialization(void)
|
||||
{
|
||||
SYSCON->AHBCLKCTRL.AHBCLKCTRL0 |= SYSCON_AHBCLKCTRL0_RTC_MASK;
|
||||
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
|
||||
|
||||
SYSCON->CTIMERCLKSEL.CTIMERCLKSEL0 = 0x4; /* OSCILATOR 1MHZ */
|
||||
SYSCON->AHBCLKCTRL.AHBCLKCTRL1 |= SYSCON_AHBCLKCTRL1_TIMER0_MASK; /*Enable clock to Ctimer0*/
|
||||
|
||||
SYSCON->PRESETCTRL.PRESETCTRL0 &= ~(SYSCON_PRESETCTRL1_TIMER0_RST_MASK); // Reset the CTIMER0
|
||||
SYSCON->PRESETCTRL.PRESETCTRL0 |= (SYSCON_PRESETCTRL1_TIMER0_RST_MASK);
|
||||
|
||||
CTIMER0->CTCR &= ~(CTIMER_CTCR_CTMODE_MASK);
|
||||
CTIMER0->TCR |= CTIMER_TCR_CEN_MASK; /*Enable counter*/
|
||||
CTIMER0->TCR |= CTIMER_TCR_CRST_MASK; /*Counter reset*/
|
||||
CTIMER0->TCR &= ~(CTIMER_TCR_CRST_MASK); /*Counter stop reset*/
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Setup of clock
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*
|
||||
*/
|
||||
void ClockInit(void)
|
||||
{
|
||||
BOARD_BootClockPLL150M();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initialization of CTIMER
|
||||
*
|
||||
* This function initializes the CTIMER. CTIMER is used for After reset WDog test.
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void CTIMER_initialisation(void)
|
||||
{
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO1M); /*!< Ensure FRO is on */
|
||||
|
||||
SYSCON->CTIMERCLKSEL.CTIMERCLKSEL0 = 0x3; /* 96MHZ HF FRO CLOCK */
|
||||
SYSCON->AHBCLKCTRL.AHBCLKCTRL1 |= SYSCON_AHBCLKCTRL1_TIMER0_MASK; /* Enable clock to Ctimer0 */
|
||||
|
||||
SYSCON->PRESETCTRL.PRESETCTRL0 &= ~(SYSCON_PRESETCTRL1_TIMER0_RST_MASK);
|
||||
SYSCON->PRESETCTRL.PRESETCTRL0 |= (SYSCON_PRESETCTRL1_TIMER0_RST_MASK);
|
||||
|
||||
CTIMER0->CTCR &= ~(CTIMER_CTCR_CTMODE_MASK);
|
||||
|
||||
CTIMER0->TCR |= CTIMER_TCR_CEN_MASK; /* Enable counter */
|
||||
CTIMER0->TCR |= CTIMER_TCR_CRST_MASK; /* Counter reset */
|
||||
CTIMER0->TCR &= ~(CTIMER_TCR_CRST_MASK); /* Counter stop reset */
|
||||
}
|
||||
/*!
|
||||
* @brief Sets port direction and mux
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void PortSetup(uint8_t *pByte,
|
||||
uint32_t *pDir,
|
||||
uint32_t *pIocon,
|
||||
uint32_t pinDir,
|
||||
uint32_t pinNum,
|
||||
uint32_t pull,
|
||||
uint32_t clock_enable_shift)
|
||||
{
|
||||
/* Enable clock to GPIO module */
|
||||
SYSCON->AHBCLKCTRL.AHBCLKCTRL0 |= (1 << clock_enable_shift);
|
||||
|
||||
*pIocon |= IOCON_PIO_DIGIMODE(1); /*Enable Digi mode*/
|
||||
*pIocon &= ~(IOCON_PIO_MODE_MASK); /*Clear PULL setting*/
|
||||
*pIocon |= IOCON_PIO_MODE(pull); /*Set pullup*/
|
||||
|
||||
if (pinDir == PIN_DIRECTION_OUT)
|
||||
{
|
||||
*pDir |= (1 << pinNum); /* PINx = 1 = output */
|
||||
}
|
||||
else if (pinDir == PIN_DIRECTION_IN)
|
||||
{
|
||||
*pDir &= ~(1 << pinNum); /* PINx = 0 = input */
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initialization of ADC0
|
||||
*
|
||||
* 8 MHz System Oscillator Bus Clock is the source clock.
|
||||
* single-ended 16-bit conversion
|
||||
*
|
||||
* @param void
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void AdcInit(void)
|
||||
{
|
||||
/* Analog pin setup
|
||||
GPIO_0_23, P19_4 on board */
|
||||
IOCON->PIO[0][23] = (0x400 | 0x10);
|
||||
|
||||
lpadc_config_t configStruct;
|
||||
lpadc_conv_command_config_t commandConfigStruct;
|
||||
lpadc_conv_trigger_config_t triggerConfigStruct;
|
||||
|
||||
/* Enable clock to ADC */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true);
|
||||
CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK);
|
||||
|
||||
/* Disable LDOGPADC power down */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
|
||||
|
||||
/* Configure ADC module */
|
||||
LPADC_GetDefaultConfig(&configStruct);
|
||||
configStruct.enableAnalogPreliminary = true;
|
||||
configStruct.referenceVoltageSource = kLPADC_ReferenceVoltageAlt2;
|
||||
configStruct.conversionAverageMode = kLPADC_ConversionAverage128;
|
||||
configStruct.powerLevelMode = kLPADC_PowerLevelAlt4;
|
||||
LPADC_Init(ADC0, &configStruct);
|
||||
|
||||
/* Request offset calibration */
|
||||
// LPADC_DoOffsetCalibration(ADC0); // uncomment for auto calibration (must feed watchdog during calibration)
|
||||
ADC0->OFSTRIM = 0x10003; // manual calibration
|
||||
|
||||
/* Request gain calibration. */
|
||||
// LPADC_DoAutoCalibration(ADC0); // uncomment for auto calibration (must feed watchdog during calibration)
|
||||
ADC0->GCR[0] = 0x00011AE; // manual calibration
|
||||
ADC0->GCR[1] = 0x0001138; // manual calibration
|
||||
|
||||
/************************************/
|
||||
/* Set conversion CMD configuration */
|
||||
/************************************/
|
||||
LPADC_GetDefaultConvCommandConfig(&commandConfigStruct);
|
||||
commandConfigStruct.conversionResolutionMode = kLPADC_ConversionResolutionHigh;
|
||||
|
||||
/* 3V3 */
|
||||
commandConfigStruct.channelNumber = 12U; /* 3V3 channel */
|
||||
LPADC_SetConvCommandConfig(ADC0, 1U, &commandConfigStruct); /* Command ID = 1 (idx 0) */
|
||||
|
||||
/* 1V */
|
||||
commandConfigStruct.channelNumber = 13U; /* 1V channel */
|
||||
LPADC_SetConvCommandConfig(ADC0, 2U, &commandConfigStruct); /* Command ID = 2 (idx 1) */
|
||||
|
||||
/* EXTERNAL PIN GPIO_0_23 (P19,4 on board) */
|
||||
commandConfigStruct.channelNumber = 0; /* external pin channel */
|
||||
LPADC_SetConvCommandConfig(ADC0, 3U, &commandConfigStruct); /* Command ID = 3 (idx 2) */
|
||||
|
||||
/*****************************/
|
||||
/* Set trigger configuration */
|
||||
/*****************************/
|
||||
LPADC_GetDefaultConvTriggerConfig(&triggerConfigStruct);
|
||||
triggerConfigStruct.enableHardwareTrigger = false;
|
||||
|
||||
/* 3V3 */
|
||||
triggerConfigStruct.targetCommandId = 1U;
|
||||
LPADC_SetConvTriggerConfig(ADC0, 0U, &triggerConfigStruct); /* Trigger ID = 0 */
|
||||
|
||||
/* 1V */
|
||||
triggerConfigStruct.targetCommandId = 2U;
|
||||
LPADC_SetConvTriggerConfig(ADC0, 1U, &triggerConfigStruct); /* Trigger ID = 1 */
|
||||
|
||||
/* EXTERNAL PIN */
|
||||
triggerConfigStruct.targetCommandId = 3U;
|
||||
LPADC_SetConvTriggerConfig(ADC0, 2U, &triggerConfigStruct); /* Trigger ID = 2 */
|
||||
}
|
||||
|
||||
/************************************************/
|
||||
void SerialInit(void)
|
||||
{
|
||||
/* Init board hardware. */
|
||||
/* attach main clock divide to FLEXCOMM0 (debug console) 12MHz */
|
||||
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
|
||||
|
||||
/* FreeMASTER communication layer initialization */
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
0x01u |
|
||||
/* No addition pin function */
|
||||
0x00u |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
0x00u |
|
||||
/* Input function is not inverted */
|
||||
0x00u |
|
||||
/* Enables digital function */
|
||||
0x0100u |
|
||||
/* Open drain is disabled */
|
||||
0x00u);
|
||||
/* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
|
||||
|
||||
const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
|
||||
0x01u |
|
||||
/* No addition pin function */
|
||||
0x00u |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
0x00u |
|
||||
/* Input function is not inverted */
|
||||
0x00u |
|
||||
/* Enables digital function */
|
||||
0x0100u |
|
||||
/* Open drain is disabled */
|
||||
0x00u);
|
||||
/* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
|
||||
|
||||
usart_config_t config;
|
||||
/*
|
||||
* usartConfig->baudRate_Bps = UART_BAUD_RATE;
|
||||
* usartConfig->parityMode = kUSART_ParityDisabled;
|
||||
* usartConfig->stopBitCount = kUSART_OneStopBit;
|
||||
* usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
|
||||
* usartConfig->loopback = false;
|
||||
* usartConfig->enableTx = false;
|
||||
* usartConfig->enableRx = false;
|
||||
*/
|
||||
USART_GetDefaultConfig(&config);
|
||||
/* Override the Default configuration to satisfy FreeMASTER needs */
|
||||
config.baudRate_Bps = UART_BAUD_RATE;
|
||||
config.enableTx = true;
|
||||
config.enableRx = true;
|
||||
|
||||
USART_Init((USART_Type *)BOARD_DEBUG_UART_BASEADDR, &config, BOARD_DEBUG_UART_CLK_FREQ);
|
||||
|
||||
#if FMSTR_SERIAL_ENABLE
|
||||
/* Register communication module used by FreeMASTER driver. */
|
||||
FMSTR_SerialSetBaseAddress((USART_Type *)BOARD_DEBUG_UART_BASEADDR);
|
||||
|
||||
#if FMSTR_SHORT_INTR || FMSTR_LONG_INTR
|
||||
/* Enable UART interrupts. */
|
||||
EnableIRQ(BOARD_UART_IRQ);
|
||||
EnableGlobalIRQ(0);
|
||||
#endif
|
||||
#endif //FMSTR_SERIAL_ENABLE
|
||||
}
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _PROJECT_SETUP_H_
|
||||
#define _PROJECT_SETUP_H_
|
||||
|
||||
#include "safety_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define BACKUP 0
|
||||
#define RESTORE 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Project setup functions
|
||||
* @{
|
||||
*/
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
void WatchdogEnable(uint32_t wd_setup_value);
|
||||
void WatchdogDisable(void);
|
||||
void CTIMER_initialisation(void);
|
||||
void second_timer_inicialization(void); /* Second timer for CLOKC TEST */
|
||||
void SystickInit(uint32_t reload_value);
|
||||
void ClockInit(void);
|
||||
void PortSetup(uint8_t *pByte,
|
||||
uint32_t *pDir,
|
||||
uint32_t *pIocon,
|
||||
uint32_t pinDir,
|
||||
uint32_t pinNum,
|
||||
uint32_t pull,
|
||||
uint32_t clock_enable_shift);
|
||||
void AdcInit(void);
|
||||
void Tsi0SetupSelfCap(void);
|
||||
void Tsi0SetupMutualCap(void);
|
||||
void SerialInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PROJECT_SETUP_H_ */
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
Overview
|
||||
========
|
||||
This application demonstrates use of certified NXP Safety Library 4.1 which meets the IEC60730 class B standard.
|
||||
|
||||
More information
|
||||
================
|
||||
- All important documents (library/application user's guide, release note and certificate) are in SDK install folder\docs\safety\.
|
||||
- For more information see webpage: www.nxp.com/iec60730.
|
||||
|
||||
Running the demo
|
||||
================
|
||||
- Follow Safety example user's guide \docs\safety\IEC60730BLPC55SXXUG.pdf.
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,195 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _SAFETY_CM33_LPC_H_
|
||||
#define _SAFETY_CM33_LPC_H_
|
||||
|
||||
#include "safety_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define CPU_TEST_ERROR 0x1 /* CPU test fault flag */
|
||||
#define FLASH_TEST_ERROR 0x2 /* Flash test fault flag */
|
||||
#define RAM_TEST_ERROR 0x4 /* RAM test fault flag */
|
||||
#define STACK_TEST_ERROR 0x8 /* Stack test fault flag */
|
||||
#define CLOCK_TEST_ERROR 0x10 /* Clock test fault flag */
|
||||
#define PC_TEST_ERROR 0x20 /* Program counter test fault flag */
|
||||
#define CPU_PRIMASK_ERROR 0x40 /* PRIMASK test fault flag */
|
||||
#define CPU_REGISTERS_ERROR 0x80 /* CPU registers test fault flag */
|
||||
#define CPU_NONSTACKED_ERROR 0x100 /* non-stacked CPU test fault flag */
|
||||
#define CPU_CONTROL_ERROR 0x200 /* CONTROL register test fault flag */
|
||||
#define CPU_SPECIAL_ERROR 0x400 /* BASEPRI and FAULTMASK test fault flag */
|
||||
#define CPU_FLOAT_ERROR 0x800 /* FLOAT test fault flag */
|
||||
#define DIO_TEST_ERROR 0x1000 /* DIO test fault flag */
|
||||
#define AIO_TEST_ERROR 0x2000 /* AIO test fault flag */
|
||||
#define TSI_TEST_ERROR 0x4000 /* TSI test fault flag */
|
||||
#define WDOG_TEST_ERROR 0x8000 /* WDOG test fault flag */
|
||||
|
||||
#define FS_FLASH_PASS 0x0 /* Flash test pass return */
|
||||
#define FS_FLASH_FAIL 0x00000301 /* Flash test fail return */
|
||||
#define FS_FLASH_PROGRESS 0x00000302
|
||||
|
||||
#define SAFETY_CFG_PC_ADDR0 0x1FFFFFF8 /* #1 test address for Program counter test */
|
||||
#define SAFETY_CFG_PC_ADDR1 0x20000006 /* #2 test address for Program counter test */
|
||||
|
||||
/*! @brief Safety tests */
|
||||
typedef struct _safety_common
|
||||
{
|
||||
uint32_t fastIsrSafetySwitch;
|
||||
uint32_t safetyErrors;
|
||||
uint32_t CLOCK_test_result;
|
||||
uint32_t FLASH_test_result;
|
||||
uint32_t RAM_test_result;
|
||||
uint32_t PC_test_result;
|
||||
uint32_t CPU_primask_s_test_result;
|
||||
uint32_t CPU_primask_ns_test_result;
|
||||
uint32_t CPU_special_s_test_result;
|
||||
uint32_t CPU_special_ns_test_result;
|
||||
uint32_t CPU_reg_test_result;
|
||||
uint32_t CPU_non_stacked_test_result;
|
||||
uint32_t CPU_control_s_test_result;
|
||||
uint32_t CPU_control_ns_test_result;
|
||||
uint32_t CPU_fpu_test_result;
|
||||
uint32_t STACK_test_result;
|
||||
uint32_t DIO_input_test_result;
|
||||
uint32_t DIO_output_test_result;
|
||||
uint32_t DIO_short_test_result;
|
||||
uint32_t AIO_test_result;
|
||||
uint32_t TSI_test_result;
|
||||
uint32_t WDOG_test_result;
|
||||
uint32_t cpuClkFreq;
|
||||
uint32_t mcgirclkFreq;
|
||||
uint32_t lpoFreq;
|
||||
} safety_common_t;
|
||||
|
||||
/*! @brief Safety Watchdog test */
|
||||
typedef struct _wd_test
|
||||
{
|
||||
uint64_t wdTestTemp1;
|
||||
uint32_t wdTestExpected;
|
||||
uint32_t wdTestTolerance;
|
||||
uint32_t wdTestLptmrCnt;
|
||||
uint32_t wdTestLimitHigh;
|
||||
uint32_t wdTestLimitLow;
|
||||
uint32_t watchdogResets;
|
||||
uint32_t watchdogTimeoutCheck;
|
||||
uint16_t watchdogRefreshRatio;
|
||||
} wd_test_t;
|
||||
|
||||
/*! @brief Safety Clock test */
|
||||
typedef struct _clock_test
|
||||
{
|
||||
uint32_t clockTestContext;
|
||||
uint32_t clockTestTolerance;
|
||||
uint32_t clockTestExpected;
|
||||
uint32_t clockTestLimitHigh;
|
||||
uint32_t clockTestLimitLow;
|
||||
uint32_t systickReloadValue;
|
||||
uint16_t clockTestStart;
|
||||
} fs_clock_test_t;
|
||||
|
||||
/*! @brief Safety RAM test */
|
||||
typedef struct _ram_test
|
||||
{
|
||||
uint32_t ramTestStartAddress;
|
||||
uint32_t ramTestEndAddress;
|
||||
uint32_t blockSize;
|
||||
uint32_t actualAddress;
|
||||
uint32_t defaultBlockSize;
|
||||
uint32_t backupAddress;
|
||||
} fs_ram_test_t;
|
||||
|
||||
/*! @brief Safety Flash test runtime */
|
||||
typedef struct _flash_runtime_test_parameters
|
||||
{
|
||||
uint32_t blockSize; /* size of tested block */
|
||||
uint32_t actualAddress; /* actual start address for crc module */
|
||||
uint32_t partCrc; /* seed in begin, particular crc result in process, crc result in final*/
|
||||
uint32_t finalCrc; /* CRC value after all blocsk is calculated */
|
||||
} fs_flash_runtime_test_parameters_t;
|
||||
|
||||
/*! @brief Safety Flash test parameters */
|
||||
typedef struct _flash_configuration_parameters
|
||||
{
|
||||
uint32_t startConditionSeed;
|
||||
uint32_t startAddress;
|
||||
uint32_t endAddress;
|
||||
uint32_t size;
|
||||
uint32_t blockSize;
|
||||
uint32_t checksum;
|
||||
} fs_flash_configuration_parameters_t;
|
||||
|
||||
/* CRC structure containing information for the offline CRC calculation. */
|
||||
typedef struct _fs_crc
|
||||
{
|
||||
uint16_t ui16Start;
|
||||
uint32_t ui32FlashStart __attribute__((packed));
|
||||
uint32_t ui32FlashEnd __attribute__((packed));
|
||||
uint32_t ui32CRC __attribute__((packed));
|
||||
uint16_t ui16End __attribute__((packed));
|
||||
} fs_crc_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Safety Class B tests handling functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
void SafetyWatchdogTest(safety_common_t *psSafetyCommon, wd_test_t *psSafetyWdTest);
|
||||
void SafetyWatchdogRuntimeRefresh(wd_test_t *psSafetyWdTest);
|
||||
void SafetyClockTestInit(safety_common_t *psSafetyCommon, fs_clock_test_t *psSafetyClockTest);
|
||||
void SafetyClockTestIsr(fs_clock_test_t *psSafetyClockTest);
|
||||
void SafetyClockTestCheck(safety_common_t *psSafetyCommon, fs_clock_test_t *psSafetyClockTest);
|
||||
void SafetyFlashTestInit(fs_flash_runtime_test_parameters_t *psFlashCrc,
|
||||
fs_flash_configuration_parameters_t *psFlashConfig);
|
||||
void SafetyFlashAfterResetTest(safety_common_t *psSafetyCommon, fs_flash_configuration_parameters_t *psFlashConfig);
|
||||
void SafetyFlashRuntimeTest(safety_common_t *psSafetyCommon,
|
||||
fs_flash_runtime_test_parameters_t *psFlashCrc,
|
||||
fs_flash_configuration_parameters_t *psFlashConfig);
|
||||
uint32_t SafetyFlashTestHandling(fs_flash_runtime_test_parameters_t *psFlashCrc,
|
||||
fs_flash_configuration_parameters_t *psFlashConfig);
|
||||
void SafetyRamTestInit(fs_ram_test_t *psSafetyRamTest, uint32_t *pSafetyRamStart, uint32_t *pSafetyRamEnd);
|
||||
void SafetyRamAfterResetTest(safety_common_t *psSafetyCommon, fs_ram_test_t *psSafetyRamTest);
|
||||
void SafetyRamRuntimeTest(safety_common_t *psSafetyCommon, fs_ram_test_t *psSafetyRamTest);
|
||||
void SafetyPcTest(safety_common_t *psSafetyCommon, uint32_t pattern);
|
||||
void SafetyCpuAfterResetTest(safety_common_t *psSafetyCommon);
|
||||
void SafetyCpuIsrTest(safety_common_t *psSafetyCommon);
|
||||
void SafetyCpuBackgroundTest(safety_common_t *psSafetyCommon);
|
||||
void SafetyStackTestInit(void);
|
||||
void SafetyStackTest(safety_common_t *psSafetyCommon);
|
||||
|
||||
void SafetyDIOTestInit(safety_common_t *psSafetyCommon, fs_dio_test_lpc_t *pTestItems[]);
|
||||
void SafetyDigitalOutputTest(safety_common_t *psSafetyCommon, fs_dio_test_lpc_t *pTestedPin);
|
||||
void SafetyDigitalInputOutput_ShortSupplyTest(safety_common_t *psSafetyCommon,
|
||||
fs_dio_test_lpc_t *pTestedPin,
|
||||
uint8_t polarity);
|
||||
void SafetyDigitalInputOutput_ShortAdjTest(safety_common_t *psSafetyCommon,
|
||||
fs_dio_test_lpc_t *pTestedPin,
|
||||
fs_dio_test_lpc_t *pAdjPin,
|
||||
uint32_t PinValue);
|
||||
|
||||
void SafetyAnalogTest(safety_common_t *psSafetyCommon);
|
||||
|
||||
void SafetyIsrFunction(safety_common_t *psSafetyCommon,
|
||||
fs_ram_test_t *psSafetyRamTest,
|
||||
fs_ram_test_t *psSafetyRamStackTest);
|
||||
|
||||
void development_test_terminate(void);
|
||||
void SafetyErrorHandling(safety_common_t *psSafetyCommon);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SAFETY_CM33_LPC_H_ */
|
||||
|
|
@ -1,135 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _SAFETY_CONFIG_H_
|
||||
#define _SAFETY_CONFIG_H_
|
||||
|
||||
#include "LPC55S69_cm33_core0.h"
|
||||
#include "iec60730b.h"
|
||||
#include "iec60730b_core.h"
|
||||
#include "safety_test_items.h"
|
||||
#include "project_setup_lpcxpresso55s69.h"
|
||||
#include "safety_cm33_lpc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
#ifndef NULL
|
||||
#ifdef __cplusplus
|
||||
#define NULL (0)
|
||||
#else
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/* This macro enables infinity while loop in SafetyErrorHandling() function */
|
||||
#define SAFETY_ERROR_ACTION 1
|
||||
|
||||
/* TEST SWITCHES - for debugging it is better to turn the flash test and watchdog OFF */
|
||||
#define ADC_TEST_ENABLED 0
|
||||
#define CLOCK_TEST_ENABLED 1
|
||||
#define DIO_TEST_ENABLED 1
|
||||
#define FLASH_TEST_ENABLED 1
|
||||
#define RAM_TEST_ENABLED 1
|
||||
#define PC_TEST_ENABLED 1
|
||||
#define WATCHDOG_ENABLED 0
|
||||
#define FMSTR_SERIAL_ENABLE 1
|
||||
|
||||
/* CLOCK test */
|
||||
#define USE_WKT 0 /*USE CTIMER = 0 USE WKT = 1 */
|
||||
#define CLOCK_ERROR_HANDLING 1
|
||||
#define REF_TIMER_USED CTIMER0
|
||||
#define REF_TIMER_CLOCK_FREQUENCY 96e06
|
||||
#define SYSTICK_RELOAD_VALUE 150000
|
||||
#define ISR_FREQUENCY 1000 /* Hz */
|
||||
#define CLOCK_TEST_TOLERANCE 20 /* % */
|
||||
|
||||
/********* Watchdog *********/
|
||||
#define WDOG_REF_TIMER_BASE CTIMER0
|
||||
#define RESET_DETECT_REGISTER &(PMC->AOREG1)
|
||||
#define RESET_DETECT_MASK 0x10U
|
||||
#define REG_WIDE FS_WDOG_SRS_WIDE_32b
|
||||
|
||||
#define Watchdog_refresh \
|
||||
WWDT->FEED = 0xAA; \
|
||||
WWDT->FEED = 0x55
|
||||
#define USED_WDOG WWDT
|
||||
|
||||
#define ENDLESS_LOOP_ENABLE 1 /* set 1 or 0 */
|
||||
#define WATCHDOG_RESETS_LIMIT 1000
|
||||
#define WATCHDOG_REFRESH_RATIO 1
|
||||
#define WATCHDOG_TIMEOUT_VALUE 500 /* 2ms refresh period (500 / 250kHz) */
|
||||
#define WD_REF_TIMER_CLOCK_FREQUENCY 96e06
|
||||
#define WATCHDOG_CLOCK 250000
|
||||
#define WD_TEST_TOLERANCE 40 /* % */
|
||||
|
||||
#define WD_RUN_TEST_CONDITION \
|
||||
(PMC_AOREG1_POR_MASK | PMC_AOREG1_PADRESET_MASK | PMC_AOREG1_BODRESET_MASK | PMC_AOREG1_SYSTEMRESET_MASK | \
|
||||
PMC_AOREG1_DPDRESET_WAKEUPIO_MASK | PMC_AOREG1_DPDRESET_RTC_MASK | PMC_AOREG1_DPDRESET_OSTIMER_MASK)
|
||||
#define WD_CHECK_TEST_CONDITION PMC_AOREG1_WDTRESET_MASK
|
||||
/********* Watchdog END *********/
|
||||
|
||||
/* GPIO macros */
|
||||
#define PIN_DIRECTION_IN 0
|
||||
#define PIN_DIRECTION_OUT 1
|
||||
|
||||
#define PIN_PULL_DISABLE 0
|
||||
#define PIN_PULL_DOWN 1
|
||||
#define PIN_PULL_UP 2
|
||||
|
||||
#define LOGICAL_ONE 1
|
||||
#define LOGICAL_ZERO 0
|
||||
|
||||
/* Dio port settings */
|
||||
#define DIO_EXPECTED_VALUE 0
|
||||
|
||||
#define DIO_WAIT_CYCLE 75
|
||||
|
||||
#define DIO_BACKUP_ENABLE 1
|
||||
#define DIO_BACKUP_DISABLE 0
|
||||
#define DIO_BACKUP DIO_BACKUP_ENABLE
|
||||
|
||||
#define DIO_SHORT_TO_GND_TEST 1
|
||||
#define DIO_SHORT_TO_VDD_TEST 0
|
||||
|
||||
/* Program Counter TEST */
|
||||
#define PC_TEST_PATTERN 0x20001000 /* test address for Program counter test (in RAM region) */
|
||||
|
||||
/* UART macros */
|
||||
#define UART_BAUD_RATE 9600
|
||||
|
||||
/* FLASH TEST MACROS */
|
||||
#define HW_FLASH_TEST 1 /* Use HW = 1 SW = 0 flash TEST*/
|
||||
#define FLASH_TEST_BLOCK_SIZE 0x20
|
||||
#define CRC_BASE CRC_ENGINE_BASE
|
||||
#define FLASH_TEST_CONDITION_SEED 0x0000 /* 0xFFFFFFFF CRC32, 0x0000 CRC16 */
|
||||
|
||||
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
|
||||
/*! @note The following flash test settings must be in consistence with
|
||||
"User AFTER BUILD = srec_cat!*/
|
||||
/* The CRC16 of safety-related FLASH memory. */
|
||||
#define FS_CFG_FLASH_TST_CRC (0xFFFFU)
|
||||
#endif
|
||||
|
||||
#define RAM_TEST_BLOCK_SIZE 0x4 /* size of block for runtime testing */
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__) || (defined(__GNUC__) && (__ARMCC_VERSION >= 6010050)) /* IAR + KEIL */
|
||||
#define RAM_TEST_BACKUP_SIZE 0x20 /* must fit with the setup from linker configuration file */
|
||||
#define STACK_TEST_BLOCK_SIZE 0x10 /* must fit with the setup from linker configuration file */
|
||||
#endif
|
||||
|
||||
#define STACK_TEST_PATTERN 0x77777777
|
||||
|
||||
#define TESTED_ADC ADC0 /*which ADC is use for AIO test*/
|
||||
#define ADC_RESOLUTION 16
|
||||
#define ADC_REFERENCE 3.3
|
||||
#define ADC_BANDGAP_LEVEL 1.65 /* depends on power supply configuration */
|
||||
#define ADC_DEVIATION_PERCENT 20
|
||||
|
||||
|
||||
#endif /* _SAFETY_CONFIG_H_ */
|
||||
|
|
@ -1,195 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="cm33_core0_LPC55S69"/>
|
||||
<definition extID="middleware.safety.LPC55S69"/>
|
||||
<definition extID="platform.drivers.clock.LPC55S69"/>
|
||||
<definition extID="platform.drivers.power.LPC55S69"/>
|
||||
<definition extID="platform.drivers.common.LPC55S69"/>
|
||||
<definition extID="platform.devices.LPC55S69_CMSIS.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_usart.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpc_iocon.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpc_gpio.LPC55S69"/>
|
||||
<definition extID="platform.utilities.assert.LPC55S69"/>
|
||||
<definition extID="utility.debug_console.LPC55S69"/>
|
||||
<definition extID="component.usart_adapter.LPC55S69"/>
|
||||
<definition extID="component.serial_manager.LPC55S69"/>
|
||||
<definition extID="component.lists.LPC55S69"/>
|
||||
<definition extID="component.serial_manager_uart.LPC55S69"/>
|
||||
<definition extID="middleware.fmstr.LPC55S69"/>
|
||||
<definition extID="middleware.fmstr.platform_gen32le.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpadc.LPC55S69"/>
|
||||
<definition extID="platform.utilities.misc_utilities.LPC55S69"/>
|
||||
<definition extID="platform.drivers.reset.LPC55S69"/>
|
||||
<definition extID="CMSIS_Include_core_cm.LPC55S69"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
</externalDefinitions>
|
||||
<example id="lpcxpresso55s69_safety_iec60730b_core0" name="safety_iec60730b_core0" device_core="cm33_core0_LPC55S69" dependency="middleware.safety.LPC55S69 platform.drivers.clock.LPC55S69 platform.drivers.power.LPC55S69 platform.drivers.common.LPC55S69 platform.devices.LPC55S69_CMSIS.LPC55S69 platform.drivers.flexcomm_usart.LPC55S69 platform.drivers.flexcomm.LPC55S69 platform.drivers.lpc_iocon.LPC55S69 platform.drivers.lpc_gpio.LPC55S69 platform.utilities.assert.LPC55S69 utility.debug_console.LPC55S69 component.usart_adapter.LPC55S69 component.serial_manager.LPC55S69 component.lists.LPC55S69 component.serial_manager_uart.LPC55S69 middleware.fmstr.LPC55S69 middleware.fmstr.platform_gen32le.LPC55S69 platform.drivers.lpadc.LPC55S69 platform.utilities.misc_utilities.LPC55S69 platform.drivers.reset.LPC55S69 CMSIS_Include_core_cm.LPC55S69" category="demo_apps">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<buildSteps>
|
||||
<postBuildStep>arm-none-eabi-objcopy -v -O ihex "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.hex"; ${ProjDirPath}/crc_hex.bat -${ConfigName}/${BuildArtifactFileBaseName}.hex -${ConfigName}/${BuildArtifactFileBaseName}_crc.hex -tools\\srecord\\srec_cat.exe</postBuildStep>
|
||||
</buildSteps>
|
||||
<option id="com.crt.advproject.link.sgstubenable" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>CPU_LPC55S69JBD100_cm33_core0=1</value>
|
||||
<value>SERIAL_PORT_TYPE_UART=1</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.securestate" type="enum">
|
||||
<value>com.crt.advproject.gcc.securestate.secure</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-mno-unaligned-access -mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.securestate" type="enum">
|
||||
<value>com.crt.advproject.link.securestate.secure</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.fpu" type="enum">
|
||||
<value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.link.option.nostdlibs" type="boolean">
|
||||
<value>true</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<include_paths>
|
||||
<include_path path="mdk/linker" project_relative_path="linker" toolchain="mdk" type="c_include"/>
|
||||
<include_path path="." project_relative_path="source" type="c_include"/>
|
||||
<include_path path="../../../../../devices/LPC55S69" project_relative_path="devices/LPC55S69" type="c_include"/>
|
||||
<include_path path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="." type="c_include"/>
|
||||
<include_path path="." project_relative_path="board" type="c_include"/>
|
||||
<include_path path="../../../../../middleware/safety_iec60730b/boards/common/cm4_cm7/startup/cm33" project_relative_path="." type="asm_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="safety_iec60730b_core0.ewd"/>
|
||||
<files mask="safety_iec60730b_core0.ewp"/>
|
||||
<files mask="safety_iec60730b_core0.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="safety_iec60730b_core0.uvprojx"/>
|
||||
<files mask="safety_iec60730b_core0.uvoptx"/>
|
||||
<files mask="JLinkSettings.JLinkScript"/>
|
||||
<files mask="JLinkSettings.ini"/>
|
||||
<files mask="safety_iec60730b_core0.uvmpw"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="src">
|
||||
<files mask="main.c"/>
|
||||
<files mask="safety_cm33_lpc.c"/>
|
||||
</source>
|
||||
<source path="iar/linker" project_relative_path="linker" type="linker" toolchain="iar">
|
||||
<files mask="lpcxpresso55s69_safety.icf"/>
|
||||
</source>
|
||||
<source path="mdk/linker" project_relative_path="linker" type="linker" toolchain="mdk">
|
||||
<files mask="lpcxpresso55s69_safety.sct"/>
|
||||
</source>
|
||||
<source path="mcux/linker" project_relative_path="linker" type="linker" toolchain="mcuxpresso">
|
||||
<files mask="lpcxpresso55s69_safety.ld"/>
|
||||
</source>
|
||||
<source path="mdk/linker" project_relative_path="linker" type="c_include" toolchain="mdk">
|
||||
<files mask="linker_config.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="c_include">
|
||||
<files mask="safety_test_items.h"/>
|
||||
<files mask="isr.h"/>
|
||||
<files mask="safety_config.h"/>
|
||||
<files mask="project_setup_lpcxpresso55s69.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="src">
|
||||
<files mask="safety_test_items.c"/>
|
||||
<files mask="project_setup_lpcxpresso55s69.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="c_include">
|
||||
<files mask="safety_cm33_lpc.h"/>
|
||||
</source>
|
||||
<source path="../../../../../devices/LPC55S69" project_relative_path="devices/LPC55S69" type="src">
|
||||
<files mask="system_LPC55S69_cm33_core0.c"/>
|
||||
</source>
|
||||
<source path="../../../../../devices/LPC55S69" project_relative_path="devices/LPC55S69" type="c_include">
|
||||
<files mask="system_LPC55S69_cm33_core0.h"/>
|
||||
</source>
|
||||
<source path="GUI" project_relative_path="GUI" type="other">
|
||||
<files mask="safety.pmp"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="c_include">
|
||||
<files mask="freemaster_cfg.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="pin_mux.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="c_include">
|
||||
<files mask="pin_mux.h"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/tools/crc" project_relative_path="." type="script" toolchain="mdk mcuxpresso">
|
||||
<files mask="crc_hex.bat"/>
|
||||
</source>
|
||||
<source path="../../../../../tools/srecord" project_relative_path="tools/srecord" type="other" toolchain="mdk mcuxpresso">
|
||||
<files mask="srec_cat.exe" hidden="true"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="src">
|
||||
<files mask="start.c"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="src" toolchain="iar">
|
||||
<files mask="startup_iar.c"/>
|
||||
<files mask="vectors_iar.c"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="c_include" toolchain="iar">
|
||||
<files mask="vectors_iar.h"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="src" toolchain="mdk">
|
||||
<files mask="startup_mdk.c"/>
|
||||
<files mask="vectors_mdk.c"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="c_include" toolchain="mdk">
|
||||
<files mask="vectors_mdk.h"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="src" toolchain="mcuxpresso">
|
||||
<files mask="startup_mcux.c"/>
|
||||
<files mask="vectors_mcux.c"/>
|
||||
</source>
|
||||
<source path="../../../../../middleware/safety_iec60730b/boards/common/cm33/startup/cm33" project_relative_path="startup" type="c_include" toolchain="mcuxpresso">
|
||||
<files mask="vectors_mcux.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="clock_config.c"/>
|
||||
<files mask="board.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="c_include">
|
||||
<files mask="clock_config.h"/>
|
||||
<files mask="board.h"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="." type="configuration" toolchain="mdk">
|
||||
<files mask="debug.ini"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "safety_config.h"
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__)
|
||||
#pragma location = ".safety_ram"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* *
|
||||
* STRUCTURE FOR DIO Initialization and TEST *
|
||||
* *
|
||||
*******************************************************************************/
|
||||
|
||||
fs_dio_test_lpc_t dio_safety_test_item_0 = /* P1_8 */
|
||||
{.iocon_mode_shift = IOCON_PIO_MODE_SHIFT, /*Device depend*/
|
||||
.pPort_byte = (uint8_t *)&(GPIO->B[1][8]), /*adress of byte register in GPIO*/
|
||||
.pPort_dir = (uint32_t *)&(GPIO->DIR[1]), /* asress of dir1 register*/
|
||||
.pPort_Iocon = (uint32_t *)&(IOCON->PIO[1][8]), /* Adress of concrete IOCON register*/
|
||||
.pinNum = 8, /*Position in DIR registor*/
|
||||
.gpio_clkc_shift = SYSCON_AHBCLKCTRL0_GPIO1_SHIFT};
|
||||
|
||||
fs_dio_test_lpc_t dio_safety_test_item_1 = /* P1_9 */
|
||||
{.iocon_mode_shift = IOCON_PIO_MODE_SHIFT, /* Device depend */
|
||||
.pPort_byte = (uint8_t *)&(GPIO->B[1][9]), /*adress of byte register in GPIO*/
|
||||
.pPort_dir = (uint32_t *)&(GPIO->DIR[1]), /* asress of dir1 register*/
|
||||
.pPort_Iocon = (uint32_t *)&(IOCON->PIO[1][9]), /* Adress of concrete IOCON register*/
|
||||
|
||||
.pinNum = 9, /*Position in DIR registor*/
|
||||
.gpio_clkc_shift = SYSCON_AHBCLKCTRL0_GPIO1_SHIFT};
|
||||
|
||||
/* NULL terminated array of pointers to dio_test_t items for safety DIO test */
|
||||
fs_dio_test_lpc_t *g_dio_safety_test_items[] = {&dio_safety_test_item_0, &dio_safety_test_item_1, NULL};
|
||||
|
||||
/*******************************************************************************
|
||||
* *
|
||||
* STRUCTURE FOR AIO TEST *
|
||||
* *
|
||||
*******************************************************************************/
|
||||
#define ADC_MAX ((1 << (ADC_RESOLUTION)) - 1)
|
||||
#define ADC_BANDGAP_LEVEL_RAW (((ADC_BANDGAP_LEVEL) * (ADC_MAX)) / (ADC_REFERENCE))
|
||||
#define ADC_MIN_LIMIT(val) (uint16_t)(((val) * (100 - ADC_DEVIATION_PERCENT)) / 100)
|
||||
#define ADC_MAX_LIMIT(val) (uint16_t)(((val) * (100 + ADC_DEVIATION_PERCENT)) / 100)
|
||||
|
||||
fs_aio_test_a1_t aio_safety_test_item_VL =
|
||||
{
|
||||
.AdcChannel = 0,
|
||||
.commandBuffer = 1,
|
||||
.SideSelect = 0,/* 0 = A side, 1 = B side*/
|
||||
.softwareTriggerEvent = 0, /* write to the SWTRIG register select between 0 - 3, SWTRIG[SWT0] is associated with TCTRL0 */
|
||||
.Limits.low = (uint32_t)ADC_MIN_LIMIT(0),
|
||||
.Limits.high = (uint32_t)ADC_MAX_LIMIT(60),
|
||||
.state = FS_AIO_INIT
|
||||
};
|
||||
|
||||
fs_aio_test_a1_t aio_safety_test_item_VH =
|
||||
{
|
||||
.AdcChannel = 1,
|
||||
.commandBuffer = 1,
|
||||
.SideSelect = 0,/* 0 = A side, 1 = B side*/
|
||||
.softwareTriggerEvent = 0, /* write to the SWTRIG register select between 0 - 3, SWTRIG[SWT0] is associated with TCTRL0 */
|
||||
.Limits.low = (uint32_t)ADC_MIN_LIMIT(ADC_MAX),
|
||||
.Limits.high = (uint32_t)ADC_MAX_LIMIT(ADC_MAX),
|
||||
.state = FS_AIO_INIT
|
||||
};
|
||||
|
||||
fs_aio_test_a1_t aio_safety_test_item_BG =
|
||||
{
|
||||
.AdcChannel = 2,
|
||||
.commandBuffer = 1,
|
||||
.SideSelect = 0,/* 0 = A side, 1 = B side*/
|
||||
.softwareTriggerEvent = 0, /* write to the SWTRIG register select between 0 - 3, SWTRIG[SWT0] is associated with TCTRL0 */
|
||||
.Limits.low = (uint32_t)ADC_MIN_LIMIT(ADC_BANDGAP_LEVEL_RAW),
|
||||
.Limits.high = (uint32_t)ADC_MAX_LIMIT(ADC_BANDGAP_LEVEL_RAW),
|
||||
.state = FS_AIO_INIT
|
||||
};
|
||||
|
||||
/* NULL terminated array of pointers to fs_aio_test_a2346_t items for safety AIO test */
|
||||
fs_aio_test_a1_t *g_aio_safety_test_items[] = {&aio_safety_test_item_VL,
|
||||
&aio_safety_test_item_VH,
|
||||
&aio_safety_test_item_BG,
|
||||
NULL};
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* Copyright 2021 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _SAFETY_TEST_ITEMS_H_
|
||||
#define _SAFETY_TEST_ITEMS_H_
|
||||
|
||||
/* NULL terminated array of pointers to fs_dio_test_lpc_t items for safety DIO test */
|
||||
extern fs_dio_test_lpc_t *g_dio_safety_test_items[];
|
||||
|
||||
/* NULL terminated array of pointers to aio_test_t items for safety AIO test */
|
||||
extern fs_aio_test_a1_t *g_aio_safety_test_items[];
|
||||
|
||||
#endif
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -111,7 +111,7 @@
|
|||
<files mask="clockout.mex" hidden="true"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="lpcxpresso55s69/driver_examples/clockout/cm33_core0" type="binary">
|
||||
<files mask="syscon_clockout.bin" hidden="true"/>
|
||||
<files mask="clockout.bin" hidden="true"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="board.c"/>
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
bin placeholder
|
||||
|
|
@ -48,7 +48,7 @@
|
|||
</externalDefinitions>
|
||||
<example id="lpcxpresso55s69_lvgl_guider" name="lvgl_guider" device_core="cm33_core0_LPC55S69" dependency="driver.ili9341.LPC55S69 driver.ft6x06.LPC55S69 platform.drivers.flexcomm_spi_dma.LPC55S69 platform.drivers.flexcomm_i2c.LPC55S69 platform.drivers.flexcomm_spi.LPC55S69 platform.drivers.flexcomm_spi_cmsis.LPC55S69 platform.drivers.inputmux.LPC55S69 platform.drivers.flexcomm_i2c_cmsis.LPC55S69 platform.drivers.inputmux_connections.LPC55S69 platform.drivers.flexcomm_i2c_dma.LPC55S69 platform.drivers.lpc_dma.LPC55S69 middleware.freertos-kernel.cm33_nonsecure_port.LPC55S69 middleware.freertos-kernel.heap_4.LPC55S69 platform.drivers.common.LPC55S69 middleware.lvgl.LPC55S69 platform.drivers.clock.LPC55S69 platform.drivers.power.LPC55S69 platform.devices.LPC55S69_CMSIS.LPC55S69 platform.devices.LPC55S69_startup.LPC55S69 platform.drivers.flexcomm_usart.LPC55S69 platform.drivers.flexcomm.LPC55S69 platform.drivers.lpc_iocon.LPC55S69 platform.drivers.lpc_gpio.LPC55S69 platform.utilities.assert.LPC55S69 utility.debug_console.LPC55S69 component.usart_adapter.LPC55S69 component.serial_manager.LPC55S69 component.lists.LPC55S69 component.serial_manager_uart.LPC55S69 platform.drivers.reset.LPC55S69 CMSIS_Include_core_cm.LPC55S69 CMSIS_Driver_Include.I2C.LPC55S69 CMSIS_Driver_Include.Common.LPC55S69 CMSIS_Driver_Include.SPI.LPC55S69 middleware.freertos-kernel.LPC55S69 middleware.freertos-kernel.extension.LPC55S69 platform.utilities.misc_utilities.LPC55S69 platform.devices.LPC55S69_system.LPC55S69" category="lvgl_examples">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
|
||||
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.ccnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
|
|
@ -59,6 +59,10 @@
|
|||
<value>SDK_OS_FREE_RTOS</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.preprocessor.def" type="stringList">
|
||||
<value>SERIAL_PORT_TYPE_UART=1</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.gas.hdrlib.newlibnano</value>
|
||||
</option>
|
||||
|
|
@ -71,15 +75,36 @@
|
|||
<option id="com.crt.advproject.gcc.specs" type="enum">
|
||||
<value>com.crt.advproject.gcc.specs.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.gcc.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.gcc.link.hdrlib.newlibnano.nohost</value>
|
||||
<option id="com.crt.advproject.cpp.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.cpp.hdrlib.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.fpu" type="enum">
|
||||
<value>com.crt.advproject.link.fpu.fpv5sp.hard</value>
|
||||
<option id="com.crt.advproject.cpp.specs" type="enum">
|
||||
<value>com.crt.advproject.cpp.specs.newlibnano</value>
|
||||
</option>
|
||||
<option id="gnu.c.link.option.nostdlibs" type="boolean">
|
||||
<option id="com.crt.advproject.link.cpp.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.cpp.link.hdrlib.newlibnano.nohost</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.link.cpp.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.link.option.nostdlibs" type="boolean">
|
||||
<value>true</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.cpp.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnupp11</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.other.other" type="string">
|
||||
<value>-Wno-format -mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -fno-rtti -fno-exceptions</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
|
|
@ -92,12 +117,6 @@
|
|||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-Wno-format -mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
|
|
|
|||
|
|
@ -22,14 +22,14 @@ SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
|||
SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
|
||||
|
||||
project(usb_pd_freertos)
|
||||
project(lvgl_guider_bm)
|
||||
|
||||
set(MCUX_BUILD_TYPES debug release)
|
||||
|
||||
set(MCUX_SDK_PROJECT_NAME usb_pd_freertos.elf)
|
||||
set(MCUX_SDK_PROJECT_NAME lvgl_guider_bm.elf)
|
||||
|
||||
if (NOT DEFINED SdkRootDirPath)
|
||||
SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
|
||||
SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
|
||||
endif()
|
||||
|
||||
include(${ProjDirPath}/flags.cmake)
|
||||
|
|
@ -37,78 +37,85 @@ include(${ProjDirPath}/flags.cmake)
|
|||
include(${ProjDirPath}/config.cmake)
|
||||
|
||||
add_executable(${MCUX_SDK_PROJECT_NAME}
|
||||
"${ProjDirPath}/../pd_board_config.h"
|
||||
"${ProjDirPath}/../pd_app_demo.c"
|
||||
"${ProjDirPath}/../pd_app.c"
|
||||
"${ProjDirPath}/../pd_app.h"
|
||||
"${ProjDirPath}/../pd_command_app.c"
|
||||
"${ProjDirPath}/../pd_command_interface.c"
|
||||
"${ProjDirPath}/../pd_command_interface.h"
|
||||
"${ProjDirPath}/../pd_power_app.c"
|
||||
"${ProjDirPath}/../pd_power_interface.c"
|
||||
"${ProjDirPath}/../pd_power_interface.h"
|
||||
"${ProjDirPath}/../usb_pd_config.h"
|
||||
"${ProjDirPath}/../pd_power_nx20p3483.c"
|
||||
"${ProjDirPath}/../pd_power_nx20p3483.h"
|
||||
"${ProjDirPath}/../FreeRTOSConfig.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/RTE_Device.h"
|
||||
"${ProjDirPath}/../lvgl_guider_bm.c"
|
||||
"${ProjDirPath}/../lv_conf.h"
|
||||
"${ProjDirPath}/../pin_mux.c"
|
||||
"${ProjDirPath}/../pin_mux.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/images/images.c"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/guider_fonts/guider_fonts.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/guider_customer_fonts/guider_customer_fonts.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/gui_guider.c"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/gui_guider.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/events_init.c"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/events_init.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/custom/custom.c"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/custom/custom.h"
|
||||
"${ProjDirPath}/../board.c"
|
||||
"${ProjDirPath}/../board.h"
|
||||
"${ProjDirPath}/../clock_config.c"
|
||||
"${ProjDirPath}/../clock_config.h"
|
||||
"${ProjDirPath}/../pin_mux.c"
|
||||
"${ProjDirPath}/../pin_mux.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_support.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_support.c"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_demo_utils.h"
|
||||
"${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_demo_utils.c"
|
||||
)
|
||||
|
||||
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
|
||||
${ProjDirPath}/..
|
||||
${SdkRootDirPath}/boards/lpcxpresso55s69
|
||||
${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples
|
||||
${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated
|
||||
${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/custom
|
||||
${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/guider_customer_fonts
|
||||
${SdkRootDirPath}/boards/lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/generated/guider_fonts
|
||||
)
|
||||
|
||||
set(CMAKE_MODULE_PATH
|
||||
${SdkRootDirPath}/middleware/usb
|
||||
${SdkRootDirPath}/components/ili9341
|
||||
${SdkRootDirPath}/components/ft6x06
|
||||
${SdkRootDirPath}/devices/LPC55S69/drivers
|
||||
${SdkRootDirPath}/components/i2c
|
||||
${SdkRootDirPath}/rtos/freertos/freertos-kernel
|
||||
${SdkRootDirPath}/components/osa
|
||||
${SdkRootDirPath}/devices/LPC55S69/cmsis_drivers
|
||||
${SdkRootDirPath}/middleware/lvgl
|
||||
${SdkRootDirPath}/devices/LPC55S69
|
||||
${SdkRootDirPath}/devices/LPC55S69/utilities
|
||||
${SdkRootDirPath}/components/uart
|
||||
${SdkRootDirPath}/components/serial_manager
|
||||
${SdkRootDirPath}/components/lists
|
||||
${SdkRootDirPath}/components/gpio
|
||||
${SdkRootDirPath}/components/timer
|
||||
${SdkRootDirPath}/CMSIS/Core/Include
|
||||
${SdkRootDirPath}/CMSIS/Driver/Include
|
||||
)
|
||||
|
||||
# include modules
|
||||
include(middleware_usb_pd_phy_ptn5110_LPC55S69_cm33_core0)
|
||||
include(driver_ili9341_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_usb_pd_LPC55S69_cm33_core0)
|
||||
include(driver_ft6x06_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_lpc_dma_LPC55S69_cm33_core0)
|
||||
include(driver_flexcomm_spi_dma_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_i2c_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_spi_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_inputmux_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_inputmux_connections_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_i2c_dma_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_flexcomm_i2c_adapter_LPC55S69_cm33_core0)
|
||||
include(driver_lpc_dma_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_mrt_LPC55S69_cm33_core0)
|
||||
include(driver_common_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_gint_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_freertos-kernel_cm33_nonsecure_port_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_freertos-kernel_heap_4_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_osa_free_rtos_LPC55S69_cm33_core0)
|
||||
include(middleware_lvgl_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_clock_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_power_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_common_LPC55S69_cm33_core0)
|
||||
|
||||
include(device_LPC55S69_CMSIS_LPC55S69_cm33_core0)
|
||||
|
||||
include(device_LPC55S69_startup_LPC55S69_cm33_core0)
|
||||
|
|
@ -117,11 +124,9 @@ include(driver_flexcomm_usart_LPC55S69_cm33_core0)
|
|||
|
||||
include(driver_flexcomm_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_lpc_gpio_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_lpc_iocon_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_reset_LPC55S69_cm33_core0)
|
||||
include(driver_lpc_gpio_LPC55S69_cm33_core0)
|
||||
|
||||
include(utility_assert_LPC55S69_cm33_core0)
|
||||
|
||||
|
|
@ -135,25 +140,15 @@ include(component_lists_LPC55S69_cm33_core0)
|
|||
|
||||
include(component_serial_manager_uart_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_lpc_gpio_adapter_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_mrt_adapter_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_inputmux_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_pint_LPC55S69_cm33_core0)
|
||||
include(driver_reset_LPC55S69_cm33_core0)
|
||||
|
||||
include(CMSIS_Include_core_cm_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_inputmux_connections_LPC55S69_cm33_core0)
|
||||
include(CMSIS_Driver_Include_I2C_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_osa_LPC55S69_cm33_core0)
|
||||
include(CMSIS_Driver_Include_Common_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_usb_pd_common_header_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_freertos-kernel_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_freertos-kernel_extension_LPC55S69_cm33_core0)
|
||||
include(CMSIS_Driver_Include_SPI_LPC55S69_cm33_core0)
|
||||
|
||||
include(utilities_misc_utilities_LPC55S69_cm33_core0)
|
||||
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0;
|
||||
|
||||
/* Specify the memory areas */
|
||||
|
|
@ -2,14 +2,14 @@ if exist CMakeFiles (RD /s /Q CMakeFiles)
|
|||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
mingw32-make -j
|
||||
|
||||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
mingw32-make -j
|
||||
|
||||
IF "%1" == "" ( pause )
|
||||
|
|
@ -3,13 +3,13 @@ if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
|||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
make -j
|
||||
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
make -j
|
||||
|
||||
|
|
@ -2,5 +2,5 @@ if exist CMakeFiles (RD /s /Q CMakeFiles)
|
|||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
mingw32-make -j 2> build_log.txt
|
||||
|
|
@ -3,5 +3,5 @@ if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
|||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
make -j 2>&1 | tee build_log.txt
|
||||
|
|
@ -2,5 +2,5 @@ if exist CMakeFiles (RD /s /Q CMakeFiles)
|
|||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
mingw32-make -j 2> build_log.txt
|
||||
|
|
@ -3,5 +3,5 @@ if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
|||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
make -j 2>&1 | tee build_log.txt
|
||||
|
|
@ -2,4 +2,3 @@
|
|||
set(CONFIG_USE_driver_power_LPC55S69_cm33_core0 true)
|
||||
set(CONFIG_USE_component_serial_manager_uart_LPC55S69_cm33_core0 true)
|
||||
set(CONFIG_USE_driver_flexcomm_usart_LPC55S69_cm33_core0 true)
|
||||
set(CONFIG_USE_middleware_baremetal_LPC55S69_cm33_core0 true)
|
||||
|
|
@ -28,16 +28,14 @@ SET(CMAKE_ASM_FLAGS_RELEASE " \
|
|||
")
|
||||
SET(CMAKE_C_FLAGS_DEBUG " \
|
||||
${CMAKE_C_FLAGS_DEBUG} \
|
||||
-D_DEBUG=1 \
|
||||
-DDEBUG \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0=1 \
|
||||
-DSDK_OS_FREE_RTOS \
|
||||
-DUSB_STACK_FREERTOS_HEAP_SIZE=8192 \
|
||||
-DI2C_RETRY_TIMES=40000 \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DLV_CONF_INCLUDE_SIMPLE=1 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-Wno-format \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
|
|
@ -55,15 +53,13 @@ SET(CMAKE_C_FLAGS_DEBUG " \
|
|||
")
|
||||
SET(CMAKE_C_FLAGS_RELEASE " \
|
||||
${CMAKE_C_FLAGS_RELEASE} \
|
||||
-D_DEBUG=0 \
|
||||
-DNDEBUG \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0=1 \
|
||||
-DSDK_OS_FREE_RTOS \
|
||||
-DUSB_STACK_FREERTOS_HEAP_SIZE=8192 \
|
||||
-DI2C_RETRY_TIMES=40000 \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DLV_CONF_INCLUDE_SIMPLE=1 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-Wno-format \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
|
|
@ -87,6 +83,7 @@ SET(CMAKE_CXX_FLAGS_DEBUG " \
|
|||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-Wno-format \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
|
|
@ -110,6 +107,7 @@ SET(CMAKE_CXX_FLAGS_RELEASE " \
|
|||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-Wno-format \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
|
|
@ -149,6 +147,8 @@ SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
|
|||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
-Xlinker \
|
||||
--defsym=__stack_size__=0x1000 \
|
||||
${FPU} \
|
||||
${SPECS} \
|
||||
-T${ProjDirPath}/LPC55S69_cm33_core0_flash.ld -static \
|
||||
|
|
@ -175,6 +175,8 @@ SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
|
|||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
-Xlinker \
|
||||
--defsym=__stack_size__=0x1000 \
|
||||
${FPU} \
|
||||
${SPECS} \
|
||||
-T${ProjDirPath}/LPC55S69_cm33_core0_flash.ld -static \
|
||||
|
|
@ -0,0 +1,814 @@
|
|||
/**
|
||||
* @file lv_conf.h
|
||||
* Configuration file for v8.3.2
|
||||
*/
|
||||
|
||||
#ifndef LV_CONF_H
|
||||
#define LV_CONF_H
|
||||
/* clang-format off */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*====================
|
||||
Graphical settings
|
||||
*====================*/
|
||||
|
||||
/* Color depth:
|
||||
* - 1: 1 byte per pixel
|
||||
* - 8: RGB332
|
||||
* - 16: RGB565
|
||||
* - 32: ARGB8888
|
||||
*/
|
||||
#define LV_COLOR_DEPTH 16
|
||||
|
||||
/* Swap the 2 bytes of RGB565 color.
|
||||
* Useful if the display has a 8 bit interface (e.g. SPI)*/
|
||||
#define LV_COLOR_16_SWAP 1
|
||||
|
||||
/*Enable features to draw on transparent background.
|
||||
*It's required if opa, and transform_* style properties are used.
|
||||
*Can be also used if the UI is above another layer, e.g. an OSD menu or video player.*//* 1: Enable screen transparency.
|
||||
* Useful for OSD or other overlapping GUIs.
|
||||
* Requires `LV_COLOR_DEPTH = 32` colors and the screen's style should be modified: `style.body.opa = ...`*/
|
||||
#define LV_COLOR_SCREEN_TRANSP 0
|
||||
|
||||
/* Adjust color mix functions rounding. GPUs might calculate color mix (blending) differently.
|
||||
* 0: round down, 64: round up from x.75, 128: round up from half, 192: round up from x.25, 254: round up */
|
||||
#define LV_COLOR_MIX_ROUND_OFS (LV_COLOR_DEPTH == 32 ? 0: 128)
|
||||
|
||||
/*Images pixels with this color will not be drawn (if they are chroma keyed)*/
|
||||
#define LV_COLOR_CHROMA_KEY lv_color_hex(0x00ff00) /*lv_color_hex(0x00ff00): pure green*/
|
||||
|
||||
/* Default display refresh period.
|
||||
* Can be changed in the display driver (`lv_disp_drv_t`).*/
|
||||
#define LV_DISP_DEF_REFR_PERIOD 30 /*[ms]*/
|
||||
|
||||
/*=========================
|
||||
Memory manager settings
|
||||
*=========================*/
|
||||
|
||||
/* LittelvGL's internal memory manager's settings.
|
||||
* The graphical objects and other related data are stored here. */
|
||||
|
||||
/* 1: use custom malloc/free, 0: use the built-in `lv_mem_alloc` and `lv_mem_free` */
|
||||
#define LV_MEM_CUSTOM 0
|
||||
#if LV_MEM_CUSTOM == 0
|
||||
/* Size of the memory used by `lv_mem_alloc` in bytes (>= 2kB)*/
|
||||
# define LV_MEM_SIZE (32U * 1024U)
|
||||
|
||||
/* Set an address for the memory pool instead of allocating it as an array.
|
||||
* Can be in external SRAM too. */
|
||||
# define LV_MEM_ADR 0
|
||||
|
||||
/*Instead of an address give a memory allocator that will be called to get a memory pool for LVGL. E.g. my_malloc*/
|
||||
#if LV_MEM_ADR == 0
|
||||
#undef LV_MEM_POOL_INCLUDE
|
||||
#undef LV_MEM_POOL_ALLOC
|
||||
#endif
|
||||
|
||||
#else /*LV_MEM_CUSTOM*/
|
||||
# define LV_MEM_CUSTOM_INCLUDE "FreeRTOS.h" /*Header for the dynamic memory function*/
|
||||
# define LV_MEM_CUSTOM_ALLOC pvPortMalloc /*Wrapper to malloc*/
|
||||
# define LV_MEM_CUSTOM_FREE vPortFree /*Wrapper to free*/
|
||||
#endif /*LV_MEM_CUSTOM*/
|
||||
|
||||
/*Number of the intermediate memory buffer used during rendering and other internal processing mechanisms.
|
||||
*You will see an error log message if there wasn't enough buffers. */
|
||||
#define LV_MEM_BUF_MAX_NUM 16
|
||||
|
||||
/* Use the standard memcpy and memset instead of LVGL's own functions.
|
||||
* The standard functions might or might not be faster depending on their implementation. */
|
||||
#define LV_MEMCPY_MEMSET_STD 0
|
||||
|
||||
/* Garbage Collector settings
|
||||
* Used if lvgl is binded to higher level language and the memory is managed by that language */
|
||||
#define LV_ENABLE_GC 0
|
||||
#if LV_ENABLE_GC != 0
|
||||
# define LV_GC_INCLUDE "gc.h" /*Include Garbage Collector related things*/
|
||||
#endif /* LV_ENABLE_GC */
|
||||
|
||||
/* Input device read period in milliseconds */
|
||||
#define LV_INDEV_DEF_READ_PERIOD 30
|
||||
|
||||
/*==================
|
||||
* Feature usage
|
||||
*==================*/
|
||||
|
||||
/* 1: Enable complex draw engine*/
|
||||
#define LV_DRAW_COMPLEX 1
|
||||
#if LV_DRAW_COMPLEX
|
||||
/* Allow buffering some shadow calculation
|
||||
* LV_SHADOW_CACHE_SIZE is the max. shadow size to buffer,
|
||||
* where shadow size is `shadow_width + radius`
|
||||
* Caching has LV_SHADOW_CACHE_SIZE^2 RAM cost*/
|
||||
#define LV_SHADOW_CACHE_SIZE 0
|
||||
|
||||
/* Set number of maximally cached circle data.
|
||||
* The circumference of 1/4 circle are saved for anti-aliasing
|
||||
* radius * 4 bytes are used per circle (the most often used radiuses are saved)
|
||||
* 0: to disable caching */
|
||||
#define LV_CIRCLE_CACHE_SIZE 4
|
||||
#endif
|
||||
|
||||
/* 1: Enable GPU interface*/
|
||||
#define LV_USE_GPU_STM32_DMA2D 0
|
||||
/*If enabling LV_USE_GPU_STM32_DMA2D, LV_GPU_DMA2D_CMSIS_INCLUDE must be defined to include path of CMSIS header of target processor
|
||||
e.g. "stm32f769xx.h" or "stm32f429xx.h" */
|
||||
#define LV_GPU_DMA2D_CMSIS_INCLUDE
|
||||
/*Use NXP's PXP GPU iMX RTxxx platforms*/
|
||||
#define LV_USE_GPU_NXP_PXP 0
|
||||
#if LV_USE_GPU_NXP_PXP
|
||||
/*1: Add default bare metal and FreeRTOS interrupt handling routines for PXP (lv_gpu_nxp_pxp_osa.c)
|
||||
* and call lv_gpu_nxp_pxp_init() automatically during lv_init(). Note that symbol SDK_OS_FREE_RTOS
|
||||
* has to be defined in order to use FreeRTOS OSA, otherwise bare-metal implementation is selected.
|
||||
*0: lv_gpu_nxp_pxp_init() has to be called manually before lv_init()
|
||||
*/
|
||||
#define LV_USE_GPU_NXP_PXP_AUTO_INIT 0
|
||||
#endif
|
||||
|
||||
/*Use NXP's VG-Lite GPU iMX RTxxx platforms*/
|
||||
#define LV_USE_GPU_NXP_VG_LITE 0
|
||||
|
||||
|
||||
/*Use SDL renderer API. Requires LV_USE_EXTERNAL_RENDERER*/
|
||||
#define LV_USE_GPU_SDL 0
|
||||
#if LV_USE_GPU_SDL
|
||||
#define LV_GPU_SDL_INCLUDE_PATH <SDL2/SDL.h>
|
||||
/*Texture cache size, 8MB by default*/
|
||||
#define LV_GPU_SDL_LRU_SIZE (1024 * 1024 * 8)
|
||||
/*Custom blend mode for mask drawing, disable if you need to link with older SDL2 lib*/
|
||||
#define LV_GPU_SDL_CUSTOM_BLEND_MODE (SDL_VERSION_ATLEAST(2, 0, 6))
|
||||
#endif
|
||||
|
||||
/*1: Add a `user_data` to drivers and objects*/
|
||||
#define LV_USE_USER_DATA 0
|
||||
|
||||
/*1: Show CPU usage and FPS count in the right bottom corner*/
|
||||
#define LV_USE_PERF_MONITOR 0
|
||||
#if LV_USE_PERF_MONITOR
|
||||
#define LV_USE_PERF_MONITOR_POS LV_ALIGN_BOTTOM_RIGHT
|
||||
#endif
|
||||
|
||||
/* Show the used memory and the memory fragmentation in the left bottom corner. Requires LV_MEM_CUSTOM = 0 */
|
||||
#define LV_USE_MEM_MONITOR 0
|
||||
#if LV_USE_MEM_MONITOR
|
||||
#define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT
|
||||
#endif
|
||||
|
||||
/* Draw random colored rectangles over the redrawn areas */
|
||||
#define LV_USE_REFR_DEBUG 0
|
||||
|
||||
/**
|
||||
* "Simple layers" are used when a widget has `style_opa < 255` to buffer the widget into a layer
|
||||
* and blend it as an image with the given opacity.
|
||||
* Note that `bg_opa`, `text_opa` etc don't require buffering into layer)
|
||||
* The widget can be buffered in smaller chunks to avoid using large buffers.
|
||||
*
|
||||
* - LV_LAYER_SIMPLE_BUF_SIZE: [bytes] the optimal target buffer size. LVGL will try to allocate it
|
||||
* - LV_LAYER_SIMPLE_FALLBACK_BUF_SIZE: [bytes] used if `LV_LAYER_SIMPLE_BUF_SIZE` couldn't be allocated.
|
||||
*
|
||||
* Both buffer sizes are in bytes.
|
||||
* "Transformed layers" (where transform_angle/zoom properties are used) use larger buffers
|
||||
* and can't be drawn in chunks. So these settings affects only widgets with opacity.
|
||||
*/
|
||||
#define LV_LAYER_SIMPLE_BUF_SIZE (24 * 1024)
|
||||
#define LV_LAYER_SIMPLE_FALLBACK_BUF_SIZE (3 * 1024)
|
||||
|
||||
/* Default image cache size. Image caching keeps the images opened.
|
||||
* If only the built-in image formats are used there is no real advantage of caching.
|
||||
* (I.e. no new image decoder is added)
|
||||
* With complex image decoders (e.g. PNG or JPG) caching can save the continuous open/decode of images.
|
||||
* However the opened images might consume additional RAM.
|
||||
* Set it to 0 to disable caching */
|
||||
#define LV_IMG_CACHE_DEF_SIZE 1
|
||||
|
||||
/*Number of stops allowed per gradient. Increase this to allow more stops.
|
||||
*This adds (sizeof(lv_color_t) + 1) bytes per additional stop*/
|
||||
#define LV_GRADIENT_MAX_STOPS 2
|
||||
|
||||
/*Default gradient buffer size.
|
||||
*When LVGL calculates the gradient "maps" it can save them into a cache to avoid calculating them again.
|
||||
*LV_GRAD_CACHE_DEF_SIZE sets the size of this cache in bytes.
|
||||
*If the cache is too small the map will be allocated only while it's required for the drawing.
|
||||
*0 mean no caching.*/
|
||||
#define LV_GRAD_CACHE_DEF_SIZE 0
|
||||
|
||||
/*Allow dithering the gradients (to achieve visual smooth color gradients on limited color depth display)
|
||||
*LV_DITHER_GRADIENT implies allocating one or two more lines of the object's rendering surface
|
||||
*The increase in memory consumption is (32 bits * object width) plus 24 bits * object width if using error diffusion */
|
||||
#define LV_DITHER_GRADIENT 0
|
||||
#if LV_DITHER_GRADIENT
|
||||
/*Add support for error diffusion dithering.
|
||||
*Error diffusion dithering gets a much better visual result, but implies more CPU consumption and memory when drawing.
|
||||
*The increase in memory consumption is (24 bits * object's width)*/
|
||||
#define LV_DITHER_ERROR_DIFFUSION 0
|
||||
#endif
|
||||
|
||||
/* Maximum buffer size to allocate for rotation. Only used if software rotation is enabled in the display driver. */
|
||||
#define LV_DISP_ROT_MAX_BUF (10*1024)
|
||||
|
||||
/*=====================
|
||||
* Compiler settings
|
||||
*====================*/
|
||||
|
||||
/* For big endian systems set to 1 */
|
||||
#define LV_BIG_ENDIAN_SYSTEM 0
|
||||
|
||||
/* Define a custom attribute to `lv_tick_inc` function */
|
||||
#define LV_ATTRIBUTE_TICK_INC
|
||||
|
||||
/* Define a custom attribute to `lv_timer_handler` function */
|
||||
#define LV_ATTRIBUTE_TIMER_HANDLER
|
||||
|
||||
/* Define a custom attribute to `lv_disp_flush_ready` function */
|
||||
#define LV_ATTRIBUTE_FLUSH_READY
|
||||
|
||||
/* Required alignment size for buffers */
|
||||
#define LV_ATTRIBUTE_MEM_ALIGN_SIZE
|
||||
|
||||
/* With size optimization (-Os) the compiler might not align data to
|
||||
* 4 or 8 byte boundary. Some HW may need even 32 or 64 bytes.
|
||||
* This alignment will be explicitly applied where needed.
|
||||
* LV_ATTRIBUTE_MEM_ALIGN_SIZE should be used to specify required align size.
|
||||
* E.g. __attribute__((aligned(LV_ATTRIBUTE_MEM_ALIGN_SIZE))) */
|
||||
#define LV_ATTRIBUTE_MEM_ALIGN
|
||||
|
||||
/* Attribute to mark large constant arrays for example
|
||||
* font's bitmaps */
|
||||
#define LV_ATTRIBUTE_LARGE_CONST
|
||||
|
||||
/* Complier prefix for a big array declaration in RAM. */
|
||||
#define LV_ATTRIBUTE_LARGE_RAM_ARRAY
|
||||
|
||||
/* Prefix performance critical functions to place them into a faster memory (e.g RAM)
|
||||
* Uses 15-20 kB extra memory */
|
||||
#define LV_ATTRIBUTE_FAST_MEM
|
||||
|
||||
/* Export integer constant to binding.
|
||||
* This macro is used with constants in the form of LV_<CONST> that
|
||||
* should also appear on lvgl binding API such as Micropython
|
||||
*
|
||||
* The default value just prevents a GCC warning.
|
||||
*/
|
||||
#define LV_EXPORT_CONST_INT(int_value) struct _silence_gcc_warning
|
||||
|
||||
/* Extend the default -32k..32k coordinate range to -4M..4M by using int32_t for coordinates instead of int16_t. */
|
||||
#define LV_USE_LARGE_COORD 0
|
||||
|
||||
/* Prefix variables that are used in GPU accelerated operations, often these need to be
|
||||
* placed in RAM sections that are DMA accessible */
|
||||
#define LV_ATTRIBUTE_DMA
|
||||
|
||||
/*===================
|
||||
* HAL settings
|
||||
*==================*/
|
||||
|
||||
/* 1: use a custom tick source.
|
||||
* It removes the need to manually update the tick with `lv_tick_inc`) */
|
||||
#define LV_TICK_CUSTOM 0
|
||||
#if LV_TICK_CUSTOM == 1
|
||||
#define LV_TICK_CUSTOM_INCLUDE "something.h" /*Header for the sys time function*/
|
||||
#define LV_TICK_CUSTOM_SYS_TIME_EXPR (millis()) /*Expression evaluating to current systime in ms*/
|
||||
#endif /*LV_TICK_CUSTOM*/
|
||||
|
||||
/* Default Dot Per Inch. Used to initialize default sizes such as widgets sized, style paddings.
|
||||
* (Not so important, you can adjust it to modify default sizes and spaces) */
|
||||
#define LV_DPI_DEF 130 /* [px/inch] */
|
||||
|
||||
/*================
|
||||
* Log settings
|
||||
*===============*/
|
||||
|
||||
/*1: Enable the log module*/
|
||||
#define LV_USE_LOG 0
|
||||
#if LV_USE_LOG
|
||||
/* How important log should be added:
|
||||
* LV_LOG_LEVEL_TRACE A lot of logs to give detailed information
|
||||
* LV_LOG_LEVEL_INFO Log important events
|
||||
* LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem
|
||||
* LV_LOG_LEVEL_ERROR Only critical issue, when the system may fail
|
||||
* LV_LOG_LEVEL_USER Only logs added by the user
|
||||
* LV_LOG_LEVEL_NONE Do not log anything
|
||||
*/
|
||||
# define LV_LOG_LEVEL LV_LOG_LEVEL_WARN
|
||||
|
||||
/* 1: Print the log with 'printf';
|
||||
* 0: user need to register a callback with `lv_log_register_print_cb`*/
|
||||
# define LV_LOG_PRINTF 0
|
||||
|
||||
/* Enable/disable LV_LOG_TRACE in modules that produces a huge number of logs. */
|
||||
#define LV_LOG_TRACE_MEM 1
|
||||
#define LV_LOG_TRACE_TIMER 1
|
||||
#define LV_LOG_TRACE_INDEV 1
|
||||
#define LV_LOG_TRACE_DISP_REFR 1
|
||||
#define LV_LOG_TRACE_EVENT 1
|
||||
#define LV_LOG_TRACE_OBJ_CREATE 1
|
||||
#define LV_LOG_TRACE_LAYOUT 1
|
||||
#define LV_LOG_TRACE_ANIM 1
|
||||
#endif /*LV_USE_LOG*/
|
||||
|
||||
/*=================
|
||||
* Debug settings
|
||||
*================*/
|
||||
|
||||
/*Check if the parameter is NULL. (Quite fast) */
|
||||
#define LV_USE_ASSERT_NULL 1
|
||||
|
||||
/* Checks is the memory is successfully allocated or no. (Very fast, recommended) */
|
||||
#define LV_USE_ASSERT_MALLOC 1
|
||||
|
||||
/*Check the integrity of `lv_mem` after critical operations. (Slow)*/
|
||||
#define LV_USE_ASSERT_MEM_INTEGRITY 0
|
||||
|
||||
/* Check NULL, the object's type and existence (e.g. not deleted). (Quite slow)
|
||||
* If disabled `LV_USE_ASSERT_NULL` will be performed instead (if it's enabled) */
|
||||
#define LV_USE_ASSERT_OBJ 0
|
||||
|
||||
/* Add a custom handler when assert happens e.g. to restart the MCU */
|
||||
#define LV_ASSERT_HANDLER_INCLUDE <stdint.h>
|
||||
#define LV_ASSERT_HANDLER while(1); /* Halt by default */
|
||||
|
||||
/*Check if the styles are properly initialized. (Fast)*/
|
||||
#define LV_USE_ASSERT_STYLE 1
|
||||
|
||||
/*==================
|
||||
* FONT USAGE
|
||||
*===================*/
|
||||
|
||||
/* The built-in fonts contains the ASCII range and some Symbols with 4 bit-per-pixel.
|
||||
* The symbols are available via `LV_SYMBOL_...` defines
|
||||
* More info about fonts: https://docs.lvgl.com/#Fonts
|
||||
* To create a new font go to: https://lvgl.com/ttf-font-to-c-array
|
||||
*/
|
||||
|
||||
/* Montserrat fonts with bpp = 4
|
||||
* https://fonts.google.com/specimen/Montserrat */
|
||||
#define LV_FONT_MONTSERRAT_8 0
|
||||
#define LV_FONT_MONTSERRAT_10 0
|
||||
#define LV_FONT_MONTSERRAT_12 1
|
||||
#define LV_FONT_MONTSERRAT_14 0
|
||||
#define LV_FONT_MONTSERRAT_16 0
|
||||
#define LV_FONT_MONTSERRAT_18 0
|
||||
#define LV_FONT_MONTSERRAT_20 0
|
||||
#define LV_FONT_MONTSERRAT_22 0
|
||||
#define LV_FONT_MONTSERRAT_24 0
|
||||
#define LV_FONT_MONTSERRAT_26 0
|
||||
#define LV_FONT_MONTSERRAT_28 0
|
||||
#define LV_FONT_MONTSERRAT_30 0
|
||||
#define LV_FONT_MONTSERRAT_32 0
|
||||
#define LV_FONT_MONTSERRAT_34 0
|
||||
#define LV_FONT_MONTSERRAT_36 0
|
||||
#define LV_FONT_MONTSERRAT_38 0
|
||||
#define LV_FONT_MONTSERRAT_40 0
|
||||
#define LV_FONT_MONTSERRAT_42 0
|
||||
#define LV_FONT_MONTSERRAT_44 0
|
||||
#define LV_FONT_MONTSERRAT_46 0
|
||||
#define LV_FONT_MONTSERRAT_48 0
|
||||
|
||||
/* Demonstrate special features */
|
||||
#define LV_FONT_MONTSERRAT_12_SUBPX 0
|
||||
#define LV_FONT_MONTSERRAT_28_COMPRESSED 0 /*bpp = 3*/
|
||||
#define LV_FONT_DEJAVU_16_PERSIAN_HEBREW 0 /*Hebrew, Arabic, PErisan letters and all their forms*/
|
||||
#define LV_FONT_SIMSUN_16_CJK 0 /*1000 most common CJK radicals*/
|
||||
|
||||
/*Pixel perfect monospace font
|
||||
* http://pelulamu.net/unscii/ */
|
||||
#define LV_FONT_UNSCII_8 0
|
||||
#define LV_FONT_UNSCII_16 0
|
||||
|
||||
/* Optionally declare your custom fonts here.
|
||||
* You can use these fonts as default font too
|
||||
* and they will be available globally. E.g.
|
||||
* #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) \
|
||||
* LV_FONT_DECLARE(my_font_2)
|
||||
*/
|
||||
#define LV_FONT_CUSTOM_DECLARE
|
||||
|
||||
/* Always set a default font. */
|
||||
#define LV_FONT_DEFAULT &lv_font_montserrat_12
|
||||
|
||||
/* Enable it if you have fonts with a lot of characters.
|
||||
* The limit depends on the font size, font face and bpp
|
||||
* but with > 10,000 characters if you see issues probably you need to enable it.*/
|
||||
#define LV_FONT_FMT_TXT_LARGE 0
|
||||
|
||||
/* Enables/disables support for compressed fonts. If it's disabled, compressed
|
||||
* glyphs cannot be processed by the library and won't be rendered.
|
||||
*/
|
||||
#define LV_USE_FONT_COMPRESSED 1
|
||||
|
||||
/* Enable subpixel rendering */
|
||||
#define LV_USE_FONT_SUBPX 1
|
||||
#if LV_USE_FONT_SUBPX
|
||||
/* Set the pixel order of the display.
|
||||
* Important only if "subpx fonts" are used.
|
||||
* With "normal" font it doesn't matter.
|
||||
*/
|
||||
#define LV_FONT_SUBPX_BGR 0
|
||||
#endif
|
||||
|
||||
/*================
|
||||
* THEME USAGE
|
||||
*================*/
|
||||
|
||||
/* Mono-color theme for monochrome displays.
|
||||
* If LV_THEME_DEFAULT_COLOR_PRIMARY is LV_COLOR_BLACK the
|
||||
* texts and borders will be black and the background will be
|
||||
* white. Else the colors are inverted.
|
||||
* No flags. Set LV_THEME_DEFAULT_FLAG 0 */
|
||||
#define LV_USE_THEME_MONO 0
|
||||
|
||||
/* A simple, impressive and very complete theme */
|
||||
#define LV_USE_THEME_DEFAULT 1
|
||||
#if LV_USE_THEME_DEFAULT
|
||||
/* 0: Light mode; 1: Dark mode */
|
||||
#define LV_THEME_DEFAULT_DARK 0
|
||||
/* 1: Enable grow on press */
|
||||
#define LV_THEME_DEFAULT_GROW 1
|
||||
/* Default transition time in [ms] */
|
||||
#define LV_THEME_DEFAULT_TRANSITION_TIME 80
|
||||
#endif /* LV_USE_THEME_DEFAULT */
|
||||
|
||||
/* An very simple them that is a good starting point for a custom theme */
|
||||
#define LV_USE_THEME_BASIC 1
|
||||
|
||||
/*Enable drawing placeholders when glyph dsc is not found*/
|
||||
#define LV_USE_FONT_PLACEHOLDER 1
|
||||
|
||||
/*Enable drawing placeholders when glyph dsc is not found*/
|
||||
#define LV_USE_FONT_PLACEHOLDER 1
|
||||
|
||||
/*=================
|
||||
* Text settings
|
||||
*=================*/
|
||||
|
||||
/* Select a character encoding for strings.
|
||||
* Your IDE or editor should have the same character encoding
|
||||
* - LV_TXT_ENC_UTF8
|
||||
* - LV_TXT_ENC_ASCII
|
||||
* */
|
||||
#define LV_TXT_ENC LV_TXT_ENC_UTF8
|
||||
|
||||
/*Can break (wrap) texts on these chars*/
|
||||
#define LV_TXT_BREAK_CHARS " ,.;:-_"
|
||||
|
||||
/* If a word is at least this long, will break wherever "prettiest"
|
||||
* To disable, set to a value <= 0 */
|
||||
#define LV_TXT_LINE_BREAK_LONG_LEN 0
|
||||
|
||||
/* Minimum number of characters in a long word to put on a line before a break.
|
||||
* Depends on LV_TXT_LINE_BREAK_LONG_LEN. */
|
||||
#define LV_TXT_LINE_BREAK_LONG_PRE_MIN_LEN 3
|
||||
|
||||
/* Minimum number of characters in a long word to put on a line after a break.
|
||||
* Depends on LV_TXT_LINE_BREAK_LONG_LEN. */
|
||||
#define LV_TXT_LINE_BREAK_LONG_POST_MIN_LEN 3
|
||||
|
||||
/* The control character to use for signalling text recoloring. */
|
||||
#define LV_TXT_COLOR_CMD "#"
|
||||
|
||||
/* Support bidirectional texts.
|
||||
* Allows mixing Left-to-Right and Right-to-Left texts.
|
||||
* The direction will be processed according to the Unicode Bidirectioanl Algorithm:
|
||||
* https://www.w3.org/International/articles/inline-bidi-markup/uba-basics*/
|
||||
#define LV_USE_BIDI 0
|
||||
#if LV_USE_BIDI
|
||||
/* Set the default direction. Supported values:
|
||||
* `LV_BASE_DIR_LTR` Left-to-Right
|
||||
* `LV_BASE_DIR_RTL` Right-to-Left
|
||||
* `LV_BASE_DIR_AUTO` detect texts base direction */
|
||||
#define LV_BIDI_BASE_DIR_DEF LV_BASE_DIR_AUTO
|
||||
#endif
|
||||
|
||||
/* Enable Arabic/Persian processing
|
||||
* In these languages characters should be replaced with
|
||||
* an other form based on their position in the text */
|
||||
#define LV_USE_ARABIC_PERSIAN_CHARS 0
|
||||
|
||||
/*Change the built in (v)snprintf functions*/
|
||||
#define LV_SPRINTF_CUSTOM 0
|
||||
#if LV_SPRINTF_CUSTOM
|
||||
# define LV_SPRINTF_INCLUDE <stdio.h>
|
||||
# define lv_snprintf snprintf
|
||||
# define lv_vsnprintf vsnprintf
|
||||
#else /*!LV_SPRINTF_CUSTOM*/
|
||||
# define LV_SPRINTF_USE_FLOAT 0
|
||||
#endif /*LV_SPRINTF_CUSTOM*/
|
||||
|
||||
/*==================
|
||||
* LV OBJ X USAGE
|
||||
*================*/
|
||||
/*
|
||||
* Documentation of the object types: https://docs.lvgl.com/#Object-types
|
||||
*/
|
||||
|
||||
/*Arc (dependencies: -)*/
|
||||
#define LV_USE_ARC 1
|
||||
|
||||
#define LV_USE_ANIMIMG 1
|
||||
|
||||
/*Bar (dependencies: -)*/
|
||||
#define LV_USE_BAR 1
|
||||
|
||||
/*Button (dependencies: lv_cont*/
|
||||
#define LV_USE_BTN 1
|
||||
|
||||
/*Button matrix (dependencies: -)*/
|
||||
#define LV_USE_BTNMATRIX 1
|
||||
|
||||
/*Calendar (dependencies: -)*/
|
||||
#define LV_USE_CALENDAR 1
|
||||
#if LV_USE_CALENDAR
|
||||
# define LV_CALENDAR_WEEK_STARTS_MONDAY 0
|
||||
|
||||
#if LV_CALENDAR_WEEK_STARTS_MONDAY
|
||||
#define LV_CALENDAR_DEFAULT_DAY_NAMES {"Mo", "Tu", "We", "Th", "Fr", "Sa", "Su"}
|
||||
#else
|
||||
#define LV_CALENDAR_DEFAULT_DAY_NAMES {"Su", "Mo", "Tu", "We", "Th", "Fr", "Sa"}
|
||||
#endif
|
||||
#define LV_CALENDAR_DEFAULT_MONTH_NAMES {"January", "February", "March", "April", "May", "June", "July", "August", "September", "October", "November", "December"}
|
||||
#define LV_USE_CALENDAR_HEADER_ARROW 1
|
||||
#define LV_USE_CALENDAR_HEADER_DROPDOWN 1
|
||||
#endif
|
||||
|
||||
/*Canvas (dependencies: lv_img)*/
|
||||
#define LV_USE_CANVAS 1
|
||||
|
||||
/*Check box (dependencies: lv_btn, lv_label)*/
|
||||
#define LV_USE_CHECKBOX 1
|
||||
|
||||
/*Chart (dependencies: -)*/
|
||||
#define LV_USE_CHART 1
|
||||
|
||||
#define LV_USE_COLORWHEEL 1
|
||||
|
||||
/*Requires: lv_label*/
|
||||
#define LV_USE_DROPDOWN 1
|
||||
|
||||
/*Image (dependencies: lv_label*/
|
||||
#define LV_USE_IMG 1
|
||||
|
||||
/*Image Button (dependencies: lv_btn*/
|
||||
#define LV_USE_IMGBTN 1
|
||||
|
||||
/*Keyboard (dependencies: lv_btnm)*/
|
||||
#define LV_USE_KEYBOARD 1
|
||||
|
||||
/*Label (dependencies: -*/
|
||||
#define LV_USE_LABEL 1
|
||||
#if LV_USE_LABEL != 0
|
||||
|
||||
/*Enable selecting text of the label */
|
||||
# define LV_LABEL_TEXT_SELECTION 0
|
||||
|
||||
/*Store extra some info in labels (12 bytes) to speed up drawing of very long texts*/
|
||||
# define LV_LABEL_LONG_TXT_HINT 0
|
||||
#endif
|
||||
|
||||
/*LED (dependencies: -)*/
|
||||
#define LV_USE_LED 1
|
||||
|
||||
/*Line (dependencies: -*/
|
||||
#define LV_USE_LINE 1
|
||||
|
||||
/*List (dependencies: lv_page, lv_btn, lv_label, (lv_img optionally for icons ))*/
|
||||
#define LV_USE_LIST 1
|
||||
|
||||
#define LV_USE_MENU 1
|
||||
|
||||
#define LV_USE_METER 1
|
||||
|
||||
/*Message box (dependencies: lv_rect, lv_btnm, lv_label)*/
|
||||
#define LV_USE_MSGBOX 1
|
||||
|
||||
/*Preload (dependencies: lv_arc, lv_anim)*/
|
||||
#define LV_USE_SPINNER 1
|
||||
|
||||
/*Requires: lv_label*/
|
||||
#define LV_USE_ROLLER 1
|
||||
#if LV_USE_ROLLER != 0
|
||||
|
||||
/*Number of extra "pages" when the roller is infinite*/
|
||||
# define LV_ROLLER_INF_PAGES 7
|
||||
#endif
|
||||
|
||||
/*Slider (dependencies: lv_bar)*/
|
||||
#define LV_USE_SLIDER 1
|
||||
|
||||
/*Spinbox (dependencies: lv_ta)*/
|
||||
#define LV_USE_SPINBOX 1
|
||||
|
||||
/*Switch (dependencies: lv_slider)*/
|
||||
#define LV_USE_SWITCH 1
|
||||
|
||||
/*Text area (dependencies: lv_label, lv_page)*/
|
||||
#define LV_USE_TEXTAREA 1
|
||||
#if LV_USE_TEXTAREA != 0
|
||||
# define LV_TEXTAREA_DEF_PWD_SHOW_TIME 1500 /*ms*/
|
||||
#endif
|
||||
|
||||
#define LV_USE_TABLE 1
|
||||
|
||||
/*Tab (dependencies: lv_page, lv_btnm)*/
|
||||
#define LV_USE_TABVIEW 1
|
||||
# if LV_USE_TABVIEW != 0
|
||||
/*Time of slide animation [ms] (0: no animation)*/
|
||||
# define LV_TABVIEW_DEF_ANIM_TIME 0
|
||||
#endif
|
||||
|
||||
/*Tileview (dependencies: lv_page) */
|
||||
#define LV_USE_TILEVIEW 1
|
||||
|
||||
/*Window (dependencies: lv_cont, lv_btn, lv_label, lv_img, lv_page)*/
|
||||
#define LV_USE_WIN 1
|
||||
|
||||
#define LV_USE_SPAN 1
|
||||
#if LV_USE_SPAN
|
||||
/* A line text can contain maximum num of span descriptor */
|
||||
#define LV_SPAN_SNIPPET_STACK_SIZE 64
|
||||
#endif
|
||||
|
||||
/*-----------
|
||||
* Layouts
|
||||
*----------*/
|
||||
|
||||
/* A layout similar to Flexbox in CSS. */
|
||||
#define LV_USE_FLEX 1
|
||||
|
||||
/* A layout similar to Grid in CSS. */
|
||||
#define LV_USE_GRID 1
|
||||
|
||||
/*---------------------
|
||||
* 3rd party libraries
|
||||
*--------------------*/
|
||||
|
||||
|
||||
/*File system interfaces for common APIs */
|
||||
|
||||
/*API for fopen, fread, etc*/
|
||||
#define LV_USE_FS_STDIO 0
|
||||
#if LV_USE_FS_STDIO
|
||||
#define LV_FS_STDIO_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/
|
||||
#define LV_FS_STDIO_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/
|
||||
#define LV_FS_STDIO_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/
|
||||
#endif
|
||||
|
||||
/*API for open, read, etc*/
|
||||
#define LV_USE_FS_POSIX 0
|
||||
#if LV_USE_FS_POSIX
|
||||
#define LV_FS_POSIX_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/
|
||||
#define LV_FS_POSIX_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/
|
||||
#define LV_FS_POSIX_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/
|
||||
#endif
|
||||
|
||||
/*API for CreateFile, ReadFile, etc*/
|
||||
#define LV_USE_FS_WIN32 0
|
||||
#if LV_USE_FS_WIN32
|
||||
#define LV_FS_WIN32_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/
|
||||
#define LV_FS_WIN32_PATH "" /*Set the working directory. File/directory paths will be appended to it.*/
|
||||
#define LV_FS_WIN32_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/
|
||||
#endif
|
||||
|
||||
/*API for FATFS (needs to be added separately). Uses f_open, f_read, etc*/
|
||||
#define LV_USE_FS_FATFS 0
|
||||
#if LV_USE_FS_FATFS
|
||||
#define LV_FS_FATFS_LETTER '\0' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/
|
||||
#define LV_FS_FATFS_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/
|
||||
#endif
|
||||
|
||||
/*PNG decoder library*/
|
||||
#define LV_USE_PNG 0
|
||||
|
||||
/*BMP decoder library*/
|
||||
#define LV_USE_BMP 0
|
||||
|
||||
/* JPG + split JPG decoder library.
|
||||
* Split JPG is a custom format optimized for embedded systems. */
|
||||
#define LV_USE_SJPG 0
|
||||
|
||||
/*GIF decoder library*/
|
||||
#define LV_USE_GIF 0
|
||||
|
||||
/*QR code library*/
|
||||
#define LV_USE_QRCODE 0
|
||||
|
||||
/*FreeType library*/
|
||||
#define LV_USE_FREETYPE 0
|
||||
#if LV_USE_FREETYPE
|
||||
/*Memory used by FreeType to cache characters [bytes] (-1: no caching)*/
|
||||
#define LV_FREETYPE_CACHE_SIZE (16 * 1024)
|
||||
#if LV_FREETYPE_CACHE_SIZE >= 0
|
||||
/* 1: bitmap cache use the sbit cache, 0:bitmap cache use the image cache. */
|
||||
/* sbit cache:it is much more memory efficient for small bitmaps(font size < 256) */
|
||||
/* if font size >= 256, must be configured as image cache */
|
||||
#define LV_FREETYPE_SBIT_CACHE 0
|
||||
/* Maximum number of opened FT_Face/FT_Size objects managed by this cache instance. */
|
||||
/* (0:use system defaults) */
|
||||
#define LV_FREETYPE_CACHE_FT_FACES 0
|
||||
#define LV_FREETYPE_CACHE_FT_SIZES 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*Rlottie library*/
|
||||
#define LV_USE_RLOTTIE 0
|
||||
|
||||
/*FFmpeg library for image decoding and playing videos
|
||||
*Supports all major image formats so do not enable other image decoder with it*/
|
||||
#define LV_USE_FFMPEG 0
|
||||
#if LV_USE_FFMPEG
|
||||
/*Dump input information to stderr*/
|
||||
#define LV_FFMPEG_DUMP_FORMAT 0
|
||||
#endif
|
||||
|
||||
/*-----------
|
||||
* Others
|
||||
*----------*/
|
||||
|
||||
/*1: Enable API to take snapshot for object*/
|
||||
#define LV_USE_SNAPSHOT 1
|
||||
|
||||
/*1: Enable Monkey test*/
|
||||
#define LV_USE_MONKEY 0
|
||||
|
||||
/*1: Enable grid navigation*/
|
||||
#define LV_USE_GRIDNAV 0
|
||||
|
||||
|
||||
/*1: Enable lv_obj fragment*/
|
||||
#define LV_USE_FRAGMENT 0
|
||||
|
||||
/*1: Support using images as font in label or span widgets */
|
||||
#define LV_USE_IMGFONT 0
|
||||
|
||||
/*1: Enable a published subscriber based messaging system */
|
||||
#define LV_USE_MSG 0
|
||||
|
||||
/*1: Enable Pinyin input method*/
|
||||
/*Requires: lv_keyboard*/
|
||||
#define LV_USE_IME_PINYIN 0
|
||||
#if LV_USE_IME_PINYIN
|
||||
/*1: Use default thesaurus*/
|
||||
/*If you do not use the default thesaurus, be sure to use `lv_ime_pinyin` after setting the thesauruss*/
|
||||
#define LV_IME_PINYIN_USE_DEFAULT_DICT 1
|
||||
/*Set the maximum number of candidate panels that can be displayed*/
|
||||
/*This needs to be adjusted according to the size of the screen*/
|
||||
#define LV_IME_PINYIN_CAND_TEXT_NUM 6
|
||||
|
||||
/*Use 9 key input(k9)*/
|
||||
#define LV_IME_PINYIN_USE_K9_MODE 1
|
||||
#if LV_IME_PINYIN_USE_K9_MODE == 1
|
||||
#define LV_IME_PINYIN_K9_CAND_TEXT_NUM 3
|
||||
#endif // LV_IME_PINYIN_USE_K9_MODE
|
||||
#endif
|
||||
/*==================
|
||||
* EXAMPLES
|
||||
*==================*/
|
||||
|
||||
/* Enable the examples to be built with the library */
|
||||
#define LV_BUILD_EXAMPLES 1
|
||||
|
||||
/*===================
|
||||
* DEMO USAGE
|
||||
====================*/
|
||||
|
||||
/*Show some widget. It might be required to increase `LV_MEM_SIZE` */
|
||||
#define LV_USE_DEMO_WIDGETS 0
|
||||
#if LV_USE_DEMO_WIDGETS
|
||||
#define LV_DEMO_WIDGETS_SLIDESHOW 0
|
||||
#endif
|
||||
|
||||
/*Demonstrate the usage of encoder and keyboard*/
|
||||
#define LV_USE_DEMO_KEYPAD_AND_ENCODER 0
|
||||
|
||||
/*Benchmark your system*/
|
||||
#define LV_USE_DEMO_BENCHMARK 0
|
||||
#if LV_USE_DEMO_BENCHMARK
|
||||
/*Use RGB565A8 images with 16 bit color depth instead of ARGB8565*/
|
||||
#define LV_DEMO_BENCHMARK_RGB565A8 0
|
||||
#endif
|
||||
|
||||
/*Stress test for LVGL*/
|
||||
#define LV_USE_DEMO_STRESS 0
|
||||
|
||||
/*Music player demo*/
|
||||
#define LV_USE_DEMO_MUSIC 0
|
||||
#if LV_USE_DEMO_MUSIC
|
||||
# define LV_DEMO_MUSIC_SQUARE 0
|
||||
# define LV_DEMO_MUSIC_LANDSCAPE 0
|
||||
# define LV_DEMO_MUSIC_ROUND 0
|
||||
# define LV_DEMO_MUSIC_LARGE 0
|
||||
# define LV_DEMO_MUSIC_AUTO_PLAY 0
|
||||
#endif
|
||||
|
||||
/*==================
|
||||
* Non-user section
|
||||
*==================*/
|
||||
|
||||
#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS) /* Disable warnings for Visual Studio*/
|
||||
# define _CRT_SECURE_NO_WARNINGS
|
||||
#endif
|
||||
|
||||
/*--END OF LV_CONF_H--*/
|
||||
|
||||
/* clang-format on */
|
||||
#endif /*LV_CONF_H*/
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_debug_console.h"
|
||||
#include "lvgl_support.h"
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
#include "board.h"
|
||||
#include "lvgl.h"
|
||||
#include "gui_guider.h"
|
||||
#include "events_init.h"
|
||||
#include "custom.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* 1 ms per tick. */
|
||||
#ifndef LVGL_TICK_MS
|
||||
#define LVGL_TICK_MS 1U
|
||||
#endif
|
||||
|
||||
/* lv_task_handler is called every 5-tick. */
|
||||
#ifndef LVGL_TASK_PERIOD_TICK
|
||||
#define LVGL_TASK_PERIOD_TICK 5U
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
lv_ui guider_ui;
|
||||
static volatile uint32_t s_tick = 0U;
|
||||
static volatile bool s_lvglTaskPending = false;
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
static void DEMO_SetupTick(void);
|
||||
#if LV_USE_LOG
|
||||
static void print_cb(const char *buf);
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Main function
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/* Init board hardware. */
|
||||
/* attach main clock divide to FLEXCOMM0 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockFROHF96M();
|
||||
BOARD_InitDebugConsole();
|
||||
DEMO_SetupTick();
|
||||
#if LV_USE_LOG
|
||||
lv_log_register_print_cb(print_cb);
|
||||
#endif
|
||||
|
||||
lv_port_pre_init();
|
||||
lv_init();
|
||||
lv_port_disp_init();
|
||||
lv_port_indev_init();
|
||||
|
||||
setup_ui(&guider_ui);
|
||||
events_init(&guider_ui);
|
||||
custom_init(&guider_ui);
|
||||
|
||||
for (;;)
|
||||
{
|
||||
while (!s_lvglTaskPending)
|
||||
{
|
||||
}
|
||||
s_lvglTaskPending = false;
|
||||
|
||||
lv_task_handler();
|
||||
}
|
||||
}
|
||||
|
||||
static void DEMO_SetupTick(void)
|
||||
{
|
||||
if (0 != SysTick_Config(SystemCoreClock / (LVGL_TICK_MS * 1000U)))
|
||||
{
|
||||
PRINTF("Tick initialization failed\r\n");
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
s_tick++;
|
||||
lv_tick_inc(LVGL_TICK_MS);
|
||||
|
||||
if ((s_tick % LVGL_TASK_PERIOD_TICK) == 0U)
|
||||
{
|
||||
s_lvglTaskPending = true;
|
||||
}
|
||||
}
|
||||
|
||||
#if LV_USE_LOG
|
||||
static void print_cb(const char *buf)
|
||||
{
|
||||
PRINTF("\r%s\n", buf);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
|
||||
<externalDefinitions>
|
||||
<definition extID="cm33_core0_LPC55S69"/>
|
||||
<definition extID="driver.ili9341.LPC55S69"/>
|
||||
<definition extID="driver.ft6x06.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_spi_dma.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_i2c.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_spi.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_spi_cmsis.LPC55S69"/>
|
||||
<definition extID="platform.drivers.inputmux.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_i2c_cmsis.LPC55S69"/>
|
||||
<definition extID="platform.drivers.inputmux_connections.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_i2c_dma.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpc_dma.LPC55S69"/>
|
||||
<definition extID="platform.drivers.common.LPC55S69"/>
|
||||
<definition extID="middleware.lvgl.LPC55S69"/>
|
||||
<definition extID="platform.drivers.clock.LPC55S69"/>
|
||||
<definition extID="platform.drivers.power.LPC55S69"/>
|
||||
<definition extID="platform.devices.LPC55S69_CMSIS.LPC55S69"/>
|
||||
<definition extID="platform.devices.LPC55S69_startup.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm_usart.LPC55S69"/>
|
||||
<definition extID="platform.drivers.flexcomm.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpc_iocon.LPC55S69"/>
|
||||
<definition extID="platform.drivers.lpc_gpio.LPC55S69"/>
|
||||
<definition extID="platform.utilities.assert.LPC55S69"/>
|
||||
<definition extID="utility.debug_console.LPC55S69"/>
|
||||
<definition extID="component.usart_adapter.LPC55S69"/>
|
||||
<definition extID="component.serial_manager.LPC55S69"/>
|
||||
<definition extID="component.lists.LPC55S69"/>
|
||||
<definition extID="component.serial_manager_uart.LPC55S69"/>
|
||||
<definition extID="platform.drivers.reset.LPC55S69"/>
|
||||
<definition extID="CMSIS_Include_core_cm.LPC55S69"/>
|
||||
<definition extID="CMSIS_Driver_Include.I2C.LPC55S69"/>
|
||||
<definition extID="CMSIS_Driver_Include.Common.LPC55S69"/>
|
||||
<definition extID="CMSIS_Driver_Include.SPI.LPC55S69"/>
|
||||
<definition extID="platform.utilities.misc_utilities.LPC55S69"/>
|
||||
<definition extID="platform.devices.LPC55S69_system.LPC55S69"/>
|
||||
<definition extID="iar"/>
|
||||
<definition extID="mdk"/>
|
||||
<definition extID="armgcc"/>
|
||||
<definition extID="mcuxpresso"/>
|
||||
<definition extID="com.nxp.mcuxpresso"/>
|
||||
</externalDefinitions>
|
||||
<example id="lpcxpresso55s69_lvgl_guider_bm" name="lvgl_guider_bm" device_core="cm33_core0_LPC55S69" dependency="driver.ili9341.LPC55S69 driver.ft6x06.LPC55S69 platform.drivers.flexcomm_spi_dma.LPC55S69 platform.drivers.flexcomm_i2c.LPC55S69 platform.drivers.flexcomm_spi.LPC55S69 platform.drivers.flexcomm_spi_cmsis.LPC55S69 platform.drivers.inputmux.LPC55S69 platform.drivers.flexcomm_i2c_cmsis.LPC55S69 platform.drivers.inputmux_connections.LPC55S69 platform.drivers.flexcomm_i2c_dma.LPC55S69 platform.drivers.lpc_dma.LPC55S69 platform.drivers.common.LPC55S69 middleware.lvgl.LPC55S69 platform.drivers.clock.LPC55S69 platform.drivers.power.LPC55S69 platform.devices.LPC55S69_CMSIS.LPC55S69 platform.devices.LPC55S69_startup.LPC55S69 platform.drivers.flexcomm_usart.LPC55S69 platform.drivers.flexcomm.LPC55S69 platform.drivers.lpc_iocon.LPC55S69 platform.drivers.lpc_gpio.LPC55S69 platform.utilities.assert.LPC55S69 utility.debug_console.LPC55S69 component.usart_adapter.LPC55S69 component.serial_manager.LPC55S69 component.lists.LPC55S69 component.serial_manager_uart.LPC55S69 platform.drivers.reset.LPC55S69 CMSIS_Include_core_cm.LPC55S69 CMSIS_Driver_Include.I2C.LPC55S69 CMSIS_Driver_Include.Common.LPC55S69 CMSIS_Driver_Include.SPI.LPC55S69 platform.utilities.misc_utilities.LPC55S69 platform.devices.LPC55S69_system.LPC55S69" category="lvgl_examples">
|
||||
<projects>
|
||||
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.ccnature"/>
|
||||
</projects>
|
||||
<toolchainSettings>
|
||||
<toolchainSetting id_refs="com.nxp.mcuxpresso">
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
|
||||
<value>CPU_LPC55S69JBD100_cm33_core0</value>
|
||||
<value>LV_CONF_INCLUDE_SIMPLE=1</value>
|
||||
<value>SERIAL_PORT_TYPE_UART=1</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.preprocessor.def" type="stringList">
|
||||
<value>SERIAL_PORT_TYPE_UART=1</value>
|
||||
<value>MCUXPRESSO_SDK</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.gas.hdrlib.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.specs" type="enum">
|
||||
<value>com.crt.advproject.gas.specs.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.gcc.hdrlib.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.specs" type="enum">
|
||||
<value>com.crt.advproject.gcc.specs.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.cpp.hdrlib.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.specs" type="enum">
|
||||
<value>com.crt.advproject.cpp.specs.newlibnano</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.cpp.hdrlib" type="enum">
|
||||
<value>com.crt.advproject.cpp.link.hdrlib.newlibnano.nohost</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.link.cpp.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.link.option.nostdlibs" type="boolean">
|
||||
<value>true</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.link.memory.heapAndStack.cpp" type="string">
|
||||
<value>&Heap:Default;Default;Default&Stack:Default;Default;0x1000</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.fpu" type="enum">
|
||||
<value>com.crt.advproject.cpp.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.cpp.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnupp11</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.other.other" type="string">
|
||||
<value>-Wno-format -mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -fno-rtti -fno-exceptions</value>
|
||||
</option>
|
||||
<option id="gnu.cpp.compiler.option.warnings.toerrors" type="boolean">
|
||||
<value>false</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gcc.fpu" type="enum">
|
||||
<value>com.crt.advproject.gcc.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.optimization.flags" type="string">
|
||||
<value>-fno-common</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.c.misc.dialect" type="enum">
|
||||
<value>com.crt.advproject.misc.dialect.gnu99</value>
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.misc.other" type="string">
|
||||
<value>-Wno-format -mcpu=cortex-m33 -c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
|
||||
</option>
|
||||
<option id="com.crt.advproject.gas.fpu" type="enum">
|
||||
<value>com.crt.advproject.gas.fpu.fpv5sp.hard</value>
|
||||
</option>
|
||||
</toolchainSetting>
|
||||
</toolchainSettings>
|
||||
<include_paths>
|
||||
<include_path path="../.." project_relative_path="board" type="c_include"/>
|
||||
<include_path path="." project_relative_path="source" type="c_include"/>
|
||||
<include_path path="." project_relative_path="board" type="c_include"/>
|
||||
<include_path path="../generated" project_relative_path="generated" type="c_include"/>
|
||||
<include_path path="../custom" project_relative_path="custom" type="c_include"/>
|
||||
<include_path path="../generated/guider_customer_fonts" project_relative_path="generated/guider_customer_fonts" type="c_include"/>
|
||||
<include_path path="../generated/guider_fonts" project_relative_path="generated/guider_fonts" type="c_include"/>
|
||||
<include_path path="../.." project_relative_path="lpcxpresso55s69/lvgl_examples/lvgl_guider_bm/cm33_core0" type="c_include"/>
|
||||
<include_path path="../.." project_relative_path="source" type="c_include"/>
|
||||
<include_path path="." project_relative_path="source" type="asm_include"/>
|
||||
</include_paths>
|
||||
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
|
||||
<files mask="lvgl_guider_bm.ewd"/>
|
||||
<files mask="lvgl_guider_bm.ewp"/>
|
||||
<files mask="lvgl_guider_bm.eww"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="./" type="workspace" toolchain="mdk">
|
||||
<files mask="lvgl_guider_bm.uvprojx"/>
|
||||
<files mask="lvgl_guider_bm.uvoptx"/>
|
||||
<files mask="JLinkSettings.JLinkScript"/>
|
||||
<files mask="JLinkSettings.ini"/>
|
||||
<files mask="lvgl_guider_bm.uvmpw"/>
|
||||
</source>
|
||||
<source path="armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
|
||||
<files mask="build_all.bat"/>
|
||||
<files mask="build_all.sh"/>
|
||||
<files mask="clean.bat"/>
|
||||
<files mask="clean.sh"/>
|
||||
<files mask="CMakeLists.txt"/>
|
||||
<files mask="flags.cmake"/>
|
||||
<files mask="config.cmake"/>
|
||||
<files mask="build_debug.bat"/>
|
||||
<files mask="build_debug.sh"/>
|
||||
<files mask="build_release.bat"/>
|
||||
<files mask="build_release.sh"/>
|
||||
</source>
|
||||
<source path="../.." project_relative_path="board" type="c_include">
|
||||
<files mask="RTE_Device.h"/>
|
||||
<files mask="lvgl_support.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="src">
|
||||
<files mask="lvgl_guider_bm.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="source" type="c_include">
|
||||
<files mask="lv_conf.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="pin_mux.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="c_include">
|
||||
<files mask="pin_mux.h"/>
|
||||
</source>
|
||||
<source path="../generated/images" project_relative_path="generated/images" type="src">
|
||||
<files mask="images.c"/>
|
||||
</source>
|
||||
<source path="../generated/guider_fonts" project_relative_path="generated/guider_fonts" type="c_include">
|
||||
<files mask="guider_fonts.h"/>
|
||||
</source>
|
||||
<source path="../generated/guider_customer_fonts" project_relative_path="generated/guider_customer_fonts" type="c_include">
|
||||
<files mask="guider_customer_fonts.h"/>
|
||||
</source>
|
||||
<source path="../generated" project_relative_path="generated" type="src">
|
||||
<files mask="gui_guider.c"/>
|
||||
<files mask="events_init.c"/>
|
||||
</source>
|
||||
<source path="../generated" project_relative_path="generated" type="c_include">
|
||||
<files mask="gui_guider.h"/>
|
||||
<files mask="events_init.h"/>
|
||||
</source>
|
||||
<source path="../custom" project_relative_path="custom" type="src">
|
||||
<files mask="custom.c"/>
|
||||
</source>
|
||||
<source path="../custom" project_relative_path="custom" type="c_include">
|
||||
<files mask="custom.h"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="src">
|
||||
<files mask="board.c"/>
|
||||
<files mask="clock_config.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="board" type="c_include">
|
||||
<files mask="board.h"/>
|
||||
<files mask="clock_config.h"/>
|
||||
</source>
|
||||
<source path="../.." project_relative_path="board" type="src">
|
||||
<files mask="lvgl_support.c"/>
|
||||
</source>
|
||||
<source path="../.." project_relative_path="source" type="c_include">
|
||||
<files mask="lvgl_demo_utils.h"/>
|
||||
</source>
|
||||
<source path="../.." project_relative_path="source" type="src">
|
||||
<files mask="lvgl_demo_utils.c"/>
|
||||
</source>
|
||||
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
|
||||
<files mask="readme.txt"/>
|
||||
</source>
|
||||
<source path="iar" project_relative_path="LPC55S69/iar" type="linker" toolchain="iar">
|
||||
<files mask="LPC55S69_cm33_core0_flash.icf"/>
|
||||
</source>
|
||||
<source path="mdk" project_relative_path="LPC55S69/arm" type="linker" toolchain="mdk">
|
||||
<files mask="LPC55S69_cm33_core0_flash.scf"/>
|
||||
</source>
|
||||
<source path="armgcc" project_relative_path="LPC55S69/gcc" type="linker" toolchain="armgcc">
|
||||
<files mask="LPC55S69_cm33_core0_flash.ld"/>
|
||||
</source>
|
||||
</example>
|
||||
</ksdk:examples>
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -48,20 +48,6 @@ BOARD_InitPins:
|
|||
mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '24', peripheral: GPIO, signal: 'PIO1, 8', pin_signal: PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled, asw: disabled}
|
||||
- {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, mode: pullUp, slew_rate: standard, invert: disabled,
|
||||
open_drain: disabled}
|
||||
- {pin_num: '40', peripheral: GPIO, signal: 'PIO1, 10', pin_signal: PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3, mode: pullUp, slew_rate: standard, invert: disabled,
|
||||
open_drain: disabled}
|
||||
- {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '31', peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, mode: pullUp, slew_rate: standard, invert: disabled,
|
||||
open_drain: disabled}
|
||||
- {pin_num: '22', peripheral: GPIO, signal: 'PIO0, 15', pin_signal: PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2, mode: pullUp,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
|
@ -78,23 +64,6 @@ void BOARD_InitPins(void)
|
|||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t port0_pin15_config = (/* Pin is configured as PIO0_15 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is enabled */
|
||||
IOCON_PIO_ASW_EN);
|
||||
/* PORT0 PIN15 (coords: 22) is configured as PIO0_15 */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 15U, port0_pin15_config);
|
||||
|
||||
const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* No addition pin function */
|
||||
|
|
@ -124,9 +93,40 @@ void BOARD_InitPins(void)
|
|||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
|
||||
}
|
||||
|
||||
const uint32_t port1_pin10_config = (/* Pin is configured as PIO1_10 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
SPI8_InitPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '61', peripheral: FLEXCOMM8, signal: HS_SPI_SCK, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '60', peripheral: FLEXCOMM8, signal: HS_SPI_MOSI, pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '62', peripheral: FLEXCOMM8, signal: HS_SPI_MISO, pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '59', peripheral: FLEXCOMM8, signal: HS_SPI_SSEL1, pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : SPI8_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void SPI8_InitPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t port0_pin26_config = (/* Pin is configured as HS_SPI_MOSI */
|
||||
IOCON_PIO_FUNC9 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
|
|
@ -137,11 +137,11 @@ void BOARD_InitPins(void)
|
|||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN10 (coords: 40) is configured as PIO1_10 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 10U, port1_pin10_config);
|
||||
/* PORT0 PIN26 (coords: 60) is configured as HS_SPI_MOSI */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 26U, port0_pin26_config);
|
||||
|
||||
const uint32_t port1_pin4_config = (/* Pin is configured as PIO1_4 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
const uint32_t port1_pin1_config = (/* Pin is configured as HS_SPI_SSEL1 */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
|
|
@ -152,11 +152,11 @@ void BOARD_InitPins(void)
|
|||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 4U, port1_pin4_config);
|
||||
/* PORT1 PIN1 (coords: 59) is configured as HS_SPI_SSEL1 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 1U, port1_pin1_config);
|
||||
|
||||
const uint32_t port1_pin5_config = (/* Pin is configured as PIO1_5 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
const uint32_t port1_pin2_config = (/* Pin is configured as HS_SPI_SCK */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
|
|
@ -167,11 +167,11 @@ void BOARD_InitPins(void)
|
|||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN5 (coords: 31) is configured as PIO1_5 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 5U, port1_pin5_config);
|
||||
/* PORT1 PIN2 (coords: 61) is configured as HS_SPI_SCK */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 2U, port1_pin2_config);
|
||||
|
||||
const uint32_t port1_pin6_config = (/* Pin is configured as PIO1_6 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
const uint32_t port1_pin3_config = (/* Pin is configured as HS_SPI_MISO */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
|
|
@ -182,40 +182,29 @@ void BOARD_InitPins(void)
|
|||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 6U, port1_pin6_config);
|
||||
/* PORT1 PIN3 (coords: 62) is configured as HS_SPI_MISO */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 3U, port1_pin3_config);
|
||||
}
|
||||
|
||||
const uint32_t port1_pin7_config = (/* Pin is configured as PIO1_7 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 7U, port1_pin7_config);
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
SPI8_DeinitPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list: []
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
const uint32_t port1_pin8_config = (/* Pin is configured as PIO1_8 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is disabled */
|
||||
IOCON_PIO_ASW_DIS_DI);
|
||||
/* PORT1 PIN8 (coords: 24) is configured as PIO1_8 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 8U, port1_pin8_config);
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : SPI8_DeinitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void SPI8_DeinitPins(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
|
|
@ -224,9 +213,9 @@ void BOARD_InitPins(void)
|
|||
I2C4_InitPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
|
||||
- {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: enabled}
|
||||
- {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive,
|
||||
- {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
|
||||
slew_rate: standard, invert: disabled, open_drain: enabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
|
@ -246,8 +235,8 @@ void I2C4_InitPins(void)
|
|||
|
||||
const uint32_t port1_pin20_config = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
|
|
@ -261,8 +250,8 @@ void I2C4_InitPins(void)
|
|||
|
||||
const uint32_t port1_pin21_config = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
|
|
@ -280,11 +269,7 @@ void I2C4_InitPins(void)
|
|||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
I2C4_DeinitPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '4', peripheral: GPIO, signal: 'PIO1, 20', pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: inactive, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '30', peripheral: GPIO, signal: 'PIO1, 21', pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: inactive, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- pin_list: []
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
|
@ -298,38 +283,6 @@ I2C4_DeinitPins:
|
|||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void I2C4_DeinitPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t port1_pin20_config = (/* Pin is configured as PIO1_20 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN20 (coords: 4) is configured as PIO1_20 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 20U, port1_pin20_config);
|
||||
|
||||
const uint32_t port1_pin21_config = (/* Pin is configured as PIO1_21 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN21 (coords: 30) is configured as PIO1_21 */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 21U, port1_pin21_config);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -32,14 +32,10 @@ extern "C" {
|
|||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
#define IOCON_PIO_ASW_DIS_DI 0x00u /*!<@brief Analog switch is disabled */
|
||||
#define IOCON_PIO_ASW_EN 0x00u /*!<@brief Analog switch is enabled */
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
|
||||
#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
|
|
@ -49,10 +45,31 @@ void BOARD_InitBootPins(void);
|
|||
*/
|
||||
void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */
|
||||
#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */
|
||||
#define IOCON_PIO_FUNC9 0x09u /*!<@brief Selects pin function 9 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void SPI8_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void SPI8_DeinitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_EN 0x0200u /*!<@brief Open drain is enabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
|
|
@ -62,13 +79,6 @@ void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
|||
*/
|
||||
void I2C4_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
Overview
|
||||
========
|
||||
|
||||
This project is used to work with LVGL GUI Guider. The GUI Guider generated
|
||||
code is placed in the folder "generated". The example generated code shows a
|
||||
button in the panel.
|
||||
|
||||
Toolchain supported
|
||||
===================
|
||||
- IAR embedded Workbench 9.32.1
|
||||
- Keil MDK 5.37
|
||||
- GCC ARM Embedded 10.3.1
|
||||
- MCUXpresso 11.7.0
|
||||
|
||||
Hardware requirements
|
||||
=====================
|
||||
- Micro USB cable
|
||||
- LPCXpresso55S69 board
|
||||
- Adafruit TFT LCD shield w/Cap Touch V2.3
|
||||
- Personal Computer
|
||||
|
||||
Board settings
|
||||
==============
|
||||
There are different versions of Adafruit 2.8" TFT LCD shields. The shields marked
|
||||
v2.0 works directly with this project. For the other shields, please solder
|
||||
the center pin of IOREF pads to the 3.3V pad, and solder the pads 11, 12, and 13.
|
||||
See the link for details:
|
||||
https://community.nxp.com/t5/MCUXpresso-Community-Articles/Modifying-the-latest-Adafruit-2-8-quot-LCD-for-SDK-graphics/ba-p/1131104
|
||||
|
||||
Attach the LCD shield to the LPC board.
|
||||
|
||||
Prepare the Demo
|
||||
================
|
||||
1. Power the board using a micro USB cable connected to P5 USB port on the board, attach debugger to P7 connector
|
||||
2. Build the project.
|
||||
3. Download the program to the target board.
|
||||
4. Reset the SoC and run the project.
|
||||
|
||||
Running the demo
|
||||
================
|
||||
Known issue: The MCU is not able to generate hardware reset of the LCD due to hardware limitation of the boards interconnection.
|
||||
Because of this the LCD may not get initialized (stays blank) following a cold start (power on) of the board even if the demo was
|
||||
correctly programmed to the FLASH memory. In such a case simply press the reset button to restart the demo.
|
||||
If user use Adafruit TFT LCD V2.8, please refer to this link: https://community.nxp.com/community/mcuxpresso/blog/2020/01/10/modifying-the-latest-adafruit-28-lcd-for-sdk-graphics-examples
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "custom.h"
|
||||
|
||||
/* User code. */
|
||||
void custom_init(lv_ui *ui)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _CUSTOM_H_
|
||||
#define _CUSTOM_H_
|
||||
|
||||
#include "gui_guider.h"
|
||||
|
||||
/* User code. */
|
||||
void custom_init(lv_ui *ui);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/*********************
|
||||
* INCLUDES
|
||||
*********************/
|
||||
#include <stdio.h>
|
||||
#include "lvgl/lvgl.h"
|
||||
#include "events_init.h"
|
||||
|
||||
/*********************
|
||||
* DEFINES
|
||||
*********************/
|
||||
|
||||
/**********************
|
||||
* TYPEDEFS
|
||||
**********************/
|
||||
|
||||
/**********************
|
||||
* STATIC PROTOTYPES
|
||||
**********************/
|
||||
|
||||
/**********************
|
||||
* STATIC VARIABLES
|
||||
**********************/
|
||||
|
||||
/**
|
||||
* Create a demo application
|
||||
*/
|
||||
|
||||
void events_init(lv_ui *ui)
|
||||
{
|
||||
/* Add your event callbacks here */
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef EVENTS_INIT_H_
|
||||
#define EVENTS_INIT_H_
|
||||
|
||||
#include "gui_guider.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void events_init(lv_ui *ui);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "lvgl/lvgl.h"
|
||||
#include "gui_guider.h"
|
||||
|
||||
void setup_ui(lv_ui *ui)
|
||||
{
|
||||
ui->btn = lv_btn_create(lv_scr_act());
|
||||
|
||||
ui->label = lv_label_create(ui->btn);
|
||||
lv_label_set_text(ui->label, "Button");
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef GUI_GUIDER_H
|
||||
#define GUI_GUIDER_H
|
||||
|
||||
#include "lvgl/lvgl.h"
|
||||
|
||||
typedef struct
|
||||
{
|
||||
lv_obj_t *btn;
|
||||
lv_obj_t *label;
|
||||
} lv_ui;
|
||||
|
||||
extern lv_ui guider_ui;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void setup_ui(lv_ui *ui);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef GUIDER_CUSTOMER_FONTS_H
|
||||
#define GUIDER_CUSTOMER_FONTS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef GUIDER_FONTS_H
|
||||
#define GUIDER_FONTS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* User imported image. */
|
||||
|
|
@ -36,7 +36,7 @@ List of boards with projects supporting flash remapping function:
|
|||
- MIMXRT1060-EVKB
|
||||
- MIMXRT1064-EVK
|
||||
- MIMXRT1170-EVK
|
||||
|
||||
- MIMXRT1170-EVKB
|
||||
|
||||
Signing the application image
|
||||
-----------------------------
|
||||
|
|
|
|||
|
|
@ -339,8 +339,8 @@ static status_t boot_swap_ok(int image)
|
|||
return status;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MCUBOOT_FLASH_REMAP_DOWNGRADE_SUPPORT)
|
||||
/* downgrade support for DIRECT-XIP, erase header of inactive slot */
|
||||
#if defined(CONFIG_MCUBOOT_FLASH_REMAP_DOWNGRADE_SUPPORT) && defined(CONFIG_MCUBOOT_FLASH_REMAP_ENABLE)
|
||||
/* downgrade support for DIRECT-XIP achieved by erasing header of inactive slot */
|
||||
/* because it can contains image with higher version */
|
||||
uint32_t off_header_erase;
|
||||
|
||||
|
|
@ -364,7 +364,7 @@ static status_t boot_swap_ok(int image)
|
|||
PRINTF("%s: failed to erase header of inactive image\r\n, __func__");
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_MCUBOOT_FLASH_REMAP_DOWNGRADE_SUPPORT && CONFIG_MCUBOOT_FLASH_REMAP_ENABLE */
|
||||
|
||||
return status;
|
||||
}
|
||||
|
|
|
|||
Binary file not shown.
|
Before Width: | Height: | Size: 34 KiB |
|
|
@ -1,129 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016, 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_i2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#if defined BOARD_USE_CODEC
|
||||
#include "fsl_wm8904.h"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if defined BOARD_USE_CODEC
|
||||
codec_config_t boardCodecConfig = {
|
||||
.I2C_SendFunc = BOARD_Codec_I2C_Send,
|
||||
.I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,
|
||||
.op = &wm8904_ops,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
void BOARD_InitDebugConsole_Core1(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM1 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
|
||||
uartClkSrcFreq);
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
i2c_master_config_t i2cConfig = {0};
|
||||
|
||||
I2C_MasterGetDefaultConfig(&i2cConfig);
|
||||
I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_I2C_Send(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
i2c_master_transfer_t masterXfer;
|
||||
|
||||
/* Prepare transfer structure. */
|
||||
masterXfer.slaveAddress = deviceAddress;
|
||||
masterXfer.direction = kI2C_Write;
|
||||
masterXfer.subaddress = subAddress;
|
||||
masterXfer.subaddressSize = subaddressSize;
|
||||
masterXfer.data = txBuff;
|
||||
masterXfer.dataSize = txBuffSize;
|
||||
masterXfer.flags = kI2C_TransferDefaultFlag;
|
||||
|
||||
return I2C_MasterTransferBlocking(base, &masterXfer);
|
||||
}
|
||||
|
||||
status_t BOARD_I2C_Receive(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
i2c_master_transfer_t masterXfer;
|
||||
|
||||
/* Prepare transfer structure. */
|
||||
masterXfer.slaveAddress = deviceAddress;
|
||||
masterXfer.subaddress = subAddress;
|
||||
masterXfer.subaddressSize = subaddressSize;
|
||||
masterXfer.data = rxBuff;
|
||||
masterXfer.dataSize = rxBuffSize;
|
||||
masterXfer.direction = kI2C_Read;
|
||||
masterXfer.flags = kI2C_TransferDefaultFlag;
|
||||
|
||||
return I2C_MasterTransferBlocking(base, &masterXfer);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
|
@ -1,233 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_reset.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iocon.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "LPCXpresso5500"
|
||||
|
||||
/*! @brief The UART to use for debug messages. */
|
||||
/* TODO: rename UART to USART */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
|
||||
#define BOARD_DEBUG_UART_INSTANCE 0U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
|
||||
#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
|
||||
#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
|
||||
#define BOARD_UART_IRQ FLEXCOMM0_IRQn
|
||||
|
||||
#define BOARD_ACCEL_I2C_BASEADDR I2C4
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
|
||||
|
||||
#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
|
||||
#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1
|
||||
#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler
|
||||
#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
|
||||
#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR I2C4
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
|
||||
|
||||
#ifndef BOARD_LED_RED_GPIO
|
||||
#define BOARD_LED_RED_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_LED_RED_GPIO_PORT 1U
|
||||
#ifndef BOARD_LED_RED_GPIO_PIN
|
||||
#define BOARD_LED_RED_GPIO_PIN 6U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_BLUE_GPIO
|
||||
#define BOARD_LED_BLUE_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_LED_BLUE_GPIO_PORT 1U
|
||||
#ifndef BOARD_LED_BLUE_GPIO_PIN
|
||||
#define BOARD_LED_BLUE_GPIO_PIN 4U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_GREEN_GPIO
|
||||
#define BOARD_LED_GREEN_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_LED_GREEN_GPIO_PORT 1U
|
||||
#ifndef BOARD_LED_GREEN_GPIO_PIN
|
||||
#define BOARD_LED_GREEN_GPIO_PIN 7U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_SW1_GPIO
|
||||
#define BOARD_SW1_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_SW1_GPIO_PORT 0U
|
||||
#ifndef BOARD_SW1_GPIO_PIN
|
||||
#define BOARD_SW1_GPIO_PIN 5U
|
||||
#endif
|
||||
#define BOARD_SW1_NAME "SW1"
|
||||
#define BOARD_SW1_IRQ PIN_INT0_IRQn
|
||||
#define BOARD_SW1_IRQ_HANDLER PIN_INT0_IRQHandler
|
||||
|
||||
#ifndef BOARD_SW2_GPIO
|
||||
#define BOARD_SW2_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_SW2_GPIO_PORT 1U
|
||||
#ifndef BOARD_SW2_GPIO_PIN
|
||||
#define BOARD_SW2_GPIO_PIN 18U
|
||||
#endif
|
||||
#define BOARD_SW2_NAME "SW2"
|
||||
#define BOARD_SW2_IRQ PIN_INT1_IRQn
|
||||
#define BOARD_SW2_IRQ_HANDLER PIN_INT1_IRQHandler
|
||||
#define BOARD_SW2_GPIO_PININT_INDEX 1
|
||||
|
||||
#ifndef BOARD_SW3_GPIO
|
||||
#define BOARD_SW3_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_SW3_GPIO_PORT 1U
|
||||
#ifndef BOARD_SW3_GPIO_PIN
|
||||
#define BOARD_SW3_GPIO_PIN 9U
|
||||
#endif
|
||||
#define BOARD_SW3_NAME "SW3"
|
||||
#define BOARD_SW3_IRQ PIN_INT1_IRQn
|
||||
#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler
|
||||
#define BOARD_SW3_GPIO_PININT_INDEX 1
|
||||
|
||||
#define BOARD_SDIF_BASEADDR SDIF
|
||||
#define BOARD_SDIF_CLKSRC kCLOCK_SDio
|
||||
#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio)
|
||||
#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
|
||||
#define BOARD_SDIF_IRQ SDIO_IRQn
|
||||
#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
|
||||
#define BOARD_SD_CARD_DETECT_PIN 17
|
||||
#define BOARD_SD_CARD_DETECT_PORT 0
|
||||
#define BOARD_SD_CARD_DETECT_GPIO GPIO
|
||||
#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
|
||||
|
||||
#define BOARD_SDIF_CD_GPIO_INIT() \
|
||||
{ \
|
||||
CLOCK_EnableClock(kCLOCK_Gpio2); \
|
||||
GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \
|
||||
}
|
||||
#define BOARD_SDIF_CD_STATUS() \
|
||||
GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
|
||||
|
||||
/* Board led color mapping */
|
||||
#define LOGIC_LED_ON 0U
|
||||
#define LOGIC_LED_OFF 1U
|
||||
|
||||
#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
|
||||
|
||||
#define LED_RED_INIT(output) \
|
||||
{ \
|
||||
IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
|
||||
(IOCON_PIO_FUNC0 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | \
|
||||
IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI)); \
|
||||
GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
|
||||
}
|
||||
#define LED_RED_ON() \
|
||||
GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
|
||||
1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 */
|
||||
#define LED_RED_OFF() \
|
||||
GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
|
||||
1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 \ \ \ \ \ \ \ \ \ \ \
|
||||
*/
|
||||
#define LED_RED_TOGGLE() \
|
||||
GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
|
||||
1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
|
||||
|
||||
#define LED_BLUE_INIT(output) \
|
||||
{ \
|
||||
IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
|
||||
(IOCON_PIO_FUNC0 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | \
|
||||
IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI)); \
|
||||
GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
|
||||
}
|
||||
#define LED_BLUE_ON() \
|
||||
GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
|
||||
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
|
||||
#define LED_BLUE_OFF() \
|
||||
GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
|
||||
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
|
||||
#define LED_BLUE_TOGGLE() \
|
||||
GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
|
||||
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
|
||||
|
||||
#define LED_GREEN_INIT(output) \
|
||||
GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
|
||||
#define LED_GREEN_ON() \
|
||||
GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
|
||||
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
|
||||
#define LED_GREEN_OFF() \
|
||||
GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
|
||||
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
|
||||
#define LED_GREEN_TOGGLE() \
|
||||
GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
|
||||
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_InitDebugConsole_Core1(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_I2C_Send(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_I2C_Receive(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
@ -1,375 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to set up clock using clock driver functions:
|
||||
*
|
||||
* 1. Setup clock sources.
|
||||
*
|
||||
* 2. Set up wait states of the flash.
|
||||
*
|
||||
* 3. Set up all dividers.
|
||||
*
|
||||
* 4. Set up all selectors to provide selected clocks.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v7.0
|
||||
processor: LPC55S69
|
||||
package_id: LPC55S69JBD100
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.7.2
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockFROHF96M();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFRO12M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 12 MHz}
|
||||
settings:
|
||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
||||
sources:
|
||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFRO12M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
||||
|
||||
POWER_SetVoltageForFreq(
|
||||
12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFROHF96M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 96 MHz}
|
||||
settings:
|
||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
||||
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
|
||||
sources:
|
||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFROHF96M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFROHF96M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFROHF96M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
||||
|
||||
POWER_SetVoltageForFreq(
|
||||
96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL100M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 100 MHz}
|
||||
settings:
|
||||
- {id: PLL0_Mode, value: Normal}
|
||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
|
||||
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
||||
- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
|
||||
- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
|
||||
- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
|
||||
sources:
|
||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL100M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
||||
|
||||
/*!< Configure XTAL32M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
||||
|
||||
POWER_SetVoltageForFreq(
|
||||
100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up PLL */
|
||||
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
|
||||
const pll_setup_t pll0Setup = {
|
||||
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
|
||||
.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
|
||||
.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
|
||||
.pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
|
||||
.pllRate = 100000000U,
|
||||
.flags = PLL_SETUPFLAG_WAITLOCK};
|
||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL150M
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 150 MHz}
|
||||
settings:
|
||||
- {id: PLL0_Mode, value: Normal}
|
||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
|
||||
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
||||
- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
|
||||
- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
|
||||
- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
|
||||
sources:
|
||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL150M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
/*!< Configure XTAL32M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
||||
|
||||
POWER_SetVoltageForFreq(
|
||||
150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up PLL */
|
||||
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
|
||||
const pll_setup_t pll0Setup = {
|
||||
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
|
||||
.pllndec = SYSCON_PLL0NDEC_NDIV(8U),
|
||||
.pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
|
||||
.pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
|
||||
.pllRate = 150000000U,
|
||||
.flags = PLL_SETUPFLAG_WAITLOCK};
|
||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockPLL1_150M ********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL1_150M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 150 MHz}
|
||||
settings:
|
||||
- {id: PLL1_Mode, value: Normal}
|
||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
|
||||
- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
||||
- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
|
||||
- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
|
||||
- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
|
||||
sources:
|
||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL1_150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL1_150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL1_150M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
/*!< Configure XTAL32M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
||||
|
||||
POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up PLL1 */
|
||||
CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
|
||||
const pll_setup_t pll1Setup = {
|
||||
.pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
|
||||
.pllndec = SYSCON_PLL1NDEC_NDIV(8U),
|
||||
.pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
|
||||
.pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
|
||||
.pllRate = 150000000U,
|
||||
.flags = PLL_SETUPFLAG_WAITLOCK
|
||||
};
|
||||
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -1,167 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO12M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF96M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF96M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF96M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL100M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL150M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockPLL1_150M ********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL1_150M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL1_150M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL1_150M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Peripherals v8.0
|
||||
processor: LPC55S69
|
||||
package_id: LPC55S69JBD100
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.9.7
|
||||
board: LPCXpresso55S69
|
||||
functionalGroups:
|
||||
- name: BOARD_InitPeripherals_cm33_core0
|
||||
UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1
|
||||
called_from_default_init: true
|
||||
selectedCore: cm33_core0
|
||||
- name: BOARD_InitPeripherals_cm33_core1
|
||||
UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48
|
||||
selectedCore: cm33_core1
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
component:
|
||||
- type: 'system'
|
||||
- type_id: 'system'
|
||||
- global_system_definitions:
|
||||
- user_definitions: ''
|
||||
- user_includes: ''
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Included files
|
||||
**********************************************************************************************************************/
|
||||
#include "peripherals.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* BOARD_InitPeripherals_cm33_core0 functional group
|
||||
**********************************************************************************************************************/
|
||||
/***********************************************************************************************************************
|
||||
* NVIC initialization code
|
||||
**********************************************************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
instance:
|
||||
- name: 'NVIC'
|
||||
- type: 'nvic'
|
||||
- mode: 'general'
|
||||
- custom_name_enabled: 'false'
|
||||
- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
|
||||
- functional_group: 'BOARD_InitPeripherals_cm33_core0'
|
||||
- peripheral: 'NVIC'
|
||||
- config_sets:
|
||||
- nvic:
|
||||
- interrupt_table: []
|
||||
- interrupts: []
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/* Empty initialization function (commented out)
|
||||
static void NVIC_init(void) {
|
||||
} */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Initialization functions
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitPeripherals_cm33_core0(void)
|
||||
{
|
||||
/* Initialize components */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void)
|
||||
{
|
||||
BOARD_InitPeripherals_cm33_core0();
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PERIPHERALS_H_
|
||||
#define _PERIPHERALS_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Included files
|
||||
**********************************************************************************************************************/
|
||||
#include "fsl_common.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Initialization functions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
void BOARD_InitPeripherals_cm33_core0(void);
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
**********************************************************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PERIPHERALS_H_ */
|
||||
|
|
@ -1,826 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v8.0
|
||||
processor: LPC55S69
|
||||
package_id: LPC55S69JBD100
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.9.7
|
||||
board: LPCXpresso55S69
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iocon.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitDEBUG_UARTPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitDEBUG_UARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
|
||||
mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitDEBUG_UARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitDEBUG_UARTPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX);
|
||||
|
||||
const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitSWD_DEBUGPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
|
||||
- {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
|
||||
- {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO,
|
||||
mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitSWD_DEBUGPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitSWD_DEBUGPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is open (disabled) */
|
||||
IOCON_PIO_ASW_DI);
|
||||
/* PORT0 PIN10 (coords: 21) is configured as SWO */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO);
|
||||
|
||||
if (Chip_GetVersion()==1)
|
||||
{
|
||||
const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* Selects pull-down function */
|
||||
IOCON_PIO_MODE_PULLDOWN |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled) */
|
||||
IOCON_PIO_ASW_EN);
|
||||
/* PORT0 PIN11 (coords: 13) is configured as SWCLK */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
|
||||
}
|
||||
else
|
||||
{
|
||||
const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* Selects pull-down function */
|
||||
IOCON_PIO_MODE_PULLDOWN |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled), only for A0 version */
|
||||
IOCON_PIO_ASW_DIS_EN);
|
||||
/* PORT0 PIN11 (coords: 13) is configured as SWCLK */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
|
||||
}
|
||||
|
||||
if (Chip_GetVersion()==1)
|
||||
{
|
||||
const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled) */
|
||||
IOCON_PIO_ASW_EN);
|
||||
/* PORT0 PIN12 (coords: 12) is configured as SWDIO */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
|
||||
}
|
||||
else
|
||||
{
|
||||
const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
|
||||
IOCON_PIO_FUNC6 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled), only for A0 version */
|
||||
IOCON_PIO_ASW_DIS_EN);
|
||||
/* PORT0 PIN12 (coords: 12) is configured as SWDIO */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
|
||||
}
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitUSBPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP}
|
||||
- {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM}
|
||||
- {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22,
|
||||
mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
|
||||
- {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
|
||||
- {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
|
||||
- {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitUSBPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitUSBPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */
|
||||
IOCON_PIO_FUNC7 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS);
|
||||
|
||||
const uint32_t port0_pin28_config = (/* Pin is configured as USB0_OVERCURRENTN */
|
||||
IOCON_PIO_FUNC7 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN28 (coords: 66) is configured as USB0_OVERCURRENTN */
|
||||
IOCON_PinMuxSet(IOCON, 0U, 28U, port0_pin28_config);
|
||||
|
||||
const uint32_t port1_pin12_config = (/* Pin is configured as USB0_PORTPWRN */
|
||||
IOCON_PIO_FUNC4 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN12 (coords: 67) is configured as USB0_PORTPWRN */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config);
|
||||
|
||||
const uint32_t port1_pin29_config = (/* Pin is configured as USB1_PORTPWRN */
|
||||
IOCON_PIO_FUNC4 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN29 (coords: 80) is configured as USB1_PORTPWRN */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 29U, port1_pin29_config);
|
||||
|
||||
const uint32_t port1_pin30_config = (/* Pin is configured as USB1_OVERCURRENTN */
|
||||
IOCON_PIO_FUNC4 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN30 (coords: 65) is configured as USB1_OVERCURRENTN */
|
||||
IOCON_PinMuxSet(IOCON, 1U, 30U, port1_pin30_config);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitLEDsPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true',
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true',
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true',
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitLEDsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitLEDsPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
/* Enables the clock for the GPIO1 module */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio1);
|
||||
|
||||
gpio_pin_config_t LED_BULE_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_4 (pin 1) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_BULE_GPIO, BOARD_INITLEDSPINS_LED_BULE_PORT, BOARD_INITLEDSPINS_LED_BULE_PIN, &LED_BULE_config);
|
||||
|
||||
gpio_pin_config_t LED_RED_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_6 (pin 5) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
|
||||
|
||||
gpio_pin_config_t LED_GREEN_config = {
|
||||
.pinDirection = kGPIO_DigitalOutput,
|
||||
.outputLogic = 1U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_7 (pin 9) */
|
||||
GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
|
||||
|
||||
const uint32_t LED_BULE = (/* Pin is configured as PIO1_4 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BULE_PORT, BOARD_INITLEDSPINS_LED_BULE_PIN, LED_BULE);
|
||||
|
||||
const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED);
|
||||
|
||||
const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitBUTTONsPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled, asw: enabled}
|
||||
- {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBUTTONsPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitBUTTONsPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
/* Enables the clock for the GPIO0 module */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
||||
|
||||
/* Enables the clock for the GPIO1 module */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio1);
|
||||
|
||||
gpio_pin_config_t S1_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO0_5 (pin 88) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config);
|
||||
|
||||
gpio_pin_config_t S3_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_9 (pin 10) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config);
|
||||
|
||||
gpio_pin_config_t S2_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_18 (pin 64) */
|
||||
GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config);
|
||||
|
||||
const uint32_t S1 = (/* Pin is configured as PIO0_5 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1);
|
||||
|
||||
const uint32_t S2 = (/* Pin is configured as PIO1_18 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2);
|
||||
|
||||
if (Chip_GetVersion()==1)
|
||||
{
|
||||
const uint32_t S3 = (/* Pin is configured as PIO1_9 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled) */
|
||||
IOCON_PIO_ASW_EN);
|
||||
/* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3);
|
||||
}
|
||||
else
|
||||
{
|
||||
const uint32_t S3 = (/* Pin is configured as PIO1_9 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled), only for A0 version */
|
||||
IOCON_PIO_ASW_DIS_EN);
|
||||
/* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3);
|
||||
}
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitI2SPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled,
|
||||
open_drain: disabled}
|
||||
- {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1,
|
||||
identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
|
||||
- {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N,
|
||||
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitI2SPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitI2SPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is closed (enabled) */
|
||||
IOCON_PIO_ASW_EN);
|
||||
/* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK);
|
||||
|
||||
const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC7 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS);
|
||||
|
||||
const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC7 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX);
|
||||
|
||||
const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */
|
||||
IOCON_PIO_FUNC7 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK);
|
||||
|
||||
const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC2 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX);
|
||||
|
||||
const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC2 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS);
|
||||
|
||||
const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
|
||||
|
||||
const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
|
||||
|
||||
const uint32_t MCLK = (/* Pin is configured as MCLK */
|
||||
IOCON_PIO_FUNC1 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN31 (coords: 91) is configured as MCLK */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitACCELPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
|
||||
invert: disabled, open_drain: disabled}
|
||||
- {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive,
|
||||
slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitACCELPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
/* Function assigned for the Cortex-M33 (Core #0) */
|
||||
void BOARD_InitACCELPins(void)
|
||||
{
|
||||
/* Enables the clock for the I/O controller.: Enable Clock. */
|
||||
CLOCK_EnableClock(kCLOCK_Iocon);
|
||||
|
||||
/* Enables the clock for the GPIO1 module */
|
||||
CLOCK_EnableClock(kCLOCK_Gpio1);
|
||||
|
||||
gpio_pin_config_t ACCL_INTR_config = {
|
||||
.pinDirection = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U
|
||||
};
|
||||
/* Initialize GPIO functionality on pin PIO1_19 (pin 58) */
|
||||
GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config);
|
||||
|
||||
const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */
|
||||
IOCON_PIO_FUNC0 |
|
||||
/* No addition pin function */
|
||||
IOCON_PIO_MODE_INACT |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI |
|
||||
/* Analog switch is open (disabled) */
|
||||
IOCON_PIO_ASW_DI);
|
||||
/* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR);
|
||||
|
||||
const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
|
||||
|
||||
const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PIO_FUNC5 |
|
||||
/* Selects pull-up function */
|
||||
IOCON_PIO_MODE_PULLUP |
|
||||
/* Standard mode, output slew rate control is enabled */
|
||||
IOCON_PIO_SLEW_STANDARD |
|
||||
/* Input function is not inverted */
|
||||
IOCON_PIO_INV_DI |
|
||||
/* Enables digital function */
|
||||
IOCON_PIO_DIGITAL_EN |
|
||||
/* Open drain is disabled */
|
||||
IOCON_PIO_OPENDRAIN_DI);
|
||||
/* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
|
||||
IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -1,819 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PERIPHERAL FLEXCOMM0
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_SIGNAL RXD_SDA_MOSI_DATA
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_NAME FC0_RXD_SDA_MOSI_DATA
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_LABEL "P8[2]/U6[13]/FC0_USART_RXD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_NAME "DEBUG_UART_RX"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PERIPHERAL FLEXCOMM0
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_SIGNAL TXD_SCL_MISO_WS
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_NAME FC0_TXD_SCL_MISO_WS
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_LABEL "P8[3]/U6[12]/FC0_USART_TXD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_NAME "DEBUG_UART_TX"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U)
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */
|
||||
#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */
|
||||
#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PERIPHERAL SWD
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_SIGNAL SWCLK
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_NAME SWCLK
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_LABEL "U14[4]/SWDCLK_TRGT"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_NAME "DEBUG_SWD_SWDCLK"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PERIPHERAL SWD
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_SIGNAL SWDIO
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_NAME SWDIO
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_LABEL "U15[4]/D7/P7[2]/IF_SWDIO"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_NAME "DEBUG_SWD_SWDIO"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PERIPHERAL SWD
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_SIGNAL SWO
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_NAME SWO
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_LABEL "U14[12]/SWO_TRGT"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_NAME "DEBUG_SWD_SWO"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U)
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC4 0x04u /*!<@brief Selects pin function 4 */
|
||||
#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name USB0_DP (number 97), P10[3]/D10[3]/USB0_FS_P
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSBPINS_USB0_DP_PERIPHERAL USBFSH /*!<@brief Peripheral name */
|
||||
#define BOARD_INITUSBPINS_USB0_DP_SIGNAL USB_DP /*!<@brief Signal name */
|
||||
#define BOARD_INITUSBPINS_USB0_DP_PIN_NAME USB0_DP /*!<@brief Routed pin name */
|
||||
#define BOARD_INITUSBPINS_USB0_DP_LABEL "P10[3]/D10[3]/USB0_FS_P" /*!<@brief Label */
|
||||
#define BOARD_INITUSBPINS_USB0_DP_NAME "USB0_DP" /*!<@brief Identifier */
|
||||
/* @} */
|
||||
|
||||
/*! @name USB0_DM (number 98), P10[2]/D10[2]/USB0_FS_N
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSBPINS_USB0_DM_PERIPHERAL USBFSH /*!<@brief Peripheral name */
|
||||
#define BOARD_INITUSBPINS_USB0_DM_SIGNAL USB_DM /*!<@brief Signal name */
|
||||
#define BOARD_INITUSBPINS_USB0_DM_PIN_NAME USB0_DM /*!<@brief Routed pin name */
|
||||
#define BOARD_INITUSBPINS_USB0_DM_LABEL "P10[2]/D10[2]/USB0_FS_N" /*!<@brief Label */
|
||||
#define BOARD_INITUSBPINS_USB0_DM_NAME "USB0_DM" /*!<@brief Identifier */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_PERIPHERAL USBFSH /*!<@brief Peripheral name */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_SIGNAL USB_VBUS /*!<@brief Signal name */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_PIN_NAME USB0_VBUS /*!<@brief Routed pin name */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_LABEL "P10[1]/USB0_VBUS" /*!<@brief Label */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_NAME "USB0_VBUS" /*!<@brief Identifier */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name USB1_DM (number 35), P9[2]/D9[2]/USB1_HS_N
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSBPINS_USB1_DM_PERIPHERAL USBHSH /*!<@brief Peripheral name */
|
||||
#define BOARD_INITUSBPINS_USB1_DM_SIGNAL USB_DM /*!<@brief Signal name */
|
||||
#define BOARD_INITUSBPINS_USB1_DM_PIN_NAME USB1_DM /*!<@brief Routed pin name */
|
||||
#define BOARD_INITUSBPINS_USB1_DM_LABEL "P9[2]/D9[2]/USB1_HS_N" /*!<@brief Label */
|
||||
#define BOARD_INITUSBPINS_USB1_DM_NAME "USB1_DM" /*!<@brief Identifier */
|
||||
/* @} */
|
||||
|
||||
/*! @name USB1_DP (number 34), P9[3]/D9[3]/USB1_HS_P
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSBPINS_USB1_DP_PERIPHERAL USBHSH /*!<@brief Peripheral name */
|
||||
#define BOARD_INITUSBPINS_USB1_DP_SIGNAL USB_DP /*!<@brief Signal name */
|
||||
#define BOARD_INITUSBPINS_USB1_DP_PIN_NAME USB1_DP /*!<@brief Routed pin name */
|
||||
#define BOARD_INITUSBPINS_USB1_DP_LABEL "P9[3]/D9[3]/USB1_HS_P" /*!<@brief Label */
|
||||
#define BOARD_INITUSBPINS_USB1_DP_NAME "USB1_DP" /*!<@brief Identifier */
|
||||
/* @} */
|
||||
|
||||
/*! @name USB1_VBUS (number 36), P9[1]/USB1_VBUS
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITUSBPINS_USB1_VBUS_PERIPHERAL USBHSH /*!<@brief Peripheral name */
|
||||
#define BOARD_INITUSBPINS_USB1_VBUS_SIGNAL USB_VBUS /*!<@brief Signal name */
|
||||
#define BOARD_INITUSBPINS_USB1_VBUS_PIN_NAME USB1_VBUS /*!<@brief Routed pin name */
|
||||
#define BOARD_INITUSBPINS_USB1_VBUS_LABEL "P9[1]/USB1_VBUS" /*!<@brief Label */
|
||||
#define BOARD_INITUSBPINS_USB1_VBUS_NAME "USB1_VBUS" /*!<@brief Identifier */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_SIGNAL PIO1 /*!<@brief Signal name */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_CHANNEL 4 /*!<@brief Signal channel */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_PIN_NAME PIO1_4 /*!<@brief Routed pin name */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_LABEL "R78/P18[5]/LEDR/PWM_ARD" /*!<@brief Label */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_NAME "LED_BULE" /*!<@brief Identifier */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_GPIO_PIN 4U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_PIN 4U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_BULE_PIN_MASK (1U << 4U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_SIGNAL PIO1 /*!<@brief Signal name */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_CHANNEL 6 /*!<@brief Signal channel */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN_NAME PIO1_6 /*!<@brief Routed pin name */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_LABEL "R80/P18[9]/LEDB/PWM_ARD" /*!<@brief Label */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_NAME "LED_RED" /*!<@brief Identifier */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 6U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN 6U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PERIPHERAL GPIO
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_SIGNAL PIO1
|
||||
/*!
|
||||
* @brief Signal channel */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_CHANNEL 7
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN_NAME PIO1_7
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_LABEL "R79/P18[7]/LEDG/PWM_ARD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_NAME "LED_GREEN"
|
||||
/*!
|
||||
* @brief Direction */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
/*!
|
||||
* @brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO
|
||||
/*!
|
||||
* @brief GPIO pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 7U
|
||||
/*!
|
||||
* @brief GPIO pin mask */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U)
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U)
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */
|
||||
#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITBUTTONSPINS_S1_PERIPHERAL GPIO
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITBUTTONSPINS_S1_SIGNAL PIO0
|
||||
/*!
|
||||
* @brief Signal channel */
|
||||
#define BOARD_INITBUTTONSPINS_S1_CHANNEL 5
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITBUTTONSPINS_S1_PIN_NAME PIO0_5
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITBUTTONSPINS_S1_LABEL "S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITBUTTONSPINS_S1_NAME "S1"
|
||||
/*!
|
||||
* @brief Direction */
|
||||
#define BOARD_INITBUTTONSPINS_S1_DIRECTION kPIN_MUX_DirectionInput
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
/*!
|
||||
* @brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO
|
||||
/*!
|
||||
* @brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN 5U
|
||||
/*!
|
||||
* @brief GPIO pin mask */
|
||||
#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U)
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_S1_PORT 0U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_S1_PIN 5U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITBUTTONSPINS_S2_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITBUTTONSPINS_S2_SIGNAL PIO1 /*!<@brief Signal name */
|
||||
#define BOARD_INITBUTTONSPINS_S2_CHANNEL 18 /*!<@brief Signal channel */
|
||||
#define BOARD_INITBUTTONSPINS_S2_PIN_NAME PIO1_18 /*!<@brief Routed pin name */
|
||||
#define BOARD_INITBUTTONSPINS_S2_LABEL "S2/P18[16]/P24[2]/WAKE/GPIO" /*!<@brief Label */
|
||||
#define BOARD_INITBUTTONSPINS_S2_NAME "S2" /*!<@brief Identifier */
|
||||
#define BOARD_INITBUTTONSPINS_S2_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN 18U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */
|
||||
#define BOARD_INITBUTTONSPINS_S2_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_S2_PIN 18U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITBUTTONSPINS_S3_PERIPHERAL GPIO /*!<@brief Peripheral name */
|
||||
#define BOARD_INITBUTTONSPINS_S3_SIGNAL PIO1 /*!<@brief Signal name */
|
||||
#define BOARD_INITBUTTONSPINS_S3_CHANNEL 9 /*!<@brief Signal channel */
|
||||
#define BOARD_INITBUTTONSPINS_S3_PIN_NAME PIO1_9 /*!<@brief Routed pin name */
|
||||
#define BOARD_INITBUTTONSPINS_S3_LABEL "S3/P18[1]/PIO1_9_GPIO_ARD" /*!<@brief Label */
|
||||
#define BOARD_INITBUTTONSPINS_S3_NAME "S3" /*!<@brief Identifier */
|
||||
#define BOARD_INITBUTTONSPINS_S3_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN 9U /*!<@brief GPIO pin number */
|
||||
#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */
|
||||
#define BOARD_INITBUTTONSPINS_S3_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITBUTTONSPINS_S3_PIN 9U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name RESETN (number 32), S4/P16[10]/P23[2]/U14[8]/RESETN
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITBUTTONSPINS_S4_PERIPHERAL SYSCON
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITBUTTONSPINS_S4_SIGNAL RESET
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITBUTTONSPINS_S4_PIN_NAME RESETN
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITBUTTONSPINS_S4_LABEL "S4/P16[10]/P23[2]/U14[8]/RESETN"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITBUTTONSPINS_S4_NAME "S4"
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
|
||||
#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */
|
||||
#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */
|
||||
#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_PERIPHERAL FLEXCOMM4
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_SIGNAL TXD_SCL_MISO_WS
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_NAME FC4_TXD_SCL_MISO_WS
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_LABEL "P17[1]/P24[5]/FC4_I2C_SCL_ARD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_NAME "FC4_I2C_SCL"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_PERIPHERAL FLEXCOMM4
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_SIGNAL RXD_SDA_MOSI_DATA
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_NAME FC4_RXD_SDA_MOSI_DATA
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_LABEL "P17[3]/P24[6]/FC4_I2C_SDA_ARD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_NAME "FC4_I2C_SDA"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_MCLK_PERIPHERAL SYSCON /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_MCLK_SIGNAL MCLK /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_MCLK_PIN_NAME MCLK /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_MCLK_LABEL "P19[7]/P19[8]/PLU_IN0/GPIO" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_MCLK_NAME "MCLK" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_PERIPHERAL FLEXCOMM7 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_SIGNAL SCK /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_NAME FC7_SCK /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_LABEL "P17[14]/FC7_I2S_SCK" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_NAME "FC7_I2S_SCK" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_PERIPHERAL FLEXCOMM7 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_SIGNAL RXD_SDA_MOSI_DATA /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_NAME FC7_RXD_SDA_MOSI_DATA /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_LABEL "P17[10]/FC7_I2S_TX" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_NAME "FC7_I2S_TX" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_PERIPHERAL FLEXCOMM7 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_SIGNAL TXD_SCL_MISO_WS /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_NAME FC7_TXD_SCL_MISO_WS /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_LABEL "P17[12]/FC7_I2S_WS" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_NAME "FC7_I2S_WS" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_PERIPHERAL FLEXCOMM6 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_SIGNAL SCK /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_NAME FC6_SCK /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_LABEL "U14[12]/SWO_TRGT" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_NAME "FC6_I2S_CLK" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_PERIPHERAL FLEXCOMM6 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_SIGNAL RXD_SDA_MOSI_DATA /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_NAME FC6_RXD_SDA_MOSI_DATA /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_LABEL "P17[20]/FC6_I2S_RX" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_NAME "FC6_I2S_RX" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_PERIPHERAL FLEXCOMM6 /*!<@brief Peripheral name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_SIGNAL TXD_SCL_MISO_WS /*!<@brief Signal name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_NAME FC6_TXD_SCL_MISO_WS /*!<@brief Routed pin name */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_LABEL "P18[17]/SD1_PWR_EN" /*!<@brief Label */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_NAME "FC6_I2S_WS" /*!<@brief Identifier */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */
|
||||
#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */
|
||||
#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
|
||||
#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
|
||||
#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */
|
||||
#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */
|
||||
#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
|
||||
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
|
||||
#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
|
||||
#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
|
||||
|
||||
/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_PERIPHERAL FLEXCOMM4
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_SIGNAL RXD_SDA_MOSI_DATA
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_NAME FC4_RXD_SDA_MOSI_DATA
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_LABEL "P17[3]/P24[6]/FC4_I2C_SDA_ARD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_NAME "FC4_I2C_SDA"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_PERIPHERAL FLEXCOMM4
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_SIGNAL TXD_SCL_MISO_WS
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_NAME FC4_TXD_SCL_MISO_WS
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_LABEL "P17[1]/P24[5]/FC4_I2C_SCL_ARD"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_NAME "FC4_I2C_SCL"
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)
|
||||
/* @} */
|
||||
|
||||
/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO
|
||||
@{ */
|
||||
/* Routed pin properties */
|
||||
/*!
|
||||
* @brief Peripheral name */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_PERIPHERAL GPIO
|
||||
/*!
|
||||
* @brief Signal name */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_SIGNAL PIO1
|
||||
/*!
|
||||
* @brief Signal channel */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_CHANNEL 19
|
||||
/*!
|
||||
* @brief Routed pin name */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_PIN_NAME PIO1_19
|
||||
/*!
|
||||
* @brief Label */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_LABEL "U7[3]/P18[14]/PLU_OUT1/GPIO"
|
||||
/*!
|
||||
* @brief Identifier */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_NAME "ACCL_INTR"
|
||||
/*!
|
||||
* @brief Direction */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_DIRECTION kPIN_MUX_DirectionInput
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
/*!
|
||||
* @brief GPIO peripheral base pointer */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO
|
||||
/*!
|
||||
* @brief GPIO pin number */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN 19U
|
||||
/*!
|
||||
* @brief GPIO pin mask */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U)
|
||||
/*!
|
||||
* @brief PORT peripheral base pointer */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U
|
||||
/*!
|
||||
* @brief PORT pin number */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U
|
||||
/*!
|
||||
* @brief PORT pin mask */
|
||||
#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U)
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
|
||||
<VIF_Specification>3.17</VIF_Specification>
|
||||
<VIF_App>
|
||||
<Vendor>Ellisys</Vendor>
|
||||
<Name>Ellisys USB Explorer 350 Examiner</Name>
|
||||
<Version>3.1.8098.23433</Version>
|
||||
</VIF_App>
|
||||
<Vendor_Name>NXP</Vendor_Name>
|
||||
<Model_Part_Number></Model_Part_Number>
|
||||
<Product_Revision></Product_Revision>
|
||||
<TID></TID>
|
||||
<VIF_Product_Type value="0">Port</VIF_Product_Type>
|
||||
<Certification_Type value="0">End Product</Certification_Type>
|
||||
<Product />
|
||||
<Component>
|
||||
<Port_Label></Port_Label>
|
||||
<Connector_Type value="2">Type-C</Connector_Type>
|
||||
<USB4_Supported value="false" />
|
||||
<USB_PD_Support value="true" />
|
||||
<PD_Port_Type value="1">Consumer / Provider</PD_Port_Type>
|
||||
<Type_C_State_Machine value="1">Sink</Type_C_State_Machine>
|
||||
<Port_Battery_Powered value="false" />
|
||||
<BC_1_2_Support value="0">None</BC_1_2_Support>
|
||||
<PD_Spec_Revision_Major value="3" />
|
||||
<PD_Spec_Revision_Minor value="0" />
|
||||
<PD_Spec_Version_Major value="2" />
|
||||
<PD_Spec_Version_Minor value="0" />
|
||||
<PD_Specification_Revision value="2">v3.0</PD_Specification_Revision>
|
||||
<SOP_Capable value="true" />
|
||||
<SOP_P_Capable value="false" />
|
||||
<SOP_PP_Capable value="false" />
|
||||
<SOP_P_Debug_Capable value="false" />
|
||||
<SOP_PP_Debug_Capable value="false" />
|
||||
<Manufacturer_Info_Supported_Port value="true" />
|
||||
<Manufacturer_Info_VID_Port value="8137">0x1FC9</Manufacturer_Info_VID_Port>
|
||||
<Manufacturer_Info_PID_Port value="256">0x0100</Manufacturer_Info_PID_Port>
|
||||
<USB_Comms_Capable value="false" />
|
||||
<DR_Swap_To_DFP_Supported value="true" />
|
||||
<DR_Swap_To_UFP_Supported value="true" />
|
||||
<Unconstrained_Power value="true" />
|
||||
<VCONN_Swap_To_On_Supported value="true" />
|
||||
<VCONN_Swap_To_Off_Supported value="true" />
|
||||
<Responds_To_Discov_SOP_UFP value="true" />
|
||||
<Responds_To_Discov_SOP_DFP value="true" />
|
||||
<Attempts_Discov_SOP value="false" />
|
||||
<Power_Interruption_Available value="0">No Interruption Possible</Power_Interruption_Available>
|
||||
<Chunking_Implemented_SOP value="true" />
|
||||
<Data_Reset_Supported value="false" />
|
||||
<Enter_USB_Supported value="false" />
|
||||
<Unchunked_Extended_Messages_Supported value="true" />
|
||||
<Security_Msgs_Supported_SOP value="false" />
|
||||
<Num_Fixed_Batteries value="0" />
|
||||
<Num_Swappable_Battery_Slots value="0" />
|
||||
<ID_Header_Connector_Type_SOP value="2">USB Type-C Receptacle</ID_Header_Connector_Type_SOP>
|
||||
<Type_C_Can_Act_As_Host value="false" />
|
||||
<Type_C_Can_Act_As_Device value="false" />
|
||||
<Type_C_Supports_Audio_Accessory value="false" />
|
||||
<Type_C_Is_VCONN_Powered_Accessory value="false" />
|
||||
<Type_C_Is_Debug_Target_SNK value="false" />
|
||||
<Captive_Cable value="false" />
|
||||
<Captive_Cable_Is_eMarked value="false" />
|
||||
<Type_C_Port_On_Hub value="false" />
|
||||
<Type_C_Power_Source value="2">Both</Type_C_Power_Source>
|
||||
<Type_C_Sources_VCONN value="true" />
|
||||
<Type_C_Is_Alt_Mode_Controller value="false" />
|
||||
<PD_Power_As_Source value="18000">18 W</PD_Power_As_Source>
|
||||
<EPR_Supported_As_Src value="false" />
|
||||
<USB_Suspend_May_Be_Cleared value="true" />
|
||||
<Sends_Pings value="false" />
|
||||
<FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
|
||||
<Master_Port value="false" />
|
||||
<Num_Src_PDOs value="2" />
|
||||
<PD_OC_Protection value="false" />
|
||||
<SrcPdoList>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="100">5 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="300">3 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="180">9 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="200">2 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
</SrcPdoList>
|
||||
<PD_Power_As_Sink value="18000">18 W</PD_Power_As_Sink>
|
||||
<EPR_Supported_As_Snk value="false" />
|
||||
<No_USB_Suspend_May_Be_Set value="true" />
|
||||
<GiveBack_May_Be_Set value="false" />
|
||||
<Higher_Capability_Set value="true" />
|
||||
<FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
|
||||
<Num_Snk_PDOs value="2" />
|
||||
<SnkPdoList>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="100">5 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="300">3 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="180">9 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="200">2 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
</SnkPdoList>
|
||||
<Accepts_PR_Swap_As_Src value="true" />
|
||||
<Accepts_PR_Swap_As_Snk value="true" />
|
||||
<Requests_PR_Swap_As_Src value="false" />
|
||||
<Requests_PR_Swap_As_Snk value="false" />
|
||||
<FR_Swap_Supported_As_Initial_Sink value="false" />
|
||||
<XID_SOP value="0" />
|
||||
<Data_Capable_As_USB_Host_SOP value="false" />
|
||||
<Data_Capable_As_USB_Device_SOP value="false" />
|
||||
<Product_Type_UFP_SOP value="0">Undefined</Product_Type_UFP_SOP>
|
||||
<Product_Type_DFP_SOP value="0">Undefined</Product_Type_DFP_SOP>
|
||||
<DFP_VDO_Port_Number value="0" />
|
||||
<Modal_Operation_Supported_SOP value="true" />
|
||||
<USB_VID_SOP value="8137">0x1FC9</USB_VID_SOP>
|
||||
<PID_SOP value="256">0x0100</PID_SOP>
|
||||
<bcdDevice_SOP value="256">0x0100</bcdDevice_SOP>
|
||||
<SVID_Fixed_SOP value="true" />
|
||||
<Num_SVIDs_Min_SOP value="1" />
|
||||
<Num_SVIDs_Max_SOP value="1" />
|
||||
<SOPSVIDList>
|
||||
<SOPSVID>
|
||||
<SVID_SOP value="8137">0x1FC9</SVID_SOP>
|
||||
<SVID_Modes_Fixed_SOP value="true" />
|
||||
<SVID_Num_Modes_Min_SOP value="1" />
|
||||
<SVID_Num_Modes_Max_SOP value="1" />
|
||||
<SOPSVIDModeList>
|
||||
<SOPSVIDMode>
|
||||
<SVID_Mode_Enter_SOP value="true" />
|
||||
<SVID_Mode_Recog_Mask_SOP value="4294967295">0xFFFFFFFF</SVID_Mode_Recog_Mask_SOP>
|
||||
<SVID_Mode_Recog_Value_SOP value="1">0x00000001</SVID_Mode_Recog_Value_SOP>
|
||||
</SOPSVIDMode>
|
||||
</SOPSVIDModeList>
|
||||
</SOPSVID>
|
||||
</SOPSVIDList>
|
||||
<Product_Total_Source_Power_mW value="0">0 W</Product_Total_Source_Power_mW>
|
||||
<Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>
|
||||
<Type_C_Supports_DP_Alt_Mode_as_DFP_D value="false" />
|
||||
<Type_C_Supports_DP_Alt_Mode_as_UFP_D value="false" />
|
||||
</Component>
|
||||
</VIF>
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
|
||||
<VIF_Specification>3.17</VIF_Specification>
|
||||
<VIF_App>
|
||||
<Vendor>Ellisys</Vendor>
|
||||
<Name>Ellisys USB Explorer 350 Examiner</Name>
|
||||
<Version>3.1.8098.23433</Version>
|
||||
</VIF_App>
|
||||
<Vendor_Name>NXP</Vendor_Name>
|
||||
<Model_Part_Number></Model_Part_Number>
|
||||
<Product_Revision></Product_Revision>
|
||||
<TID></TID>
|
||||
<VIF_Product_Type value="0">Port</VIF_Product_Type>
|
||||
<Certification_Type value="0">End Product</Certification_Type>
|
||||
<Product />
|
||||
<Component>
|
||||
<Port_Label></Port_Label>
|
||||
<Connector_Type value="2">Type-C</Connector_Type>
|
||||
<USB4_Supported value="false" />
|
||||
<USB_PD_Support value="true" />
|
||||
<PD_Port_Type value="4">DRP</PD_Port_Type>
|
||||
<Type_C_State_Machine value="2">DRP</Type_C_State_Machine>
|
||||
<Port_Battery_Powered value="false" />
|
||||
<BC_1_2_Support value="0">None</BC_1_2_Support>
|
||||
<PD_Spec_Revision_Major value="3" />
|
||||
<PD_Spec_Revision_Minor value="0" />
|
||||
<PD_Spec_Version_Major value="2" />
|
||||
<PD_Spec_Version_Minor value="0" />
|
||||
<PD_Specification_Revision value="2">v3.0</PD_Specification_Revision>
|
||||
<SOP_Capable value="true" />
|
||||
<SOP_P_Capable value="false" />
|
||||
<SOP_PP_Capable value="false" />
|
||||
<SOP_P_Debug_Capable value="false" />
|
||||
<SOP_PP_Debug_Capable value="false" />
|
||||
<Manufacturer_Info_Supported_Port value="true" />
|
||||
<Manufacturer_Info_VID_Port value="8137">0x1FC9</Manufacturer_Info_VID_Port>
|
||||
<Manufacturer_Info_PID_Port value="256">0x0100</Manufacturer_Info_PID_Port>
|
||||
<USB_Comms_Capable value="false" />
|
||||
<DR_Swap_To_DFP_Supported value="true" />
|
||||
<DR_Swap_To_UFP_Supported value="true" />
|
||||
<Unconstrained_Power value="true" />
|
||||
<VCONN_Swap_To_On_Supported value="true" />
|
||||
<VCONN_Swap_To_Off_Supported value="true" />
|
||||
<Responds_To_Discov_SOP_UFP value="true" />
|
||||
<Responds_To_Discov_SOP_DFP value="true" />
|
||||
<Attempts_Discov_SOP value="false" />
|
||||
<Power_Interruption_Available value="0">No Interruption Possible</Power_Interruption_Available>
|
||||
<Chunking_Implemented_SOP value="true" />
|
||||
<Data_Reset_Supported value="false" />
|
||||
<Enter_USB_Supported value="false" />
|
||||
<Unchunked_Extended_Messages_Supported value="true" />
|
||||
<Security_Msgs_Supported_SOP value="false" />
|
||||
<Num_Fixed_Batteries value="0" />
|
||||
<Num_Swappable_Battery_Slots value="0" />
|
||||
<ID_Header_Connector_Type_SOP value="2">USB Type-C Receptacle</ID_Header_Connector_Type_SOP>
|
||||
<Type_C_Can_Act_As_Host value="false" />
|
||||
<Type_C_Can_Act_As_Device value="false" />
|
||||
<Type_C_Implements_Try_SRC value="false" />
|
||||
<Type_C_Implements_Try_SNK value="false" />
|
||||
<Type_C_Supports_Audio_Accessory value="false" />
|
||||
<Type_C_Is_VCONN_Powered_Accessory value="false" />
|
||||
<Type_C_Is_Debug_Target_SRC value="false" />
|
||||
<Type_C_Is_Debug_Target_SNK value="false" />
|
||||
<Captive_Cable value="false" />
|
||||
<Captive_Cable_Is_eMarked value="false" />
|
||||
<RP_Value value="2">3A @ 5V</RP_Value>
|
||||
<Type_C_Port_On_Hub value="false" />
|
||||
<Type_C_Power_Source value="2">Both</Type_C_Power_Source>
|
||||
<Type_C_Sources_VCONN value="true" />
|
||||
<Type_C_Is_Alt_Mode_Controller value="false" />
|
||||
<PD_Power_As_Source value="18000">18 W</PD_Power_As_Source>
|
||||
<EPR_Supported_As_Src value="false" />
|
||||
<USB_Suspend_May_Be_Cleared value="true" />
|
||||
<Sends_Pings value="false" />
|
||||
<FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
|
||||
<Master_Port value="false" />
|
||||
<Num_Src_PDOs value="2" />
|
||||
<PD_OC_Protection value="false" />
|
||||
<SrcPdoList>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="100">5 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="300">3 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="180">9 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="200">2 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
</SrcPdoList>
|
||||
<PD_Power_As_Sink value="18000">18 W</PD_Power_As_Sink>
|
||||
<EPR_Supported_As_Snk value="false" />
|
||||
<No_USB_Suspend_May_Be_Set value="true" />
|
||||
<GiveBack_May_Be_Set value="false" />
|
||||
<Higher_Capability_Set value="true" />
|
||||
<FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
|
||||
<Num_Snk_PDOs value="2" />
|
||||
<SnkPdoList>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="100">5 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="300">3 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="180">9 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="200">2 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
</SnkPdoList>
|
||||
<Accepts_PR_Swap_As_Src value="true" />
|
||||
<Accepts_PR_Swap_As_Snk value="true" />
|
||||
<Requests_PR_Swap_As_Src value="false" />
|
||||
<Requests_PR_Swap_As_Snk value="false" />
|
||||
<FR_Swap_Supported_As_Initial_Sink value="false" />
|
||||
<XID_SOP value="0" />
|
||||
<Data_Capable_As_USB_Host_SOP value="false" />
|
||||
<Data_Capable_As_USB_Device_SOP value="false" />
|
||||
<Product_Type_UFP_SOP value="0">Undefined</Product_Type_UFP_SOP>
|
||||
<Product_Type_DFP_SOP value="0">Undefined</Product_Type_DFP_SOP>
|
||||
<DFP_VDO_Port_Number value="0" />
|
||||
<Modal_Operation_Supported_SOP value="true" />
|
||||
<USB_VID_SOP value="8137">0x1FC9</USB_VID_SOP>
|
||||
<PID_SOP value="256">0x0100</PID_SOP>
|
||||
<bcdDevice_SOP value="256">0x0100</bcdDevice_SOP>
|
||||
<SVID_Fixed_SOP value="true" />
|
||||
<Num_SVIDs_Min_SOP value="1" />
|
||||
<Num_SVIDs_Max_SOP value="1" />
|
||||
<SOPSVIDList>
|
||||
<SOPSVID>
|
||||
<SVID_SOP value="8137">0x1FC9</SVID_SOP>
|
||||
<SVID_Modes_Fixed_SOP value="true" />
|
||||
<SVID_Num_Modes_Min_SOP value="1" />
|
||||
<SVID_Num_Modes_Max_SOP value="1" />
|
||||
<SOPSVIDModeList>
|
||||
<SOPSVIDMode>
|
||||
<SVID_Mode_Enter_SOP value="true" />
|
||||
<SVID_Mode_Recog_Mask_SOP value="4294967295">0xFFFFFFFF</SVID_Mode_Recog_Mask_SOP>
|
||||
<SVID_Mode_Recog_Value_SOP value="1">0x00000001</SVID_Mode_Recog_Value_SOP>
|
||||
</SOPSVIDMode>
|
||||
</SOPSVIDModeList>
|
||||
</SOPSVID>
|
||||
</SOPSVIDList>
|
||||
<Product_Total_Source_Power_mW value="0">0 W</Product_Total_Source_Power_mW>
|
||||
<Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>
|
||||
<Type_C_Supports_DP_Alt_Mode_as_DFP_D value="false" />
|
||||
<Type_C_Supports_DP_Alt_Mode_as_UFP_D value="false" />
|
||||
</Component>
|
||||
</VIF>
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
|
||||
<VIF_Specification>3.17</VIF_Specification>
|
||||
<VIF_App>
|
||||
<Vendor>Ellisys</Vendor>
|
||||
<Name>Ellisys USB Explorer 350 Examiner</Name>
|
||||
<Version>3.1.8098.23433</Version>
|
||||
</VIF_App>
|
||||
<Vendor_Name>NXP</Vendor_Name>
|
||||
<Model_Part_Number></Model_Part_Number>
|
||||
<Product_Revision></Product_Revision>
|
||||
<TID></TID>
|
||||
<VIF_Product_Type value="0">Port</VIF_Product_Type>
|
||||
<Certification_Type value="0">End Product</Certification_Type>
|
||||
<Product />
|
||||
<Component>
|
||||
<Port_Label></Port_Label>
|
||||
<Connector_Type value="2">Type-C</Connector_Type>
|
||||
<USB4_Supported value="false" />
|
||||
<USB_PD_Support value="true" />
|
||||
<PD_Port_Type value="4">DRP</PD_Port_Type>
|
||||
<Type_C_State_Machine value="2">DRP</Type_C_State_Machine>
|
||||
<Port_Battery_Powered value="false" />
|
||||
<BC_1_2_Support value="0">None</BC_1_2_Support>
|
||||
<PD_Spec_Revision_Major value="3" />
|
||||
<PD_Spec_Revision_Minor value="0" />
|
||||
<PD_Spec_Version_Major value="2" />
|
||||
<PD_Spec_Version_Minor value="0" />
|
||||
<PD_Specification_Revision value="2">v3.0</PD_Specification_Revision>
|
||||
<SOP_Capable value="true" />
|
||||
<SOP_P_Capable value="false" />
|
||||
<SOP_PP_Capable value="false" />
|
||||
<SOP_P_Debug_Capable value="false" />
|
||||
<SOP_PP_Debug_Capable value="false" />
|
||||
<Manufacturer_Info_Supported_Port value="true" />
|
||||
<Manufacturer_Info_VID_Port value="8137">0x1FC9</Manufacturer_Info_VID_Port>
|
||||
<Manufacturer_Info_PID_Port value="256">0x0100</Manufacturer_Info_PID_Port>
|
||||
<USB_Comms_Capable value="false" />
|
||||
<DR_Swap_To_DFP_Supported value="true" />
|
||||
<DR_Swap_To_UFP_Supported value="true" />
|
||||
<Unconstrained_Power value="true" />
|
||||
<VCONN_Swap_To_On_Supported value="true" />
|
||||
<VCONN_Swap_To_Off_Supported value="true" />
|
||||
<Responds_To_Discov_SOP_UFP value="true" />
|
||||
<Responds_To_Discov_SOP_DFP value="true" />
|
||||
<Attempts_Discov_SOP value="false" />
|
||||
<Power_Interruption_Available value="0">No Interruption Possible</Power_Interruption_Available>
|
||||
<Chunking_Implemented_SOP value="true" />
|
||||
<Data_Reset_Supported value="false" />
|
||||
<Enter_USB_Supported value="false" />
|
||||
<Unchunked_Extended_Messages_Supported value="true" />
|
||||
<Security_Msgs_Supported_SOP value="false" />
|
||||
<Num_Fixed_Batteries value="0" />
|
||||
<Num_Swappable_Battery_Slots value="0" />
|
||||
<ID_Header_Connector_Type_SOP value="2">USB Type-C Receptacle</ID_Header_Connector_Type_SOP>
|
||||
<Type_C_Can_Act_As_Host value="false" />
|
||||
<Type_C_Can_Act_As_Device value="false" />
|
||||
<Type_C_Implements_Try_SRC value="false" />
|
||||
<Type_C_Implements_Try_SNK value="true" />
|
||||
<Type_C_Supports_Audio_Accessory value="false" />
|
||||
<Type_C_Is_VCONN_Powered_Accessory value="false" />
|
||||
<Type_C_Is_Debug_Target_SRC value="false" />
|
||||
<Type_C_Is_Debug_Target_SNK value="false" />
|
||||
<Captive_Cable value="false" />
|
||||
<Captive_Cable_Is_eMarked value="false" />
|
||||
<RP_Value value="2">3A @ 5V</RP_Value>
|
||||
<Type_C_Port_On_Hub value="false" />
|
||||
<Type_C_Power_Source value="2">Both</Type_C_Power_Source>
|
||||
<Type_C_Sources_VCONN value="true" />
|
||||
<Type_C_Is_Alt_Mode_Controller value="false" />
|
||||
<PD_Power_As_Source value="18000">18 W</PD_Power_As_Source>
|
||||
<EPR_Supported_As_Src value="false" />
|
||||
<USB_Suspend_May_Be_Cleared value="true" />
|
||||
<Sends_Pings value="false" />
|
||||
<FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
|
||||
<Master_Port value="false" />
|
||||
<Num_Src_PDOs value="2" />
|
||||
<PD_OC_Protection value="false" />
|
||||
<SrcPdoList>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="100">5 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="300">3 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="180">9 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="200">2 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
</SrcPdoList>
|
||||
<PD_Power_As_Sink value="18000">18 W</PD_Power_As_Sink>
|
||||
<EPR_Supported_As_Snk value="false" />
|
||||
<No_USB_Suspend_May_Be_Set value="true" />
|
||||
<GiveBack_May_Be_Set value="false" />
|
||||
<Higher_Capability_Set value="true" />
|
||||
<FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
|
||||
<Num_Snk_PDOs value="2" />
|
||||
<SnkPdoList>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="100">5 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="300">3 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="180">9 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="200">2 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
</SnkPdoList>
|
||||
<Accepts_PR_Swap_As_Src value="true" />
|
||||
<Accepts_PR_Swap_As_Snk value="true" />
|
||||
<Requests_PR_Swap_As_Src value="false" />
|
||||
<Requests_PR_Swap_As_Snk value="false" />
|
||||
<FR_Swap_Supported_As_Initial_Sink value="false" />
|
||||
<XID_SOP value="0" />
|
||||
<Data_Capable_As_USB_Host_SOP value="false" />
|
||||
<Data_Capable_As_USB_Device_SOP value="false" />
|
||||
<Product_Type_UFP_SOP value="0">Undefined</Product_Type_UFP_SOP>
|
||||
<Product_Type_DFP_SOP value="0">Undefined</Product_Type_DFP_SOP>
|
||||
<DFP_VDO_Port_Number value="0" />
|
||||
<Modal_Operation_Supported_SOP value="true" />
|
||||
<USB_VID_SOP value="8137">0x1FC9</USB_VID_SOP>
|
||||
<PID_SOP value="256">0x0100</PID_SOP>
|
||||
<bcdDevice_SOP value="256">0x0100</bcdDevice_SOP>
|
||||
<SVID_Fixed_SOP value="true" />
|
||||
<Num_SVIDs_Min_SOP value="1" />
|
||||
<Num_SVIDs_Max_SOP value="1" />
|
||||
<SOPSVIDList>
|
||||
<SOPSVID>
|
||||
<SVID_SOP value="8137">0x1FC9</SVID_SOP>
|
||||
<SVID_Modes_Fixed_SOP value="true" />
|
||||
<SVID_Num_Modes_Min_SOP value="1" />
|
||||
<SVID_Num_Modes_Max_SOP value="1" />
|
||||
<SOPSVIDModeList>
|
||||
<SOPSVIDMode>
|
||||
<SVID_Mode_Enter_SOP value="true" />
|
||||
<SVID_Mode_Recog_Mask_SOP value="4294967295">0xFFFFFFFF</SVID_Mode_Recog_Mask_SOP>
|
||||
<SVID_Mode_Recog_Value_SOP value="1">0x00000001</SVID_Mode_Recog_Value_SOP>
|
||||
</SOPSVIDMode>
|
||||
</SOPSVIDModeList>
|
||||
</SOPSVID>
|
||||
</SOPSVIDList>
|
||||
<Product_Total_Source_Power_mW value="0">0 W</Product_Total_Source_Power_mW>
|
||||
<Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>
|
||||
<Type_C_Supports_DP_Alt_Mode_as_DFP_D value="false" />
|
||||
<Type_C_Supports_DP_Alt_Mode_as_UFP_D value="false" />
|
||||
</Component>
|
||||
</VIF>
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
|
||||
<VIF_Specification>3.17</VIF_Specification>
|
||||
<VIF_App>
|
||||
<Vendor>Ellisys</Vendor>
|
||||
<Name>Ellisys USB Explorer 350 Examiner</Name>
|
||||
<Version>3.1.8098.23433</Version>
|
||||
</VIF_App>
|
||||
<Vendor_Name>NXP</Vendor_Name>
|
||||
<Model_Part_Number></Model_Part_Number>
|
||||
<Product_Revision></Product_Revision>
|
||||
<TID></TID>
|
||||
<VIF_Product_Type value="0">Port</VIF_Product_Type>
|
||||
<Certification_Type value="0">End Product</Certification_Type>
|
||||
<Product />
|
||||
<Component>
|
||||
<Port_Label></Port_Label>
|
||||
<Connector_Type value="2">Type-C</Connector_Type>
|
||||
<USB4_Supported value="false" />
|
||||
<USB_PD_Support value="true" />
|
||||
<PD_Port_Type value="4">DRP</PD_Port_Type>
|
||||
<Type_C_State_Machine value="2">DRP</Type_C_State_Machine>
|
||||
<Port_Battery_Powered value="false" />
|
||||
<BC_1_2_Support value="0">None</BC_1_2_Support>
|
||||
<PD_Spec_Revision_Major value="3" />
|
||||
<PD_Spec_Revision_Minor value="0" />
|
||||
<PD_Spec_Version_Major value="2" />
|
||||
<PD_Spec_Version_Minor value="0" />
|
||||
<PD_Specification_Revision value="2">v3.0</PD_Specification_Revision>
|
||||
<SOP_Capable value="true" />
|
||||
<SOP_P_Capable value="false" />
|
||||
<SOP_PP_Capable value="false" />
|
||||
<SOP_P_Debug_Capable value="false" />
|
||||
<SOP_PP_Debug_Capable value="false" />
|
||||
<Manufacturer_Info_Supported_Port value="true" />
|
||||
<Manufacturer_Info_VID_Port value="8137">0x1FC9</Manufacturer_Info_VID_Port>
|
||||
<Manufacturer_Info_PID_Port value="256">0x0100</Manufacturer_Info_PID_Port>
|
||||
<USB_Comms_Capable value="false" />
|
||||
<DR_Swap_To_DFP_Supported value="true" />
|
||||
<DR_Swap_To_UFP_Supported value="true" />
|
||||
<Unconstrained_Power value="true" />
|
||||
<VCONN_Swap_To_On_Supported value="true" />
|
||||
<VCONN_Swap_To_Off_Supported value="true" />
|
||||
<Responds_To_Discov_SOP_UFP value="true" />
|
||||
<Responds_To_Discov_SOP_DFP value="true" />
|
||||
<Attempts_Discov_SOP value="false" />
|
||||
<Power_Interruption_Available value="0">No Interruption Possible</Power_Interruption_Available>
|
||||
<Chunking_Implemented_SOP value="true" />
|
||||
<Data_Reset_Supported value="false" />
|
||||
<Enter_USB_Supported value="false" />
|
||||
<Unchunked_Extended_Messages_Supported value="true" />
|
||||
<Security_Msgs_Supported_SOP value="false" />
|
||||
<Num_Fixed_Batteries value="0" />
|
||||
<Num_Swappable_Battery_Slots value="0" />
|
||||
<ID_Header_Connector_Type_SOP value="2">USB Type-C Receptacle</ID_Header_Connector_Type_SOP>
|
||||
<Type_C_Can_Act_As_Host value="false" />
|
||||
<Type_C_Can_Act_As_Device value="false" />
|
||||
<Type_C_Implements_Try_SRC value="true" />
|
||||
<Type_C_Implements_Try_SNK value="false" />
|
||||
<Type_C_Supports_Audio_Accessory value="false" />
|
||||
<Type_C_Is_VCONN_Powered_Accessory value="false" />
|
||||
<Type_C_Is_Debug_Target_SRC value="false" />
|
||||
<Type_C_Is_Debug_Target_SNK value="false" />
|
||||
<Captive_Cable value="false" />
|
||||
<Captive_Cable_Is_eMarked value="false" />
|
||||
<RP_Value value="2">3A @ 5V</RP_Value>
|
||||
<Type_C_Port_On_Hub value="false" />
|
||||
<Type_C_Power_Source value="2">Both</Type_C_Power_Source>
|
||||
<Type_C_Sources_VCONN value="true" />
|
||||
<Type_C_Is_Alt_Mode_Controller value="false" />
|
||||
<PD_Power_As_Source value="18000">18 W</PD_Power_As_Source>
|
||||
<EPR_Supported_As_Src value="false" />
|
||||
<USB_Suspend_May_Be_Cleared value="true" />
|
||||
<Sends_Pings value="false" />
|
||||
<FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
|
||||
<Master_Port value="false" />
|
||||
<Num_Src_PDOs value="2" />
|
||||
<PD_OC_Protection value="false" />
|
||||
<SrcPdoList>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="100">5 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="300">3 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="180">9 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="200">2 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
</SrcPdoList>
|
||||
<PD_Power_As_Sink value="18000">18 W</PD_Power_As_Sink>
|
||||
<EPR_Supported_As_Snk value="false" />
|
||||
<No_USB_Suspend_May_Be_Set value="true" />
|
||||
<GiveBack_May_Be_Set value="false" />
|
||||
<Higher_Capability_Set value="true" />
|
||||
<FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
|
||||
<Num_Snk_PDOs value="2" />
|
||||
<SnkPdoList>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="100">5 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="300">3 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="180">9 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="200">2 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
</SnkPdoList>
|
||||
<Accepts_PR_Swap_As_Src value="true" />
|
||||
<Accepts_PR_Swap_As_Snk value="true" />
|
||||
<Requests_PR_Swap_As_Src value="false" />
|
||||
<Requests_PR_Swap_As_Snk value="false" />
|
||||
<FR_Swap_Supported_As_Initial_Sink value="false" />
|
||||
<XID_SOP value="0" />
|
||||
<Data_Capable_As_USB_Host_SOP value="false" />
|
||||
<Data_Capable_As_USB_Device_SOP value="false" />
|
||||
<Product_Type_UFP_SOP value="0">Undefined</Product_Type_UFP_SOP>
|
||||
<Product_Type_DFP_SOP value="0">Undefined</Product_Type_DFP_SOP>
|
||||
<DFP_VDO_Port_Number value="0" />
|
||||
<Modal_Operation_Supported_SOP value="true" />
|
||||
<USB_VID_SOP value="8137">0x1FC9</USB_VID_SOP>
|
||||
<PID_SOP value="256">0x0100</PID_SOP>
|
||||
<bcdDevice_SOP value="256">0x0100</bcdDevice_SOP>
|
||||
<SVID_Fixed_SOP value="true" />
|
||||
<Num_SVIDs_Min_SOP value="1" />
|
||||
<Num_SVIDs_Max_SOP value="1" />
|
||||
<SOPSVIDList>
|
||||
<SOPSVID>
|
||||
<SVID_SOP value="8137">0x1FC9</SVID_SOP>
|
||||
<SVID_Modes_Fixed_SOP value="true" />
|
||||
<SVID_Num_Modes_Min_SOP value="1" />
|
||||
<SVID_Num_Modes_Max_SOP value="1" />
|
||||
<SOPSVIDModeList>
|
||||
<SOPSVIDMode>
|
||||
<SVID_Mode_Enter_SOP value="true" />
|
||||
<SVID_Mode_Recog_Mask_SOP value="4294967295">0xFFFFFFFF</SVID_Mode_Recog_Mask_SOP>
|
||||
<SVID_Mode_Recog_Value_SOP value="1">0x00000001</SVID_Mode_Recog_Value_SOP>
|
||||
</SOPSVIDMode>
|
||||
</SOPSVIDModeList>
|
||||
</SOPSVID>
|
||||
</SOPSVIDList>
|
||||
<Product_Total_Source_Power_mW value="0">0 W</Product_Total_Source_Power_mW>
|
||||
<Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>
|
||||
<Type_C_Supports_DP_Alt_Mode_as_DFP_D value="false" />
|
||||
<Type_C_Supports_DP_Alt_Mode_as_UFP_D value="false" />
|
||||
</Component>
|
||||
</VIF>
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<VIF xmlns="http://usb.org/VendorInfoFile.xsd">
|
||||
<VIF_Specification>3.17</VIF_Specification>
|
||||
<VIF_App>
|
||||
<Vendor>Ellisys</Vendor>
|
||||
<Name>Ellisys USB Explorer 350 Examiner</Name>
|
||||
<Version>3.1.8098.23433</Version>
|
||||
</VIF_App>
|
||||
<Vendor_Name>NXP</Vendor_Name>
|
||||
<Model_Part_Number></Model_Part_Number>
|
||||
<Product_Revision></Product_Revision>
|
||||
<TID></TID>
|
||||
<VIF_Product_Type value="0">Port</VIF_Product_Type>
|
||||
<Certification_Type value="0">End Product</Certification_Type>
|
||||
<Product />
|
||||
<Component>
|
||||
<Port_Label></Port_Label>
|
||||
<Connector_Type value="2">Type-C</Connector_Type>
|
||||
<USB4_Supported value="false" />
|
||||
<USB_PD_Support value="true" />
|
||||
<PD_Port_Type value="2">Provider / Consumer</PD_Port_Type>
|
||||
<Type_C_State_Machine value="0">Source</Type_C_State_Machine>
|
||||
<Port_Battery_Powered value="false" />
|
||||
<BC_1_2_Support value="0">None</BC_1_2_Support>
|
||||
<PD_Spec_Revision_Major value="3" />
|
||||
<PD_Spec_Revision_Minor value="0" />
|
||||
<PD_Spec_Version_Major value="2" />
|
||||
<PD_Spec_Version_Minor value="0" />
|
||||
<PD_Specification_Revision value="2">v3.0</PD_Specification_Revision>
|
||||
<SOP_Capable value="true" />
|
||||
<SOP_P_Capable value="false" />
|
||||
<SOP_PP_Capable value="false" />
|
||||
<SOP_P_Debug_Capable value="false" />
|
||||
<SOP_PP_Debug_Capable value="false" />
|
||||
<Manufacturer_Info_Supported_Port value="true" />
|
||||
<Manufacturer_Info_VID_Port value="8137">0x1FC9</Manufacturer_Info_VID_Port>
|
||||
<Manufacturer_Info_PID_Port value="256">0x0100</Manufacturer_Info_PID_Port>
|
||||
<USB_Comms_Capable value="false" />
|
||||
<DR_Swap_To_DFP_Supported value="true" />
|
||||
<DR_Swap_To_UFP_Supported value="true" />
|
||||
<Unconstrained_Power value="true" />
|
||||
<VCONN_Swap_To_On_Supported value="true" />
|
||||
<VCONN_Swap_To_Off_Supported value="true" />
|
||||
<Responds_To_Discov_SOP_UFP value="true" />
|
||||
<Responds_To_Discov_SOP_DFP value="true" />
|
||||
<Attempts_Discov_SOP value="false" />
|
||||
<Power_Interruption_Available value="0">No Interruption Possible</Power_Interruption_Available>
|
||||
<Chunking_Implemented_SOP value="true" />
|
||||
<Data_Reset_Supported value="false" />
|
||||
<Enter_USB_Supported value="false" />
|
||||
<Unchunked_Extended_Messages_Supported value="true" />
|
||||
<Security_Msgs_Supported_SOP value="false" />
|
||||
<Num_Fixed_Batteries value="0" />
|
||||
<Num_Swappable_Battery_Slots value="0" />
|
||||
<ID_Header_Connector_Type_SOP value="2">USB Type-C Receptacle</ID_Header_Connector_Type_SOP>
|
||||
<Type_C_Can_Act_As_Host value="false" />
|
||||
<Type_C_Can_Act_As_Device value="false" />
|
||||
<Type_C_Supports_Audio_Accessory value="false" />
|
||||
<Type_C_Is_VCONN_Powered_Accessory value="false" />
|
||||
<Type_C_Is_Debug_Target_SRC value="false" />
|
||||
<Captive_Cable value="false" />
|
||||
<Captive_Cable_Is_eMarked value="false" />
|
||||
<RP_Value value="2">3A @ 5V</RP_Value>
|
||||
<Type_C_Port_On_Hub value="false" />
|
||||
<Type_C_Power_Source value="2">Both</Type_C_Power_Source>
|
||||
<Type_C_Sources_VCONN value="true" />
|
||||
<Type_C_Is_Alt_Mode_Controller value="false" />
|
||||
<PD_Power_As_Source value="18000">18 W</PD_Power_As_Source>
|
||||
<EPR_Supported_As_Src value="false" />
|
||||
<USB_Suspend_May_Be_Cleared value="true" />
|
||||
<Sends_Pings value="false" />
|
||||
<FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
|
||||
<Master_Port value="false" />
|
||||
<Num_Src_PDOs value="2" />
|
||||
<PD_OC_Protection value="false" />
|
||||
<SrcPdoList>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="100">5 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="300">3 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
<SrcPDO>
|
||||
<Src_PDO_Supply_Type value="0">Fixed</Src_PDO_Supply_Type>
|
||||
<Src_PDO_Peak_Current value="0">100% IOC</Src_PDO_Peak_Current>
|
||||
<Src_PDO_Voltage value="180">9 V</Src_PDO_Voltage>
|
||||
<Src_PDO_Max_Current value="200">2 A</Src_PDO_Max_Current>
|
||||
<Src_PD_OCP_OC_Debounce value="0">0 s</Src_PD_OCP_OC_Debounce>
|
||||
<Src_PD_OCP_OC_Threshold value="0">0 A</Src_PD_OCP_OC_Threshold>
|
||||
</SrcPDO>
|
||||
</SrcPdoList>
|
||||
<PD_Power_As_Sink value="18000">18 W</PD_Power_As_Sink>
|
||||
<EPR_Supported_As_Snk value="false" />
|
||||
<No_USB_Suspend_May_Be_Set value="true" />
|
||||
<GiveBack_May_Be_Set value="false" />
|
||||
<Higher_Capability_Set value="true" />
|
||||
<FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
|
||||
<Num_Snk_PDOs value="2" />
|
||||
<SnkPdoList>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="100">5 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="300">3 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
<SnkPDO>
|
||||
<Snk_PDO_Supply_Type value="0">Fixed</Snk_PDO_Supply_Type>
|
||||
<Snk_PDO_Voltage value="180">9 V</Snk_PDO_Voltage>
|
||||
<Snk_PDO_Op_Current value="200">2 A</Snk_PDO_Op_Current>
|
||||
</SnkPDO>
|
||||
</SnkPdoList>
|
||||
<Accepts_PR_Swap_As_Src value="true" />
|
||||
<Accepts_PR_Swap_As_Snk value="true" />
|
||||
<Requests_PR_Swap_As_Src value="false" />
|
||||
<Requests_PR_Swap_As_Snk value="false" />
|
||||
<FR_Swap_Supported_As_Initial_Sink value="false" />
|
||||
<XID_SOP value="0" />
|
||||
<Data_Capable_As_USB_Host_SOP value="false" />
|
||||
<Data_Capable_As_USB_Device_SOP value="false" />
|
||||
<Product_Type_UFP_SOP value="0">Undefined</Product_Type_UFP_SOP>
|
||||
<Product_Type_DFP_SOP value="0">Undefined</Product_Type_DFP_SOP>
|
||||
<DFP_VDO_Port_Number value="0" />
|
||||
<Modal_Operation_Supported_SOP value="true" />
|
||||
<USB_VID_SOP value="8137">0x1FC9</USB_VID_SOP>
|
||||
<PID_SOP value="256">0x0100</PID_SOP>
|
||||
<bcdDevice_SOP value="256">0x0100</bcdDevice_SOP>
|
||||
<SVID_Fixed_SOP value="true" />
|
||||
<Num_SVIDs_Min_SOP value="1" />
|
||||
<Num_SVIDs_Max_SOP value="1" />
|
||||
<SOPSVIDList>
|
||||
<SOPSVID>
|
||||
<SVID_SOP value="8137">0x1FC9</SVID_SOP>
|
||||
<SVID_Modes_Fixed_SOP value="true" />
|
||||
<SVID_Num_Modes_Min_SOP value="1" />
|
||||
<SVID_Num_Modes_Max_SOP value="1" />
|
||||
<SOPSVIDModeList>
|
||||
<SOPSVIDMode>
|
||||
<SVID_Mode_Enter_SOP value="true" />
|
||||
<SVID_Mode_Recog_Mask_SOP value="4294967295">0xFFFFFFFF</SVID_Mode_Recog_Mask_SOP>
|
||||
<SVID_Mode_Recog_Value_SOP value="1">0x00000001</SVID_Mode_Recog_Value_SOP>
|
||||
</SOPSVIDMode>
|
||||
</SOPSVIDModeList>
|
||||
</SOPSVID>
|
||||
</SOPSVIDList>
|
||||
<Product_Total_Source_Power_mW value="0">0 W</Product_Total_Source_Power_mW>
|
||||
<Port_Source_Power_Type value="0">Assured</Port_Source_Power_Type>
|
||||
<Type_C_Supports_DP_Alt_Mode_as_DFP_D value="false" />
|
||||
<Type_C_Supports_DP_Alt_Mode_as_UFP_D value="false" />
|
||||
</Component>
|
||||
</VIF>
|
||||
|
|
@ -1,165 +0,0 @@
|
|||
# CROSS COMPILER SETTING
|
||||
SET(CMAKE_SYSTEM_NAME Generic)
|
||||
CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
|
||||
|
||||
# THE VERSION NUMBER
|
||||
SET (Tutorial_VERSION_MAJOR 1)
|
||||
SET (Tutorial_VERSION_MINOR 0)
|
||||
|
||||
# ENABLE ASM
|
||||
ENABLE_LANGUAGE(ASM)
|
||||
|
||||
SET(CMAKE_STATIC_LIBRARY_PREFIX)
|
||||
SET(CMAKE_STATIC_LIBRARY_SUFFIX)
|
||||
|
||||
SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
|
||||
SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
|
||||
|
||||
# CURRENT DIRECTORY
|
||||
SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
|
||||
|
||||
SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
|
||||
|
||||
|
||||
project(usb_pd_bm)
|
||||
|
||||
set(MCUX_BUILD_TYPES debug release)
|
||||
|
||||
set(MCUX_SDK_PROJECT_NAME usb_pd_bm.elf)
|
||||
|
||||
if (NOT DEFINED SdkRootDirPath)
|
||||
SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
|
||||
endif()
|
||||
|
||||
include(${ProjDirPath}/flags.cmake)
|
||||
|
||||
include(${ProjDirPath}/config.cmake)
|
||||
|
||||
add_executable(${MCUX_SDK_PROJECT_NAME}
|
||||
"${ProjDirPath}/../pd_board_config.h"
|
||||
"${ProjDirPath}/../pd_app_demo.c"
|
||||
"${ProjDirPath}/../pd_app.c"
|
||||
"${ProjDirPath}/../pd_app.h"
|
||||
"${ProjDirPath}/../pd_command_app.c"
|
||||
"${ProjDirPath}/../pd_command_interface.c"
|
||||
"${ProjDirPath}/../pd_command_interface.h"
|
||||
"${ProjDirPath}/../pd_power_app.c"
|
||||
"${ProjDirPath}/../pd_power_interface.c"
|
||||
"${ProjDirPath}/../pd_power_interface.h"
|
||||
"${ProjDirPath}/../usb_pd_config.h"
|
||||
"${ProjDirPath}/../pd_power_nx20p3483.c"
|
||||
"${ProjDirPath}/../pd_power_nx20p3483.h"
|
||||
"${ProjDirPath}/../board.c"
|
||||
"${ProjDirPath}/../board.h"
|
||||
"${ProjDirPath}/../clock_config.c"
|
||||
"${ProjDirPath}/../clock_config.h"
|
||||
"${ProjDirPath}/../pin_mux.c"
|
||||
"${ProjDirPath}/../pin_mux.h"
|
||||
)
|
||||
|
||||
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
|
||||
${ProjDirPath}/..
|
||||
)
|
||||
|
||||
set(CMAKE_MODULE_PATH
|
||||
${SdkRootDirPath}/middleware/usb
|
||||
${SdkRootDirPath}/devices/LPC55S69/drivers
|
||||
${SdkRootDirPath}/components/i2c
|
||||
${SdkRootDirPath}/middleware
|
||||
${SdkRootDirPath}/components/osa
|
||||
${SdkRootDirPath}/devices/LPC55S69
|
||||
${SdkRootDirPath}/devices/LPC55S69/utilities
|
||||
${SdkRootDirPath}/components/uart
|
||||
${SdkRootDirPath}/components/serial_manager
|
||||
${SdkRootDirPath}/components/lists
|
||||
${SdkRootDirPath}/components/gpio
|
||||
${SdkRootDirPath}/components/timer
|
||||
${SdkRootDirPath}/CMSIS/Core/Include
|
||||
)
|
||||
|
||||
# include modules
|
||||
include(middleware_usb_pd_phy_ptn5110_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_usb_pd_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_lpc_dma_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_i2c_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_i2c_dma_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_flexcomm_i2c_adapter_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_mrt_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_gint_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_baremetal_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_osa_bm_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_clock_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_power_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_common_LPC55S69_cm33_core0)
|
||||
|
||||
include(device_LPC55S69_CMSIS_LPC55S69_cm33_core0)
|
||||
|
||||
include(device_LPC55S69_startup_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_usart_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_flexcomm_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_lpc_gpio_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_lpc_iocon_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_reset_LPC55S69_cm33_core0)
|
||||
|
||||
include(utility_assert_LPC55S69_cm33_core0)
|
||||
|
||||
include(utility_debug_console_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_usart_adapter_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_serial_manager_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_lists_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_serial_manager_uart_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_lpc_gpio_adapter_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_mrt_adapter_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_inputmux_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_pint_LPC55S69_cm33_core0)
|
||||
|
||||
include(CMSIS_Include_core_cm_LPC55S69_cm33_core0)
|
||||
|
||||
include(driver_inputmux_connections_LPC55S69_cm33_core0)
|
||||
|
||||
include(component_osa_LPC55S69_cm33_core0)
|
||||
|
||||
include(middleware_usb_pd_common_header_LPC55S69_cm33_core0)
|
||||
|
||||
include(utilities_misc_utilities_LPC55S69_cm33_core0)
|
||||
|
||||
include(device_LPC55S69_system_LPC55S69_cm33_core0)
|
||||
|
||||
|
||||
IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
|
||||
SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
|
||||
ENDIF()
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
|
||||
|
||||
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
|
||||
|
||||
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
|
||||
|
||||
|
||||
|
|
@ -1,234 +0,0 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC55S69JBD100_cm33_core0
|
||||
** LPC55S69JBD64_cm33_core0
|
||||
** LPC55S69JEV98_cm33_core0
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
|
||||
** Version: rev. 1.1, 2019-05-16
|
||||
** Build: b210928
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
|
||||
RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200
|
||||
m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x00071E00
|
||||
m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x0002B800
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE
|
||||
rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
|
||||
m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* section for storing the secondary core image */
|
||||
.core1_code :
|
||||
{
|
||||
. = ALIGN(4) ;
|
||||
KEEP (*(.core1_code))
|
||||
*(.core1_code*)
|
||||
. = ALIGN(4) ;
|
||||
} > m_core1_image
|
||||
|
||||
/* NOINIT section for rpmsg_sh_mem */
|
||||
.noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
__RPMSG_SH_MEM_START__ = .;
|
||||
*(.noinit.$rpmsg_sh_mem*)
|
||||
. = ALIGN(4) ;
|
||||
__RPMSG_SH_MEM_END__ = .;
|
||||
} > rpmsg_sh_mem
|
||||
|
||||
/* The startup code goes first into internal flash */
|
||||
.interrupts :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.ramfunc*) /* for functions in ram */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
m_usb_bdt (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(512);
|
||||
*(m_usb_bdt)
|
||||
} > m_usb_sram
|
||||
|
||||
m_usb_global (NOLOAD) :
|
||||
{
|
||||
*(m_usb_global)
|
||||
} > m_usb_sram
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
|
||||
}
|
||||
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
if exist CMakeFiles (RD /s /Q CMakeFiles)
|
||||
if exist Makefile (DEL /s /Q /F Makefile)
|
||||
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
|
||||
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
mingw32-make -j 2> build_log.txt
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#!/bin/sh
|
||||
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
|
||||
if [ -f "Makefile" ];then rm -f Makefile; fi
|
||||
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
|
||||
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
|
||||
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
|
||||
make -j 2>&1 | tee build_log.txt
|
||||
|
|
@ -1,185 +0,0 @@
|
|||
IF(NOT DEFINED FPU)
|
||||
SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16")
|
||||
ENDIF()
|
||||
|
||||
IF(NOT DEFINED SPECS)
|
||||
SET(SPECS "--specs=nano.specs --specs=nosys.specs")
|
||||
ENDIF()
|
||||
|
||||
IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
|
||||
SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
|
||||
ENDIF()
|
||||
|
||||
SET(CMAKE_ASM_FLAGS_DEBUG " \
|
||||
${CMAKE_ASM_FLAGS_DEBUG} \
|
||||
-DDEBUG \
|
||||
-D__STARTUP_CLEAR_BSS \
|
||||
-mcpu=cortex-m33 \
|
||||
-mthumb \
|
||||
${FPU} \
|
||||
")
|
||||
SET(CMAKE_ASM_FLAGS_RELEASE " \
|
||||
${CMAKE_ASM_FLAGS_RELEASE} \
|
||||
-DNDEBUG \
|
||||
-D__STARTUP_CLEAR_BSS \
|
||||
-mcpu=cortex-m33 \
|
||||
-mthumb \
|
||||
${FPU} \
|
||||
")
|
||||
SET(CMAKE_C_FLAGS_DEBUG " \
|
||||
${CMAKE_C_FLAGS_DEBUG} \
|
||||
-D_DEBUG=1 \
|
||||
-DDEBUG \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0=1 \
|
||||
-DDEBUG_CONSOLE_TRANSMIT_BUFFER_LEN=600 \
|
||||
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
|
||||
-DFSL_OSA_BM_TASK_ENABLE=0 \
|
||||
-DFSL_OSA_BM_TIMER_CONFIG=0 \
|
||||
-DI2C_RETRY_TIMES=40000 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-std=gnu99 \
|
||||
${FPU} \
|
||||
${DEBUG_CONSOLE_CONFIG} \
|
||||
")
|
||||
SET(CMAKE_C_FLAGS_RELEASE " \
|
||||
${CMAKE_C_FLAGS_RELEASE} \
|
||||
-D_DEBUG=0 \
|
||||
-DNDEBUG \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0=1 \
|
||||
-DDEBUG_CONSOLE_TRANSMIT_BUFFER_LEN=600 \
|
||||
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
|
||||
-DFSL_OSA_BM_TASK_ENABLE=0 \
|
||||
-DFSL_OSA_BM_TIMER_CONFIG=0 \
|
||||
-DI2C_RETRY_TIMES=40000 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-std=gnu99 \
|
||||
${FPU} \
|
||||
${DEBUG_CONSOLE_CONFIG} \
|
||||
")
|
||||
SET(CMAKE_CXX_FLAGS_DEBUG " \
|
||||
${CMAKE_CXX_FLAGS_DEBUG} \
|
||||
-DDEBUG \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-g \
|
||||
-O0 \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-fno-rtti \
|
||||
-fno-exceptions \
|
||||
${FPU} \
|
||||
${DEBUG_CONSOLE_CONFIG} \
|
||||
")
|
||||
SET(CMAKE_CXX_FLAGS_RELEASE " \
|
||||
${CMAKE_CXX_FLAGS_RELEASE} \
|
||||
-DNDEBUG \
|
||||
-DCPU_LPC55S69JBD100_cm33_core0 \
|
||||
-DSERIAL_PORT_TYPE_UART=1 \
|
||||
-DMCUXPRESSO_SDK \
|
||||
-Os \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-mthumb \
|
||||
-MMD \
|
||||
-MP \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mapcs \
|
||||
-fno-rtti \
|
||||
-fno-exceptions \
|
||||
${FPU} \
|
||||
${DEBUG_CONSOLE_CONFIG} \
|
||||
")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
|
||||
${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
|
||||
-g \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mthumb \
|
||||
-mapcs \
|
||||
-Xlinker \
|
||||
--gc-sections \
|
||||
-Xlinker \
|
||||
-static \
|
||||
-Xlinker \
|
||||
-z \
|
||||
-Xlinker \
|
||||
muldefs \
|
||||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
${FPU} \
|
||||
${SPECS} \
|
||||
-T${ProjDirPath}/LPC55S69_cm33_core0_flash.ld -static \
|
||||
")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
|
||||
${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
|
||||
-mcpu=cortex-m33 \
|
||||
-Wall \
|
||||
-fno-common \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding \
|
||||
-fno-builtin \
|
||||
-mthumb \
|
||||
-mapcs \
|
||||
-Xlinker \
|
||||
--gc-sections \
|
||||
-Xlinker \
|
||||
-static \
|
||||
-Xlinker \
|
||||
-z \
|
||||
-Xlinker \
|
||||
muldefs \
|
||||
-Xlinker \
|
||||
-Map=output.map \
|
||||
-Wl,--print-memory-usage \
|
||||
${FPU} \
|
||||
${SPECS} \
|
||||
-T${ProjDirPath}/LPC55S69_cm33_core0_flash.ld -static \
|
||||
")
|
||||
|
|
@ -1,135 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
#include "fsl_i2c.h"
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
void BOARD_InitDebugConsole_Core1(void)
|
||||
{
|
||||
/* attach 12 MHz clock to FLEXCOMM1 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH_CORE1);
|
||||
|
||||
RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
|
||||
|
||||
uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
|
||||
uartClkSrcFreq);
|
||||
}
|
||||
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
|
||||
{
|
||||
i2c_master_config_t i2cConfig = {0};
|
||||
|
||||
I2C_MasterGetDefaultConfig(&i2cConfig);
|
||||
I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
|
||||
}
|
||||
|
||||
status_t BOARD_I2C_Send(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
i2c_master_transfer_t masterXfer;
|
||||
|
||||
/* Prepare transfer structure. */
|
||||
masterXfer.slaveAddress = deviceAddress;
|
||||
masterXfer.direction = kI2C_Write;
|
||||
masterXfer.subaddress = subAddress;
|
||||
masterXfer.subaddressSize = subaddressSize;
|
||||
masterXfer.data = txBuff;
|
||||
masterXfer.dataSize = txBuffSize;
|
||||
masterXfer.flags = kI2C_TransferDefaultFlag;
|
||||
|
||||
return I2C_MasterTransferBlocking(base, &masterXfer);
|
||||
}
|
||||
|
||||
status_t BOARD_I2C_Receive(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
i2c_master_transfer_t masterXfer;
|
||||
|
||||
/* Prepare transfer structure. */
|
||||
masterXfer.slaveAddress = deviceAddress;
|
||||
masterXfer.subaddress = subAddress;
|
||||
masterXfer.subaddressSize = subaddressSize;
|
||||
masterXfer.data = rxBuff;
|
||||
masterXfer.dataSize = rxBuffSize;
|
||||
masterXfer.direction = kI2C_Read;
|
||||
masterXfer.flags = kI2C_TransferDefaultFlag;
|
||||
|
||||
return I2C_MasterTransferBlocking(base, &masterXfer);
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
|
@ -1,223 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_reset.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_iocon.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "LPCXpresso55S69"
|
||||
|
||||
/*! @brief The UART to use for debug messages. */
|
||||
/* TODO: rename UART to USART */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
|
||||
#define BOARD_DEBUG_UART_INSTANCE 0U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
|
||||
#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0
|
||||
#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
|
||||
#define BOARD_UART_IRQ FLEXCOMM0_IRQn
|
||||
|
||||
#define BOARD_ACCEL_I2C_BASEADDR I2C4
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
|
||||
|
||||
#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U
|
||||
#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1
|
||||
#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn
|
||||
#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1
|
||||
#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler
|
||||
#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1
|
||||
#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR I2C4
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
|
||||
#define BOARD_CODEC_I2C_INSTANCE 4
|
||||
#ifndef BOARD_LED_RED_GPIO
|
||||
#define BOARD_LED_RED_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_LED_RED_GPIO_PORT 1U
|
||||
#ifndef BOARD_LED_RED_GPIO_PIN
|
||||
#define BOARD_LED_RED_GPIO_PIN 6U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_BLUE_GPIO
|
||||
#define BOARD_LED_BLUE_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_LED_BLUE_GPIO_PORT 1U
|
||||
#ifndef BOARD_LED_BLUE_GPIO_PIN
|
||||
#define BOARD_LED_BLUE_GPIO_PIN 4U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_LED_GREEN_GPIO
|
||||
#define BOARD_LED_GREEN_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_LED_GREEN_GPIO_PORT 1U
|
||||
#ifndef BOARD_LED_GREEN_GPIO_PIN
|
||||
#define BOARD_LED_GREEN_GPIO_PIN 7U
|
||||
#endif
|
||||
|
||||
#ifndef BOARD_SW1_GPIO
|
||||
#define BOARD_SW1_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_SW1_GPIO_PORT 0U
|
||||
#ifndef BOARD_SW1_GPIO_PIN
|
||||
#define BOARD_SW1_GPIO_PIN 5U
|
||||
#endif
|
||||
#define BOARD_SW1_NAME "SW1"
|
||||
#define BOARD_SW1_IRQ PIN_INT0_IRQn
|
||||
#define BOARD_SW1_IRQ_HANDLER PIN_INT0_IRQHandler
|
||||
|
||||
#ifndef BOARD_SW2_GPIO
|
||||
#define BOARD_SW2_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_SW2_GPIO_PORT 1U
|
||||
#ifndef BOARD_SW2_GPIO_PIN
|
||||
#define BOARD_SW2_GPIO_PIN 18U
|
||||
#endif
|
||||
#define BOARD_SW2_NAME "SW2"
|
||||
#define BOARD_SW2_IRQ PIN_INT1_IRQn
|
||||
#define BOARD_SW2_IRQ_HANDLER PIN_INT1_IRQHandler
|
||||
#define BOARD_SW2_GPIO_PININT_INDEX 1
|
||||
|
||||
#ifndef BOARD_SW3_GPIO
|
||||
#define BOARD_SW3_GPIO GPIO
|
||||
#endif
|
||||
#define BOARD_SW3_GPIO_PORT 1U
|
||||
#ifndef BOARD_SW3_GPIO_PIN
|
||||
#define BOARD_SW3_GPIO_PIN 9U
|
||||
#endif
|
||||
#define BOARD_SW3_NAME "SW3"
|
||||
#define BOARD_SW3_IRQ PIN_INT1_IRQn
|
||||
#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler
|
||||
#define BOARD_SW3_GPIO_PININT_INDEX 1
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x05U)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x0AU)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x0AU)
|
||||
|
||||
/* Board led color mapping */
|
||||
#define LOGIC_LED_ON 0U
|
||||
#define LOGIC_LED_OFF 1U
|
||||
|
||||
#define LED_RED_INIT(output) \
|
||||
{ \
|
||||
IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, IOCON_DIGITAL_EN); \
|
||||
GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
|
||||
}
|
||||
#define LED_RED_ON() \
|
||||
GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
|
||||
1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 */
|
||||
#define LED_RED_OFF() \
|
||||
GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
|
||||
1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 \ \ \ \ \ \ \ \ \ \ \
|
||||
*/
|
||||
#define LED_RED_TOGGLE() \
|
||||
GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \
|
||||
1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */
|
||||
|
||||
#define LED_BLUE_INIT(output) \
|
||||
{ \
|
||||
IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, IOCON_DIGITAL_EN); \
|
||||
GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \
|
||||
}
|
||||
#define LED_BLUE_ON() \
|
||||
GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
|
||||
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */
|
||||
#define LED_BLUE_OFF() \
|
||||
GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
|
||||
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */
|
||||
#define LED_BLUE_TOGGLE() \
|
||||
GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \
|
||||
1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */
|
||||
|
||||
#define LED_GREEN_INIT(output) \
|
||||
GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \
|
||||
&(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
|
||||
#define LED_GREEN_ON() \
|
||||
GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
|
||||
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */
|
||||
#define LED_GREEN_OFF() \
|
||||
GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
|
||||
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */
|
||||
#define LED_GREEN_TOGGLE() \
|
||||
GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \
|
||||
1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */
|
||||
|
||||
/* Display. */
|
||||
#define BOARD_LCD_DC_GPIO GPIO
|
||||
#define BOARD_LCD_DC_GPIO_PORT 1U
|
||||
#define BOARD_LCD_DC_GPIO_PIN 5U
|
||||
|
||||
/* Serial MWM WIFI */
|
||||
#define BOARD_SERIAL_MWM_PORT_CLK_FREQ CLOCK_GetFlexCommClkFreq(2)
|
||||
#define BOARD_SERIAL_MWM_PORT USART2
|
||||
#define BOARD_SERIAL_MWM_PORT_IRQn FLEXCOMM2_IRQn
|
||||
#define BOARD_SERIAL_MWM_RST_WRITE(output)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
void BOARD_InitDebugConsole_Core1(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_I2C_Send(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_I2C_Receive(I2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
@ -1,374 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017-2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to set up clock using clock driver functions:
|
||||
*
|
||||
* 1. Setup clock sources.
|
||||
*
|
||||
* 2. Set up wait states of the flash.
|
||||
*
|
||||
* 3. Set up all dividers.
|
||||
*
|
||||
* 4. Set up all selectors to provide selected clocks.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v7.0
|
||||
processor: LPC55S69
|
||||
package_id: LPC55S69JBD100
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_power.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockPLL150M();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFRO12M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 12 MHz}
|
||||
settings:
|
||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
||||
sources:
|
||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFRO12M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
||||
|
||||
POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF96M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockFROHF96M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 96 MHz}
|
||||
settings:
|
||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
||||
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
|
||||
sources:
|
||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockFROHF96M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockFROHF96M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockFROHF96M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
||||
|
||||
POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL100M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 100 MHz}
|
||||
settings:
|
||||
- {id: PLL0_Mode, value: Normal}
|
||||
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
|
||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
|
||||
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
||||
- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
|
||||
- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
|
||||
- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
|
||||
sources:
|
||||
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
|
||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL100M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
|
||||
|
||||
/*!< Configure XTAL32M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
||||
|
||||
POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up PLL */
|
||||
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
|
||||
const pll_setup_t pll0Setup = {
|
||||
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
|
||||
.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
|
||||
.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
|
||||
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
|
||||
.pllRate = 100000000U,
|
||||
.flags = PLL_SETUPFLAG_WAITLOCK
|
||||
};
|
||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL150M
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 150 MHz}
|
||||
settings:
|
||||
- {id: PLL0_Mode, value: Normal}
|
||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
|
||||
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
||||
- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
|
||||
- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
|
||||
- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
|
||||
sources:
|
||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL150M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
/*!< Configure XTAL32M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
||||
|
||||
POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up PLL */
|
||||
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
|
||||
const pll_setup_t pll0Setup = {
|
||||
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
|
||||
.pllndec = SYSCON_PLL0NDEC_NDIV(8U),
|
||||
.pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
|
||||
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
|
||||
.pllRate = 150000000U,
|
||||
.flags = PLL_SETUPFLAG_WAITLOCK
|
||||
};
|
||||
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockPLL1_150M ********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL1_150M
|
||||
outputs:
|
||||
- {id: System_clock.outFreq, value: 150 MHz}
|
||||
settings:
|
||||
- {id: PLL1_Mode, value: Normal}
|
||||
- {id: ENABLE_CLKIN_ENA, value: Enabled}
|
||||
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
|
||||
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
|
||||
- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
|
||||
- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
|
||||
- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
|
||||
- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
|
||||
sources:
|
||||
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL1_150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL1_150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL1_150M(void)
|
||||
{
|
||||
#ifndef SDK_SECONDARY_CORE
|
||||
/*!< Set up the clock sources */
|
||||
/*!< Configure FRO192M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
|
||||
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
|
||||
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
|
||||
|
||||
/*!< Configure XTAL32M */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
|
||||
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
|
||||
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
|
||||
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
|
||||
|
||||
POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
|
||||
CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
|
||||
|
||||
/*!< Set up PLL1 */
|
||||
CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
|
||||
POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
|
||||
const pll_setup_t pll1Setup = {
|
||||
.pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
|
||||
.pllndec = SYSCON_PLL1NDEC_NDIV(8U),
|
||||
.pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
|
||||
.pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
|
||||
.pllRate = 150000000U,
|
||||
.flags = PLL_SETUPFLAG_WAITLOCK
|
||||
};
|
||||
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
|
||||
|
||||
/*< Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
|
||||
#endif
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue