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Updated to v2.12.1 

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2022-12-08 23:33:41 +08:00
parent f208e9228e
commit ded8674389
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
1600 changed files with 432003 additions and 134818 deletions
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3958
MIMXRT1052xxxxB_manifest_v3_10.xml
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File diff suppressed because it is too large Load Diff

53
SW-Content-Register.txt
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@ -1,5 +1,5 @@
Release Name: MCUXpresso Software Development Kit (SDK)
Release Version: 2.12.0
Release Version: 2.12.1
Package License: LA_OPT_NXP_Software_License.txt v35 May 2022- Additional Distribution License granted, license in Section 2.3 applies
SDK_Peripheral_Driver Name: SDK Peripheral Driver
@ -608,7 +608,7 @@ DeepviewRT Sample Name: DeepviewRT Sample
Url: https://embeddedml.com
maestro Name: Maestro Audio Framework
Version: 1.3.0
Version: 1.4.0
Outgoing License: LA_OPT_NXP_Software_License.txt
v35 May 2022- Additional distribution license
granted - License in Section 2.3 applies
@ -664,6 +664,31 @@ canopen Name: EmSA CANopen (FD) Libraries
Location: middleware/canopen
Origin: EmSA
VIT Name: VIT_v5.6.0
Version: 5.6.0
Outgoing License: LA_OPT_NXP_Software_License.txt
v35 May 2022 - Additional distribution license
granted - License in Section 2.3 applies
License File: LA_OPT_NXP_Software_License.txt
Format: Precompiled libraries, header files,
example application
Description: Voice Intelligent Technology library
Location: middleware/vit
Origin: NXP (Proprietary)
bt_ble_hoststack Name: Bluetooth and Bluetooth Low Energy Host
Stack
Version: 16.5.16
Outgoing License: LA_OPT_NXP_Software_License.txt
v35 May 2022 - Additional distribution license
granted - License in Section 2.3 applies
License File: LA_OPT_NXP_Software_License.txt
Format: Source, Binary libraries
Description: Bluetooth and Bluetooth Low Energy
Host Stack.
Location: middleware/wireless/ethermind
Origin: Mindtree
azure_rtos_threadx Name: Azure RTOS ThreadX
Version: 6.1.10
Outgoing License: LA_OPT_NXP_Software_License.txt
@ -746,6 +771,18 @@ azure_rtos_usbx Name: Azure RTOS USBX
Url:
https://azure.microsoft.com/en-us/services/rtos/
EdgeFast_PAL name: EdgeFast Protocol Abstraction Layer
version: 0.1.0
Outgoing License: BSD-3-Clause
License File: COPYING-BSD-3
Format: source code, header files
Description: EdgeFast Bluetooth PAL
Location: middleware/edgefast_bluetooth
Origin: NXP (BSD-3-Clause) Zephyr BT/BLE Host
stack (Apache-2.0) -
https://github.com/zephyrproject-rtos/zephyr/tree/
v2.6-branch/subsys/bluetooth
freertos_corehttp name: FreeRTOS coreHTTP library
version: 2.0.1
Outgoing License: MIT
@ -770,6 +807,18 @@ MCUBoot Name: MCUBoot
Origin: MCUBoot https://www.mcuboot.com/
Url: https://github.com/mcu-tools/mcuboot
soem Name: Simple Open EtherCAT Master Library (SOEM)
Version: 1.4.0
Outgoing License: GPL-2.0 with a special exception
License File: middleware/soem/LICENSE
Format: source code
Description: An opensource EtherCAT master stack
which is used to write custom EtherCAT Master
applications.
Location: middleware/soem
Origin: RT-Labs
Url: https://github.com/OpenEtherCATsociety/soem
CJSON Name: CJSON
Version: 1.7.4
Outgoing License: MIT

101
boards/evkbimxrt1050/audio_examples/common/att/eap_att.c
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@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -175,22 +175,24 @@ LVM_ControlParams_t ControlParamSet_internal = {
};
// @formatter:on
static eap_att_code_t normalize_params();
static eap_att_code_t set_control_params();
static eap_att_code_t normalize_params(void);
static eap_att_code_t set_control_params(void);
static eap_att_code_t get_control_params(LVM_HeadroomParams_t *headroom, LVM_ControlParams_t *control);
static eap_att_code_t update_wrapper();
static eap_att_code_t update_wrapper(void);
#endif /* EAP_PROC */
static eap_att_code_t play_wrapper();
static eap_att_code_t pause_wrapper();
static eap_att_code_t resume_wrapper();
static eap_att_code_t reset_wrapper();
static eap_att_code_t stop_wrapper();
static eap_att_code_t play_wrapper(void);
static eap_att_code_t pause_wrapper(void);
static eap_att_code_t resume_wrapper(void);
static eap_att_code_t reset_wrapper(void);
static eap_att_code_t stop_wrapper(void);
static eap_att_code_t set_volume_wrapper(int value);
static eap_att_code_t seek_wrapper(int32_t seek_time);
static eap_att_code_t update();
static eap_att_code_t set_volume();
static eap_att_code_t update(void);
static eap_att_code_t set_volume(int value);
static eap_att_code_t seek(int32_t seek_time);
static void progress(int current, int total);
@ -210,8 +212,10 @@ eap_att_control_t att_control = {.attVersion = 4,
.progress = &progress,
.update = &update,
.set_volume = &set_volume,
.seek = &seek,
.logme = printf,
.volume = 75,
.seek_time = 0,
#if (defined EAP_PROC || defined EAP32_PROC)
.controlParam = &ControlParamSet_internal,
@ -221,12 +225,12 @@ eap_att_control_t att_control = {.attVersion = 4,
#endif
};
eap_att_control_t *get_eap_att_control()
eap_att_control_t *get_eap_att_control(void)
{
return &att_control;
}
void eap_att_process()
void eap_att_process(void)
{
#if (defined EAP_PROC || defined EAP32_PROC)
if (attProcessIterator++ == 0)
@ -262,7 +266,7 @@ void eap_att_process()
}
if (att_control.lastError == kEapAttCodeOk)
{
att_control.lastError = play_wrapper(att_control.input);
att_control.lastError = play_wrapper();
}
}
@ -301,6 +305,16 @@ void eap_att_process()
}
break;
}
case kAttCmdSeek:
if (att_control.status != kAttPaused)
{
att_control.logme("[EAP_ATT] First pause the track\r\n");
}
else
{
att_control.lastError = seek_wrapper(att_control.seek_time);
}
break;
#if (defined EAP_PROC || defined EAP32_PROC)
case kAttCmdSetConfig:
{
@ -326,7 +340,14 @@ void eap_att_process()
}
case kAttCmdVolume:
{
att_control.lastError = set_volume_wrapper(att_control.volume);
if (att_control.status == kAttRunning || att_control.status == kAttPaused)
{
att_control.lastError = set_volume_wrapper(att_control.volume);
}
else
{
att_control.logme("[EAP_ATT] First, play an audio file.\r\n");
}
break;
}
default:
@ -357,59 +378,73 @@ static void progress(int current, int total)
}
/* wrap functions by safe invoker */
static eap_att_code_t play_wrapper()
static eap_att_code_t play_wrapper(void)
{
if (att_control.play != 0)
if (att_control.play != NULL)
{
return (*att_control.play)();
}
return kEapAttCodeMissingHandler;
}
static eap_att_code_t pause_wrapper()
static eap_att_code_t pause_wrapper(void)
{
if (att_control.pause != 0)
if (att_control.pause != NULL)
{
return (*att_control.pause)();
}
return kEapAttCodeMissingHandler;
}
static eap_att_code_t resume_wrapper()
static eap_att_code_t resume_wrapper(void)
{
if (att_control.resume != 0)
if (att_control.resume != NULL)
{
return (*att_control.resume)();
}
return kEapAttCodeMissingHandler;
}
static eap_att_code_t reset_wrapper()
static eap_att_code_t reset_wrapper(void)
{
if (att_control.reset != 0)
if (att_control.reset != NULL)
{
return (*att_control.reset)();
}
return kEapAttCodeMissingHandler;
}
static eap_att_code_t stop_wrapper()
static eap_att_code_t stop_wrapper(void)
{
if (att_control.stop != 0)
if (att_control.stop != NULL)
{
return (*att_control.stop)();
}
return kEapAttCodeMissingHandler;
}
static eap_att_code_t update()
static eap_att_code_t seek_wrapper(int32_t seek_time)
{
if (att_control.seek != NULL)
{
return (*att_control.seek)(seek_time);
}
return kEapAttCodeMissingHandler;
}
eap_att_code_t seek(int32_t seek_time)
{
return kEapAttCodeOk; // let implementation on user if needed
}
static eap_att_code_t update(void)
{
return kEapAttCodeOk; // let implementation on user if needed
}
static eap_att_code_t set_volume_wrapper(int volume)
{
if (att_control.set_volume != 0)
if (att_control.set_volume != NULL)
{
return (*att_control.set_volume)(volume);
}
@ -423,9 +458,9 @@ eap_att_code_t set_volume(int value)
#if (defined EAP_PROC || defined EAP32_PROC)
static eap_att_code_t update_wrapper()
static eap_att_code_t update_wrapper(void)
{
if (att_control.update != 0)
if (att_control.update != NULL)
{
return (*att_control.update)();
}
@ -445,7 +480,7 @@ void eap_att_register_handle(LVM_Handle_t *handle)
att_control.handle = handle;
}
static eap_att_code_t normalize_params()
static eap_att_code_t normalize_params(void)
{
LVM_ControlParams_t *cp = att_control.controlParam;
#ifdef ALGORITHM_EQNB
@ -477,9 +512,9 @@ static eap_att_code_t normalize_params()
return kEapAttCodeOk;
}
static eap_att_code_t normalize_params_wrapper()
static eap_att_code_t normalize_params_wrapper(void)
{
if (att_control.normalize_params != 0)
if (att_control.normalize_params != NULL)
{
return (*att_control.normalize_params)();
}
@ -487,7 +522,7 @@ static eap_att_code_t normalize_params_wrapper()
}
/* internal */
static eap_att_code_t set_control_params()
static eap_att_code_t set_control_params(void)
{
int status = LVM_SUCCESS;

30
boards/evkbimxrt1050/audio_examples/common/att/eap_att.h
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@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -50,6 +50,7 @@
#elif defined EAP32_PROC
#include <EAP32.h>
#endif
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
@ -91,7 +92,8 @@ typedef enum _eap_att_command
kAttCmdGetConfig = 5, /*!< load actual EAP parameters from LVM library */
kAttCmdReset = 6, /*!< stops application and starts again with last values
(also critical properties like sampling frequency could be changed by this)*/
kAttCmdVolume = 7 /*!< apply current volume */
kAttCmdVolume = 7, /*!< apply current volume */
kAttCmdSeek = 8 /*!< seek current paused track */
} eap_att_command_t;
/* EAP ATT state machine statuses */
@ -125,24 +127,26 @@ typedef struct _eap_att_control
// preset definition, '0' is reserved for default, used as optional storage or by tests
char eapPreset;
int volume; // volume in range 0-100%, 0 is muted
int volume; // Volume in range 0-100%, 0 is muted
int32_t seek_time; // Seek time
// control handlers
eap_att_code_t (*play)(); /* Register playback start function. */
eap_att_code_t (*pause)(); /* Pause audio stream and save current position. */
eap_att_code_t (*resume)(); /* Continue playback of audio stream which was previously paused. */
eap_att_code_t (*reset)(); /* Optional handler for master reset. (currently used only in tests) */
eap_att_code_t (*stop)(); /* Stop audio stream. This is called i.e. before play() for new audio input. */
eap_att_code_t (*destroy)(); /* Destroy audio stream. Return kEapAttCodeOk if this behavior is not needed. */
eap_att_code_t (*play)(void); /* Register playback start function. */
eap_att_code_t (*pause)(void); /* Pause audio stream and save current position. */
eap_att_code_t (*resume)(void); /* Continue playback of audio stream which was previously paused. */
eap_att_code_t (*reset)(void); /* Optional handler for master reset. (currently used only in tests) */
eap_att_code_t (*stop)(void); /* Stop audio stream. This is called i.e. before play() for new audio input. */
eap_att_code_t (*seek)(int32_t seek_time); /* Seek current paused track. */
eap_att_code_t (*destroy)(void); /* Destroy audio stream. Return kEapAttCodeOk if this behavior is not needed. */
void (*progress)(int current, int total); /* Call periodically on audio stream progress changed. */
eap_att_code_t (*set_volume)(int value); /* Handler for volume control */
// advanced overrides
eap_att_code_t (*update)(); /* This is called when EAP config structures were changed by the tool. */
eap_att_code_t (*update)(void); /* This is called when EAP config structures were changed by the tool. */
int (*logme)(const char *fmt_s, ...); /* This function is mapped to stdio::printf() by default. */
#if (defined EAP_PROC || defined EAP32_PROC)
eap_att_code_t (*normalize_params)(); /* Normalizes params definition structures i.e. bands elements count. */
eap_att_code_t (*normalize_params)(void); /* Normalizes params definition structures i.e. bands elements count. */
// EAP references
LVM_Handle_t handle;
@ -156,14 +160,14 @@ typedef struct _eap_att_control
* This function is main accessor to internal control structure singleton. Please use this where needed.
* @return Returns pointer to ATT control structure singleton.
*/
eap_att_control_t *get_eap_att_control();
eap_att_control_t *get_eap_att_control(void);
/*
* Main EAP ATT state machine process method. Should be called periodically.
* Selected period defines how fast will be reaction on commands from Audio Tuning Tool.
* Recommended period is between 1-100ms (higher values can leeds into too slow reaction).
*/
void eap_att_process();
void eap_att_process(void);
#if (defined EAP_PROC || defined EAP32_PROC)
/*

4
boards/evkbimxrt1050/audio_examples/maestro_playback/FreeRTOSConfig.h
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@ -70,9 +70,9 @@
#define configSUPPORT_STATIC_ALLOCATION 0
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#if (defined(CPU_MIMXRT1051DVL6B) || defined(CPU_MIMXRT1052DVL6B) || defined(CPU_MIMXRT1041XJM5B) || defined(CPU_MIMXRT1042XJM5B))
#define configTOTAL_HEAP_SIZE ((size_t) (252 * 1024))
#define configTOTAL_HEAP_SIZE ((size_t) (255 * 1024))
#elif defined(CPU_LPC55S69JBD100_cm33_core0)
#define configTOTAL_HEAP_SIZE ((size_t) (220 * 1024))
#define configTOTAL_HEAP_SIZE ((size_t) (210 * 1024))
#else
#define configTOTAL_HEAP_SIZE ((size_t) (734 * 1024))
#endif

35
boards/evkbimxrt1050/audio_examples/maestro_playback/app_streamer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2020-2021 NXP
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -23,7 +23,7 @@
#define STREAMER_TASK_NAME "Streamer"
#define STREAMER_MESSAGE_TASK_NAME "StreamerMessage"
#define STREAMER_TASK_STACK_SIZE 16 * 1024
#define STREAMER_TASK_STACK_SIZE 20 * 1024
#define STREAMER_MESSAGE_TASK_STACK_SIZE 1024
static STREAMER_T *streamer;
@ -297,6 +297,36 @@ eap_att_code_t pause()
return kEapAttCodeStreamControlFailure;
}
eap_att_code_t seek(int32_t seek_time)
{
StreamData query1;
if (streamer_query_info(streamer, 0, INFO_DURATION, &query1, true) != 0)
{
return kEapAttCodeStreamControlFailure;
}
if (query1.value32u > 0U)
{
if ((uint32_t)seek_time > query1.value32u)
{
PRINTF(
"[SEEK STREAMER] No seek was performed because the seek time is longer than the duration of the audio "
"track.\r\n");
return kEapAttCodeOk;
}
if (streamer_seek_pipeline(streamer, 0, seek_time, true) == 0)
{
PRINTF("[SEEK STREAMER] The seek audio track to %u milliseconds was performed successfully.\r\n",
seek_time);
return kEapAttCodeOk;
}
}
return kEapAttCodeStreamControlFailure;
}
eap_att_code_t set_volume(int volume)
{
ELEMENT_PROPERTY_T prop;
@ -412,6 +442,7 @@ void STREAMER_Init(void)
att_control->pause = &pause;
att_control->reset = &reset;
att_control->stop = &stop;
att_control->seek = &seek;
att_control->destroy = &destroy;
att_control->resume = &resume;
att_control->set_volume = &set_volume;

8
boards/evkbimxrt1050/audio_examples/maestro_playback/armgcc/flags.cmake
View File

@ -46,10 +46,14 @@ SET(CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG " \
-DPRINTF_ADVANCED_ENABLE=1 \
-DPRINTF_FLOAT_ENABLE=1 \
-DOGG_OPUS_DEC=1 \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DHAVE_CONFIG_H \
-DSERIAL_PORT_TYPE_UART=1 \
@ -107,10 +111,14 @@ SET(CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE " \
-DPRINTF_ADVANCED_ENABLE=1 \
-DPRINTF_FLOAT_ENABLE=1 \
-DOGG_OPUS_DEC=1 \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DHAVE_CONFIG_H \
-DSERIAL_PORT_TYPE_UART=1 \

32
boards/evkbimxrt1050/audio_examples/maestro_playback/cmd.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2019-2021 NXP
* Copyright 2019-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -49,14 +49,16 @@ SHELL_COMMAND_DEFINE(
file,
"\r\n\"file\": Perform audio file decode and playback\r\n"
"\r\n"
" USAGE: file [start|stop|pause|"
" USAGE: file [start|stop|pause|seek|volume|"
#ifdef EAP_PROC
"update|set|get"
"update|set|get|"
#endif
"track|list|info]\r\n"
" start Play default (first found) or specified audio track file.\r\n"
" stop Stops actual playback.\r\n"
" pause Pause actual track or resume if already paused.\r\n"
" seek=<seek_time> Seek currently paused track. Seek time is in milliseconds.\r\n"
" volume=<volume> Set volume. The volume can be set from 0 to 100.\r\n"
#ifdef EAP_PROC
" update=<preset> Apply current EAP parameters without attribute value\r\n"
@ -178,6 +180,19 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
{
get_eap_att_control()->command = kAttCmdPause;
}
else if (strcmp(argv[1], "seek") == 0)
{
if (argc >= 3)
{
get_eap_att_control()->seek_time = abs(atoi((argv[2])));
get_eap_att_control()->command = kAttCmdSeek;
}
else
{
PRINTF("[CMD] Enter seek time value.\r\n");
retVal = kStatus_SHELL_Error;
}
}
#if defined(EAP_PROC) && (ALGORITHM_XO == 1)
else if (strcmp(argv[1], "xo") == 0) // this option is good for testing but could be removed for production
{
@ -221,7 +236,7 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
{
if (argc >= 3)
{
int value = abs(atoi((argv[2])));
int value = atoi((argv[2]));
if (value >= 0 && value <= 100)
{
get_eap_att_control()->volume = value;
@ -268,7 +283,10 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
if (isFileOnSDcard(argv[2]))
{
dot = strrchr(argv[2], '.');
if ((dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
if (
#if (OGG_OPUS_DEC == 1)
(dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
#endif
(dot && strncmp(dot + 1, "mp3", 3) == 0))
{
strcpy(get_eap_att_control()->input, argv[2]);
@ -276,7 +294,11 @@ static shell_status_t shellFile(shell_handle_t shellHandle, int32_t argc, char *
}
else
{
#if (OGG_OPUS_DEC == 1)
PRINTF("Input audio file name has to match one of the .opus|.ogg|.mp3 formats.\r\n");
#else
PRINTF("Input audio file name has to match the .mp3 format.\r\n");
#endif
retVal = kStatus_SHELL_Error;
}
}

41
boards/evkbimxrt1050/audio_examples/maestro_playback/eap_proc.c
View File

@ -136,6 +136,9 @@ static LVM_UINT32 EAP_AudioTime = 0;
// malloc memory
static LVM_INT16 MallocAlign = 4; /* 4 byte Malloc alignment */
#if (ALGORITHM_XO == 1)
static uint16_t eap_xo_out_buf_size = 0U; /* Chunk size for which the xo out buffers are allocated */
#endif
int EAP_Init(void *arg)
{
@ -145,6 +148,15 @@ int EAP_Init(void *arg)
LVM_INT16 j;
LVM_UINT16 order[LVM_NR_MEMORY_REGIONS];
#if (ALGORITHM_XO == 1)
/* Init variables */
eap_xo_out_buf_size = 0U;
for (int o = 0; o < 2; o++)
{
eap_xo_out_buffer[o] = NULL;
}
#endif
/******************************************************************************
GET VERSION INFORMATION
*******************************************************************************/
@ -321,6 +333,11 @@ int EAP_Execute(void *arg, void *inputBuffer, int size)
#if (ALGORITHM_XO == 1)
eap_att_control_t *control = get_eap_att_control();
app_data_t *app_data = get_app_data();
if (size > (int)eap_xo_out_buf_size)
{
first_exec = true;
}
if (first_exec)
{
first_exec = false;
@ -332,8 +349,16 @@ int EAP_Execute(void *arg, void *inputBuffer, int size)
// streamer
app_data->eap_args.xo_enabled = true;
eap_xo_out_buf_size = (uint16_t)size;
for (int i = 0; i < 2; i++)
{
if (eap_xo_out_buffer[i] != NULL)
{
OSA_MemoryFree(eap_xo_out_buffer[i]);
eap_xo_out_buffer[i] = NULL;
}
eap_xo_out_buffer[i] = OSA_MemoryAllocate(size * num_channel);
if (eap_xo_out_buffer[i] != NULL)
{
@ -361,7 +386,7 @@ int EAP_Execute(void *arg, void *inputBuffer, int size)
(LVM_INT16 *)inputBuffer, /* Input buffer */
outBuffer, /* Output buffer */
size / num_channel, /* Number of samples to process */
EAP_AudioTime); /* Audio Time*/
EAP_AudioTime); /* Audio Time */
#if (ALGORITHM_XO == 1)
if (app_data->lastXOOperatingMode)
@ -467,18 +492,19 @@ int EAP_Deinit(void)
/*
* Free memory
*/
LVM_Status = LVM_GetMemoryTable(EAP_hInstance, &EAP_MemTab, LVM_NULL);
if (LVM_Status != LVM_SUCCESS)
{
return LVM_Status;
PRINTF("EAP GetMemoryTable error: %d\r\n", LVM_Status);
}
for (i = 0; i < LVM_NR_MEMORY_REGIONS; i++)
{
if (EAP_MemTab.Region[i].Size != 0)
if (EAP_MemTab.Region[i].pBaseAddress != NULL)
{
temp32 = (LVM_INT32)EAP_MemTab.Region[i].pBaseAddress - MallocAlign;
OSA_MemoryFree((LVM_INT8 *)temp32);
EAP_MemTab.Region[i].pBaseAddress = NULL;
}
}
#if (ALGORITHM_XO == 1)
@ -486,7 +512,12 @@ int EAP_Deinit(void)
{
for (int i = 0; i < 2; i++)
{
OSA_MemoryFree(eap_xo_out_buffer[i]);
if (eap_xo_out_buffer[i] != NULL)
{
OSA_MemoryFree(eap_xo_out_buffer[i]);
eap_xo_out_buffer[i] = NULL;
eap_xo_out_buf_size = 0U;
}
}
}
#endif

4
boards/evkbimxrt1050/audio_examples/maestro_playback/maestro_playback_v3_10.xml
View File

@ -103,10 +103,14 @@
<value>PRINTF_ADVANCED_ENABLE=1</value>
<value>PRINTF_FLOAT_ENABLE=1</value>
<value>OGG_OPUS_DEC=1</value>
<value>DEBUG_CONSOLE_TRANSFER_NON_BLOCKING</value>
<value>OSA_USED</value>
<value>SHELL_TASK_STACK_SIZE=4000</value>
<value>SDK_I2C_BASED_COMPONENT_USED=1</value>
<value>BOARD_USE_CODEC=1</value>
<value>CODEC_WM8960_ENABLE</value>
<value>SD_ENABLED</value>
<value>SAI_XFER_QUEUE_SIZE=2</value>
<value>DEBUG_CONSOLE_RX_ENABLE=0</value>
<value>HAVE_CONFIG_H</value>
<value>SERIAL_PORT_TYPE_UART=1</value>

14
boards/evkbimxrt1050/audio_examples/maestro_playback/main.c
View File

@ -27,9 +27,9 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#define SHELL_TASK_STACK_SIZE (512)
#define SDCARD_TASK_STACK_SIZE (512)
#define APP_TASK_STACK_SIZE (512)
#define APP_SHELL_TASK_STACK_SIZE (512)
#define SDCARD_TASK_STACK_SIZE (512)
#define APP_TASK_STACK_SIZE (512)
/*******************************************************************************
* Prototypes
@ -157,7 +157,10 @@ status_t list_files(bool autoInput)
{
/* Check file for supported audio extension */
dot = strrchr(fileInformation.fname, '.');
if ((dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
if (
#if (OGG_OPUS_DEC == 1)
(dot && strncmp(dot + 1, "opus", 4) == 0) || (dot && strncmp(dot + 1, "ogg", 3) == 0) ||
#endif
(dot && strncmp(dot + 1, "mp3", 3) == 0))
{
if (count < MAX_FILES_LIST)
@ -260,7 +263,6 @@ void APP_Shell_Task(void *param)
/* Handle shell commands. */
shellCmd();
vTaskSuspend(NULL);
while (1)
;
}
@ -328,7 +330,7 @@ int main(void)
;
}
if (xTaskCreate(APP_Shell_Task, "Shell Task", SHELL_TASK_STACK_SIZE, &app, configMAX_PRIORITIES - 4,
if (xTaskCreate(APP_Shell_Task, "Shell Task", APP_SHELL_TASK_STACK_SIZE, &app, configMAX_PRIORITIES - 4,
&app.shell_task_handle) != pdPASS)
{
PRINTF("\r\nFailed to create Shell observer task. Please, fix issue and restart board.\r\n");

24
boards/evkbimxrt1050/audio_examples/maestro_playback/streamer_pcm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2018-2021 NXP
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -111,19 +111,15 @@ int streamer_pcm_write(pcm_rtos_t *pcm, uint8_t *data, uint32_t size)
DCACHE_CleanByRange((uint32_t)pcm->saiTx.data, pcm->saiTx.dataSize);
if (pcm->isFirstTx)
{
pcm->isFirstTx = 0;
}
else
{
/* Wait for the previous transfer to finish */
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
return -1;
}
/* Start the consecutive transfer */
SAI_TransferSendEDMA(DEMO_SAI, &pcm->saiTxHandle, &pcm->saiTx);
while (SAI_TransferSendEDMA(DEMO_SAI, &pcm->saiTxHandle, &pcm->saiTx) == kStatus_SAI_QueueFull)
{
/* Wait for transfer to finish */
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
{
return -1;
}
}
return 0;
}
@ -199,7 +195,6 @@ int streamer_pcm_setparams(pcm_rtos_t *pcm,
sai_transceiver_t saiConfig;
uint32_t masterClockHz = 0U;
pcm->isFirstTx = transfer ? 1U : pcm->isFirstTx;
pcm->sample_rate = sample_rate;
pcm->bit_width = bit_width;
pcm->num_channels = num_channels;
@ -215,6 +210,7 @@ int streamer_pcm_setparams(pcm_rtos_t *pcm,
format.masterClockHz = masterClockHz;
#endif
SAI_TransferTerminateSendEDMA(DEMO_SAI, &pcm->saiTxHandle);
SAI_GetClassicI2SConfig(&saiConfig, _pcm_map_word_width(bit_width), format.stereo, 1U << DEMO_SAI_CHANNEL);
saiConfig.syncMode = kSAI_ModeAsync;
saiConfig.masterSlave = kSAI_Master;

10
boards/evkbimxrt1050/audio_examples/maestro_playback/streamer_pcm_app.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -27,20 +27,12 @@ struct _pcm_rtos_t
sai_edma_handle_t saiTxHandle;
edma_handle_t dmaTxHandle;
sai_transfer_t saiRx;
sai_edma_handle_t saiRxHandle;
edma_handle_t dmaRxHandle;
uint32_t sample_rate;
uint32_t bit_width;
uint8_t num_channels;
SemaphoreHandle_t semaphoreRX;
SemaphoreHandle_t semaphoreTX;
uint8_t isFirstRx;
uint8_t isFirstTx;
bool dummy_tx_enable;
};

182
boards/evkbimxrt1050/audio_examples/maestro_record/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,182 @@
/*
* FreeRTOS Kernel V10.4.3
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Ensure stdint is only used by the compiler, and not the assembler. */
#if defined( __ICCARM__ ) || defined( __ARMCC_VERSION ) || defined( __GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
extern int DbgConsole_Printf( const char *fmt_s, ... );
extern void vLoggingPrintf( const char *pcFormat, ... );
#endif
#define configUSE_PREEMPTION 1
#define configUSE_TICKLESS_IDLE 0
#define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES 7
#define configMINIMAL_STACK_SIZE ((unsigned short)90)
#define configMAX_TASK_NAME_LEN 20
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configUSE_QUEUE_SETS 0
#define configUSE_NEWLIB_REENTRANT 0
#define configENABLE_BACKWARD_COMPATIBILITY 0
#define configUSE_APPLICATION_TASK_TAG 0
/* Memory allocation related definitions. */
#define configSUPPORT_STATIC_ALLOCATION 0
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#if ((defined(CPU_MIMXRT1051DVL6B) || defined(CPU_MIMXRT1052DVL6B) || defined(CPU_MIMXRT1041XJM5B) || defined(CPU_MIMXRT1042XJM5B)) && defined(VIT_PROC))
#define configTOTAL_HEAP_SIZE ((size_t) (478 * 1024))
#elif ((defined(CPU_MIMXRT1051DVL6B) || defined(CPU_MIMXRT1052DVL6B) || defined(CPU_MIMXRT1041XJM5B) || defined(CPU_MIMXRT1042XJM5B)) && !defined(VIT_PROC))
#define configTOTAL_HEAP_SIZE ((size_t) (252 * 1024))
#elif defined(CPU_LPC55S69JBD100_cm33_core0)
#define configTOTAL_HEAP_SIZE ((size_t) (220 * 1024))
#else
#define configTOTAL_HEAP_SIZE ((size_t) (734 * 1024))
#endif
#define configAPPLICATION_ALLOCATED_HEAP 0
#define configCHECK_FOR_STACK_OVERFLOW 1
#define configRECORD_STACK_HIGH_ADDRESS 1
/* Hook function related definitions. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
/* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
#define configUSE_TRACE_FACILITY 0
/* Co-routine related definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 2
/* Software timer related definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 3)
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 4)
/* Define to trap errors during development. */
#define configASSERT(x) if((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
/* Optional functions - most linkers will remove unused functions anyway. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_eTaskGetState 0
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_xTaskAbortDelay 0
#define INCLUDE_xTaskGetHandle 0
/* Demo specific macros that allow the application writer to insert code to be
* executed immediately before the MCU's STOP low power mode is entered and exited
* respectively. These macros are in addition to the standard
* configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros, which are
* called pre and post the low power SLEEP mode being entered and exited. These
* macros can be used to turn turn off and on IO, clocks, the Flash etc. to obtain
* the lowest power possible while the tick is off. */
#if defined( __ICCARM__ ) || defined( __CC_ARM ) || defined( __GNUC__ )
void vMainPreStopProcessing( void );
void vMainPostStopProcessing( void );
#endif /* defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) */
#define configPRE_STOP_PROCESSING vMainPreStopProcessing
#define configPOST_STOP_PROCESSING vMainPostStopProcessing
#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
/* Clock manager provides in this variable system core clock frequency */
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
/* Interrupt nesting behaviour configuration. Cortex-M specific. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#endif /* FREERTOS_CONFIG_H */

65
boards/evkbimxrt1050/audio_examples/maestro_record/app_definitions.h Normal file
View File

@ -0,0 +1,65 @@
/*
* Copyright 2021 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _APP_DEFINITIONS_H_
#define _APP_DEFINITIONS_H_
/*${header:start}*/
#include "fsl_wm8960.h"
/*${header:end}*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*${macro:start}*/
/* SAI instance and clock */
#define DEMO_CODEC_WM8960
#define DEMO_SAI SAI1
#define DEMO_SAI_CHANNEL (0)
#define DEMO_SAI_BITWIDTH (kSAI_WordWidth16bits)
#define DEMO_SAI_IRQ SAI1_IRQn
#define SAI_UserIRQHandler SAI1_IRQHandler
#define DEMO_CHANNEL_NUM 2
#define DEMO_CODEC_CHANNEL kCODEC_PlayChannelHeadphoneLeft | kCODEC_PlayChannelHeadphoneRight
/* IRQ */
#define DEMO_SAI_TX_IRQ SAI1_IRQn
#define DEMO_SAI_RX_IRQ SAI1_IRQn
/* DMA */
#define DEMO_DMA DMA0
#define DEMO_DMAMUX DMAMUX
#define DEMO_TX_CHANNEL (0U)
#define DEMO_RX_CHANNEL (1U)
#define DEMO_SAI_TX_SOURCE kDmaRequestMuxSai1Tx
#define DEMO_SAI_RX_SOURCE kDmaRequestMuxSai1Rx
/* Select Audio/Video PLL (786.48 MHz) as sai1 clock source */
#define DEMO_SAI1_CLOCK_SOURCE_SELECT (2U)
/* Clock pre divider for sai1 clock source */
#define DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER (0U)
/* Clock divider for sai1 clock source */
#define DEMO_SAI1_CLOCK_SOURCE_DIVIDER (63U)
/* Get frequency of sai1 clock */
#define DEMO_SAI_CLK_FREQ \
(CLOCK_GetFreq(kCLOCK_AudioPllClk) / (DEMO_SAI1_CLOCK_SOURCE_DIVIDER + 1U) / \
(DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER + 1U))
/* I2C instance and clock */
#define DEMO_I2C LPI2C1
/* Select USB1 PLL (480 MHz) as master lpi2c clock source */
#define DEMO_LPI2C_CLOCK_SOURCE_SELECT (0U)
/* Clock divider for master lpi2c clock source */
#define DEMO_LPI2C_CLOCK_SOURCE_DIVIDER (5U)
/* Get frequency of lpi2c clock */
#define DEMO_I2C_CLK_FREQ ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (DEMO_LPI2C_CLOCK_SOURCE_DIVIDER + 1U))
#define DEMO_VOLUME (75)
/*${macro:end}*/
#endif /* _APP_DEFINITIONS_H_ */

447
boards/evkbimxrt1050/audio_examples/maestro_record/app_streamer.c Normal file
View File

@ -0,0 +1,447 @@
/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_debug_console.h"
#include "app_streamer.h"
#include "streamer_pcm_app.h"
#include "logging.h"
#ifdef VIT_PROC
#include "vit_proc.h"
#endif
#include "app_definitions.h"
#define APP_STREAMER_MSG_QUEUE "app_queue"
#define STREAMER_TASK_NAME "Streamer"
#define STREAMER_MESSAGE_TASK_NAME "StreamerMessage"
#ifdef OPUS_ENCODE
/* The STREAMER_OPUS_TASK_STACK_SIZE value is different for the IAR because the IAR allocates memory for VLA (variable
* length array - used in the opus encoder) in the application heap and the opus task stack would be largely unused.
*/
#if defined(__ICCARM__)
#define STREAMER_OPUS_TASK_STACK_SIZE 5 * 1024
#else
#define STREAMER_OPUS_TASK_STACK_SIZE 30 * 1024
#endif
#endif
#define STREAMER_TASK_STACK_SIZE 16 * 1024
#define STREAMER_MESSAGE_TASK_STACK_SIZE 1024
#define MAX_FILE_NAME_LENGTH 100
ringbuf_t *audioBuffer;
OSA_MUTEX_HANDLE_DEFINE(audioMutex);
OSA_TASK_HANDLE_DEFINE(msg_thread);
/*!
* @brief Streamer task for communicating messages
*
* This function is the entry point of a task that is manually created by
* STREAMER_Create. It listens on a message queue and receives status updates
* about errors, audio playback state and position. The application can make
* use of this data.
*
* @param arg Data to be passed to the task
*/
static void STREAMER_MessageTask(void *arg)
{
STREAMER_MSG_T msg;
streamer_handle_t *handle;
bool exit_thread = false;
osa_status_t ret;
handle = (streamer_handle_t *)arg;
while (!handle->streamer->mq_out)
{
OSA_TimeDelay(1);
}
if (handle->streamer->mq_out == NULL)
{
PRINTF("[STREAMER] osa_mq_open failed: %d\r\n");
return;
}
PRINTF("[STREAMER] Message Task started\r\n");
do
{
ret = OSA_MsgQGet(&handle->streamer->mq_out, (void *)&msg, osaWaitForever_c);
if (ret != KOSA_StatusSuccess)
{
PRINTF("OSA_MsgQGet error: %d\r\n", ret);
continue;
}
switch (msg.id)
{
case STREAM_MSG_ERROR:
PRINTF("STREAM_MSG_ERROR\r\n");
exit_thread = true;
STREAMER_Stop(handle);
break;
case STREAM_MSG_EOS:
PRINTF("\nSTREAM_MSG_EOS\r\n");
exit_thread = true;
/* Indicate to other software layers that playing has ended. */
STREAMER_Stop(handle);
break;
case STREAM_MSG_UPDATE_POSITION:
PRINTF("STREAM_MSG_UPDATE_POSITION..");
PRINTF(" position: %d ms\r", msg.event_data);
break;
case STREAM_MSG_CLOSE_TASK:
PRINTF("STREAM_MSG_CLOSE_TASK\r\n");
exit_thread = true;
break;
default:
break;
}
} while (!exit_thread);
OSA_MsgQDestroy(&handle->streamer->mq_out);
handle->streamer->mq_out = NULL;
OSA_TaskDestroy(msg_thread);
}
int STREAMER_Read(uint8_t *data, uint32_t size)
{
uint32_t bytes_read;
OSA_MutexLock(&audioMutex, osaWaitForever_c);
bytes_read = ringbuf_read(audioBuffer, data, size);
OSA_MutexUnlock(&audioMutex);
if (bytes_read != size)
{
PRINTF("[STREAMER WARN] read underrun: size: %d, read: %d\r\n", size, bytes_read);
}
return bytes_read;
}
int STREAMER_Write(uint8_t *data, uint32_t size)
{
uint32_t written;
OSA_MutexLock(&audioMutex, osaWaitForever_c);
written = ringbuf_write(audioBuffer, data, size);
OSA_MutexUnlock(&audioMutex);
if (written != size)
{
PRINTF("[STREAMER ERR] write overflow: size %d, written %d\r\n", size, written);
}
return written;
}
bool STREAMER_IsPlaying(streamer_handle_t *handle)
{
return handle->audioPlaying;
}
void STREAMER_Start(streamer_handle_t *handle)
{
PRINTF("[STREAMER] start \r\n");
handle->audioPlaying = true;
streamer_set_state(handle->streamer, 0, STATE_PLAYING, true);
}
void STREAMER_Stop(streamer_handle_t *handle)
{
PRINTF("[STREAMER] stop \r\n");
handle->audioPlaying = false;
streamer_set_state(handle->streamer, 0, STATE_NULL, true);
/* Empty input ringbuffer. */
if (audioBuffer)
{
ringbuf_clear(audioBuffer);
}
}
status_t STREAMER_Create(streamer_handle_t *handle)
{
STREAMER_CREATE_PARAM params;
ELEMENT_PROPERTY_T prop;
osa_task_def_t thread_attr;
int ret;
OSA_MutexCreate(&audioMutex);
audioBuffer = ringbuf_create(AUDIO_BUFFER_SIZE);
if (!audioBuffer)
{
return kStatus_Fail;
}
/* Create message process thread */
thread_attr.tpriority = OSA_PRIORITY_NORMAL;
thread_attr.tname = (uint8_t *)STREAMER_MESSAGE_TASK_NAME;
thread_attr.pthread = &STREAMER_MessageTask;
thread_attr.stacksize = STREAMER_MESSAGE_TASK_STACK_SIZE;
ret = OSA_TaskCreate(&msg_thread, &thread_attr, (void *)handle);
if (KOSA_StatusSuccess != ret)
{
return kStatus_Fail;
}
/* Create streamer */
strcpy(params.out_mq_name, APP_STREAMER_MSG_QUEUE);
params.stack_size = STREAMER_TASK_STACK_SIZE;
params.pipeline_type = STREAM_PIPELINE_NETBUF;
params.task_name = STREAMER_TASK_NAME;
params.in_dev_name = "";
params.out_dev_name = "";
handle->streamer = streamer_create(&params);
if (!handle->streamer)
{
return kStatus_Fail;
}
prop.prop = PROP_NETBUFSRC_SET_CALLBACK;
prop.val = (uintptr_t)STREAMER_Read;
streamer_set_property(handle->streamer, prop, true);
prop.prop = PROP_DECODER_DECODER_TYPE;
prop.val = DECODER_TYPE_MP3;
streamer_set_property(handle->streamer, prop, true);
handle->audioPlaying = false;
return kStatus_Success;
}
status_t STREAMER_mic_Create(streamer_handle_t *handle, out_sink_t out_sink, char *file_name)
{
STREAMER_CREATE_PARAM params;
osa_task_def_t thread_attr;
ELEMENT_PROPERTY_T prop;
int ret;
/* Create streamer */
strcpy(params.out_mq_name, APP_STREAMER_MSG_QUEUE);
params.stack_size = STREAMER_TASK_STACK_SIZE;
switch (out_sink)
{
case AUDIO_SINK:
params.pipeline_type = STREAM_PIPELINE_PCM;
params.out_dev_name = "";
break;
case FILE_SINK:
params.pipeline_type = STREAM_PIPELINE_MIC2FILE;
params.out_dev_name = "file";
break;
case VIT_SINK:
params.pipeline_type = STREAM_PIPELINE_VIT;
params.out_dev_name = "";
break;
default:
PRINTF("[STREAMER ERR] wrong type of sink\r\n");
return kStatus_InvalidArgument;
}
params.task_name = STREAMER_TASK_NAME;
params.in_dev_name = "microphone";
handle->streamer = streamer_create(&params);
if (!handle->streamer)
{
return kStatus_Fail;
}
/* Create message process thread */
thread_attr.tpriority = OSA_PRIORITY_HIGH;
thread_attr.tname = (uint8_t *)STREAMER_MESSAGE_TASK_NAME;
thread_attr.pthread = &STREAMER_MessageTask;
thread_attr.stacksize = STREAMER_MESSAGE_TASK_STACK_SIZE;
ret = OSA_TaskCreate(&msg_thread, &thread_attr, (void *)handle);
if (KOSA_StatusSuccess != ret)
{
return kStatus_Fail;
}
#ifdef VIT_PROC
if (params.pipeline_type == STREAM_PIPELINE_VIT)
{
EXT_PROCESS_DESC_T vit_proc = {VIT_Initialize_func, VIT_Execute_func, VIT_Deinit_func, &Vit_Language};
prop.prop = PROP_VITSINK_FPOINT;
prop.val = (uintptr_t)&vit_proc;
streamer_set_property(handle->streamer, prop, true);
}
#else
if (params.pipeline_type == STREAM_PIPELINE_VIT)
{
PRINTF("[STREAMER] VIT pipeline not available for this config\r\n switching to audio sink");
params.pipeline_type = STREAM_PIPELINE_PCM;
}
#endif
prop.prop = PROP_AUDIOSRC_SET_SAMPLE_RATE;
prop.val = 16000;
streamer_set_property(handle->streamer, prop, true);
#if (defined(PLATFORM_RT1170) || defined(PLATFORM_RT1160))
prop.prop = PROP_AUDIOSRC_SET_BITS_PER_SAMPLE;
prop.val = 32;
streamer_set_property(handle->streamer, prop, true);
#endif
#if DEMO_CODEC_CS42448
prop.prop = PROP_AUDIOSRC_SET_NUM_CHANNELS;
prop.val = 8;
streamer_set_property(handle->streamer, prop, true);
prop.prop = PROP_AUDIOSRC_SET_BITS_PER_SAMPLE;
prop.val = 32;
streamer_set_property(handle->streamer, prop, true);
#endif
if (out_sink == FILE_SINK)
{
char file_name_val[MAX_FILE_NAME_LENGTH];
memcpy(file_name_val, file_name == NULL ? "tmp" : file_name, MAX_FILE_NAME_LENGTH);
strcat(file_name_val, ".pcm");
prop.prop = PROP_FILESINK_LOCATION;
prop.val = (uintptr_t)file_name_val;
streamer_set_property(handle->streamer, prop, true);
}
return kStatus_Success;
}
#ifdef OPUS_ENCODE
status_t STREAMER_opusmem2mem_Create(streamer_handle_t *handle,
CeiBitstreamInfo *info,
MEMSRC_SET_BUFFER_T *inBuf,
SET_BUFFER_DESC_T *outBuf)
{
STREAMER_CREATE_PARAM params;
osa_task_def_t thread_attr;
ELEMENT_PROPERTY_T prop;
int ret;
/* Create streamer */
strcpy(params.out_mq_name, APP_STREAMER_MSG_QUEUE);
params.stack_size = STREAMER_OPUS_TASK_STACK_SIZE;
params.pipeline_type = STREAM_PIPELINE_OPUS_MEM2MEM;
params.task_name = STREAMER_TASK_NAME;
params.in_dev_name = "";
params.out_dev_name = "";
handle->streamer = streamer_create(&params);
if (!handle->streamer)
{
return kStatus_Fail;
}
/* Create message process thread */
thread_attr.tpriority = OSA_PRIORITY_HIGH;
thread_attr.tname = (uint8_t *)STREAMER_MESSAGE_TASK_NAME;
thread_attr.pthread = &STREAMER_MessageTask;
thread_attr.stacksize = STREAMER_MESSAGE_TASK_STACK_SIZE;
ret = OSA_TaskCreate(&msg_thread, &thread_attr, (void *)handle);
if (KOSA_StatusSuccess != ret)
{
return kStatus_Fail;
}
prop.prop = PROP_MEMSRC_SET_BUFF;
prop.val = (uintptr_t)inBuf;
ret = streamer_set_property(handle->streamer, prop, true);
if (ret != STREAM_OK)
{
streamer_destroy(handle->streamer);
handle->streamer = NULL;
return kStatus_Fail;
}
prop.prop = PROP_MEMSINK_BUFFER_DESC;
prop.val = (uintptr_t)outBuf;
ret = streamer_set_property(handle->streamer, prop, true);
if (ret != STREAM_OK)
{
streamer_destroy(handle->streamer);
handle->streamer = NULL;
return kStatus_Fail;
}
prop.prop = PROP_ENCODER_TYPE;
prop.val = (uintptr_t)CEIENC_OPUS;
ret = streamer_set_property(handle->streamer, prop, true);
if (ret != STREAM_OK)
{
streamer_destroy(handle->streamer);
handle->streamer = NULL;
return kStatus_Fail;
}
prop.prop = PROP_ENCODER_BITSTREAMINFO;
prop.val = (uintptr_t)info;
ret = streamer_set_property(handle->streamer, prop, true);
if (ret != STREAM_OK)
{
streamer_destroy(handle->streamer);
handle->streamer = NULL;
return kStatus_Fail;
}
return kStatus_Success;
}
#endif
void STREAMER_Destroy(streamer_handle_t *handle)
{
streamer_destroy(handle->streamer);
handle->streamer = NULL;
if (audioBuffer != NULL)
{
ringbuf_destroy(audioBuffer);
audioBuffer = NULL;
}
deinit_logging();
}
void STREAMER_Init(void)
{
/* Initialize logging */
init_logging();
/* Uncomment below to turn on full debug logging for the streamer. */
// set_debug_module(0xffffffff);
// set_debug_level(LOGLVL_DEBUG);
// get_debug_state();
/* Initialize streamer PCM management library. */
streamer_pcm_init();
}

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/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _APP_STREAMER_H_
#define _APP_STREAMER_H_
/* streamer library includes. */
#include "streamer_api.h"
#include "streamer_element_properties.h"
#ifdef OPUS_ENCODE
#include "opus.h"
#endif
#include "ringbuffer.h"
#include "cei.h"
#include "cei_enctypes.h"
#ifdef VIT_PROC
#include "vit_proc.h"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Maestro network audio buffer size */
#define AUDIO_BUFFER_SIZE (30 * 1024)
/*! @brief Maestro Streamer interface structure */
typedef struct _streamer_handle_t
{
STREAMER_T *streamer;
volatile bool audioPlaying;
} streamer_handle_t;
typedef enum
{
AUDIO_SINK,
FILE_SINK,
VIT_SINK
} out_sink_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Initialize the Maestro streamer interface
*
* This function initializes the Maestro streamer library, and initializes the PCM
* output interface. This function should be called before creating a streamer
* handle.
*/
void STREAMER_Init(void);
/*!
* @brief Create a Maestro streamer interface handle
*
* This function creates a Maestro streamer interface and starts a task for
* handling media playback, and a task for sending status and error messages
* back to the application.
*
* @param handle Pointer to input handle
* @return kStatus_Success on success, otherwise an error.
*/
status_t STREAMER_Create(streamer_handle_t *handle);
/*!
* @brief Create a Maestro streamer interface handle
*
* This function creates a Maestro streamer interface and starts a task for
* handling mic
*
* @param handle Pointer to input handle
* @param out sink type
* @param file_name The specified file name for saving samples. If not used, use NULL.
* @return kStatus_Success on success, otherwise an error.
*/
status_t STREAMER_mic_Create(streamer_handle_t *handle, out_sink_t out_sink, char *file_name);
#ifdef OPUS_ENCODE
status_t STREAMER_opusmem2mem_Create(streamer_handle_t *handle,
CeiBitstreamInfo *info,
MEMSRC_SET_BUFFER_T *inBuf,
SET_BUFFER_DESC_T *outBuf);
#endif
/*!
* @brief Destroy an Maestro streamer interface handle
*
* This function destroys an Maestro streamer interface and frees associated memory.
*
* @param handle Pointer to input handle
*/
void STREAMER_Destroy(streamer_handle_t *handle);
/*!
* @brief Start audio playback for the streamer interface
*
* This function puts the streamer in a playing state, and begins pulling data
* from the internal ring buffer, filled with calls to STREAMER_Start.
*
* @param handle Pointer to input handle
*/
void STREAMER_Start(streamer_handle_t *handle);
/*!
* @brief Stop audio playback for the streamer interface
*
* This function puts the streamer in a stopped state, and ends playback from
* the audio buffer. The internal audio buffer is cleared of any data.
*
* @param handle Pointer to input handle
*/
void STREAMER_Stop(streamer_handle_t *handle);
/*!
* @brief Check if streamer interface is playing
*
* This function returns true/false of the playing state for the interface
*
* @param handle Pointer to input handle
* @return true if playing, false if not
*/
bool STREAMER_IsPlaying(streamer_handle_t *handle);
/*!
* @brief Write audio data to the streamer interface
*
* This function pushes data onto the internal audio ring buffer for processing
* by the audio streamer.
*
* @param data Pointer to audio data
* @param size Size in bytes of the audio data
* @return Number of bytes successfully written. If this is less than the
* 'size' parameter, an overflow has occured.
*/
int STREAMER_Write(uint8_t *data, uint32_t size);
/*!
* @brief Read audio data from the internal audio ring buffer
*
* This function is called internally by the streamer (passed as a callback
* function) to consume and process data from the ring buffer.
*
* @param data Pointer to buffer to copy audio data into
* @param size Size in bytes of the buffer to fill
* @return Number of bytes successfully read. If this is less than the
* 'size' parameter, an underflow has occured.
*/
int STREAMER_Read(uint8_t *data, uint32_t size);
#if defined(__cplusplus)
}
#endif
#endif

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# CROSS COMPILER SETTING
SET(CMAKE_SYSTEM_NAME Generic)
CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
# THE VERSION NUMBER
SET (Tutorial_VERSION_MAJOR 1)
SET (Tutorial_VERSION_MINOR 0)
# ENABLE ASM
ENABLE_LANGUAGE(ASM)
SET(CMAKE_STATIC_LIBRARY_PREFIX)
SET(CMAKE_STATIC_LIBRARY_SUFFIX)
SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
# CURRENT DIRECTORY
SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
project(maestro_record)
set(MCUX_SDK_PROJECT_NAME maestro_record.elf)
include(${ProjDirPath}/flags.cmake)
include(${ProjDirPath}/config.cmake)
add_executable(${MCUX_SDK_PROJECT_NAME}
"${ProjDirPath}/../opusmem2mem_file.h"
"${ProjDirPath}/../app_streamer.c"
"${ProjDirPath}/../app_streamer.h"
"${ProjDirPath}/../cmd.c"
"${ProjDirPath}/../cmd.h"
"${ProjDirPath}/../main.c"
"${ProjDirPath}/../main.h"
"${ProjDirPath}/../pin_mux.c"
"${ProjDirPath}/../pin_mux.h"
"${ProjDirPath}/../FreeRTOSConfig.h"
"${ProjDirPath}/../ffconf.h"
"${ProjDirPath}/../streamer_pcm.c"
"${ProjDirPath}/../streamer_pcm_app.h"
"${ProjDirPath}/../sdmmc_config.c"
"${ProjDirPath}/../sdmmc_config.h"
"${ProjDirPath}/../app_definitions.h"
"${ProjDirPath}/../board.c"
"${ProjDirPath}/../board.h"
"${ProjDirPath}/../clock_config.c"
"${ProjDirPath}/../clock_config.h"
"${ProjDirPath}/../dcd.c"
"${ProjDirPath}/../dcd.h"
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${ProjDirPath}/..
${ProjDirPath}/../../..
)
set(CMAKE_MODULE_PATH
${ProjDirPath}/../../../../../devices/MIMXRT1052/drivers
${ProjDirPath}/../../../../../components/codec/wm8960
${ProjDirPath}/../../../../../components/codec
${ProjDirPath}/../../../../../components/codec/i2c
${ProjDirPath}/../../../../../components/i2c
${ProjDirPath}/../../../../../middleware/sdmmc
${ProjDirPath}/../../../../../middleware/vit
${ProjDirPath}/../../../../../CMSIS/DSP
${ProjDirPath}/../../../../../components/gpio
${ProjDirPath}/../../../../../rtos/freertos/freertos_kernel
${ProjDirPath}/../../../../../middleware/maestro
${ProjDirPath}/../../../../../devices/MIMXRT1052/utilities
${ProjDirPath}/../../../../../middleware/fatfs
${ProjDirPath}/../../../../../middleware/maestro/mcu-audio/opus
${ProjDirPath}/../../../../../devices/MIMXRT1052
${ProjDirPath}/../../../../../components/uart
${ProjDirPath}/../../../../../components/serial_manager
${ProjDirPath}/../../../../../components/lists
${ProjDirPath}/../../../../../devices/MIMXRT1052/xip
${ProjDirPath}/../../../xip
${ProjDirPath}/../../../../../components/silicon_id
${ProjDirPath}/../../../../../CMSIS/Core/Include
${ProjDirPath}/../../../../../components/osa
${ProjDirPath}/../../../../../middleware/maestro/streamer
)
# include modules
include(driver_lpi2c_MIMXRT1052)
include(driver_sai_MIMXRT1052)
include(driver_wm8960_MIMXRT1052)
include(driver_codec_MIMXRT1052)
include(driver_common_MIMXRT1052)
include(component_wm8960_adapter_MIMXRT1052)
include(component_codec_i2c_MIMXRT1052)
include(component_lpi2c_adapter_MIMXRT1052)
include(driver_sai_edma_MIMXRT1052)
include(driver_dmamux_MIMXRT1052)
include(driver_edma_MIMXRT1052)
include(middleware_sdmmc_sd_MIMXRT1052)
include(middleware_sdmmc_common_MIMXRT1052)
include(middleware_sdmmc_host_usdhc_MIMXRT1052)
include(middleware_sdmmc_host_usdhc_freertos_MIMXRT1052)
include(driver_cache_armv7_m7_MIMXRT1052)
include(middleware_vit_cm7_RT105x_MIMXRT1052)
include(CMSIS_DSP_Source_MIMXRT1052)
include(driver_flexram_MIMXRT1052)
include(component_igpio_adapter_MIMXRT1052)
include(middleware_freertos-kernel_heap_4_MIMXRT1052)
include(middleware_maestro_framework_MIMXRT1052)
include(utility_shell_MIMXRT1052)
include(middleware_fatfs_MIMXRT1052)
include(middleware_fatfs_sd_MIMXRT1052)
include(middleware_maestro_framework_opus_MIMXRT1052)
include(driver_clock_MIMXRT1052)
include(device_MIMXRT1052_CMSIS_MIMXRT1052)
include(utility_debug_console_MIMXRT1052)
include(component_lpuart_adapter_MIMXRT1052)
include(component_serial_manager_MIMXRT1052)
include(component_lists_MIMXRT1052)
include(component_serial_manager_uart_MIMXRT1052)
include(driver_lpuart_MIMXRT1052)
include(device_MIMXRT1052_startup_MIMXRT1052)
include(driver_iomuxc_MIMXRT1052)
include(utility_assert_MIMXRT1052)
include(driver_igpio_MIMXRT1052)
include(driver_xip_device_MIMXRT1052)
include(driver_xip_board_evkbimxrt1050_MIMXRT1052)
include(component_silicon_id_MIMXRT1052)
include(CMSIS_Include_core_cm_MIMXRT1052)
include(middleware_sdmmc_osa_freertos_MIMXRT1052)
include(component_osa_free_rtos_MIMXRT1052)
include(middleware_freertos-kernel_MIMXRT1052)
include(middleware_freertos-kernel_extension_MIMXRT1052)
include(driver_usdhc_MIMXRT1052)
include(driver_soc_flexram_allocate_MIMXRT1052)
include(middleware_maestro_framework_doc_MIMXRT1052)
include(middleware_maestro_framework_streamer_MIMXRT1052)
include(utilities_misc_utilities_MIMXRT1052)
include(device_MIMXRT1052_system_MIMXRT1052)
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE m)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE c)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE gcc)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE nosys)
if(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_debug)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../middleware/maestro/libs/cm7f/armgcc/release/libmp3.a)
endif(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_debug)
if(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_debug)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../middleware/maestro/libs/cm7f/armgcc/release/libwav.a)
endif(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_debug)
if(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_release)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../middleware/maestro/libs/cm7f/armgcc/release/libmp3.a)
endif(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_release)
if(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_release)
target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${ProjDirPath}/../../../../../middleware/maestro/libs/cm7f/armgcc/release/libwav.a)
endif(CMAKE_BUILD_TYPE STREQUAL flexspi_nor_release)
TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)

282
boards/evkbimxrt1050/audio_examples/maestro_record/armgcc/MIMXRT1052xxxxx_flexspi_nor.ld Normal file
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/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2
** Version: rev. 1.0, 2018-09-21
** Build: b210227
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
/* Specify the memory areas */
MEMORY
{
m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
}
/* Define output sections */
SECTIONS
{
__NCACHE_REGION_START = ORIGIN(m_data2);
__NCACHE_REGION_SIZE = 0;
.flash_config :
{
. = ALIGN(4);
__FLASH_BASE = .;
KEEP(* (.boot_hdr.conf)) /* flash config section */
. = ALIGN(4);
} > m_flash_config
ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config);
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
__Vectors = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
.ram_function : AT(__ram_function_flash_start)
{
. = ALIGN(32);
__ram_function_start__ = .;
*(CodeQuickAccess)
. = ALIGN(128);
__ram_function_end__ = .;
} > m_qacode
__NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.heap_4 :
{
. = ALIGN(4);
__START_OCRAM_BSS = .;
__bss_ocram_start__ = .;
*heap_4.c.obj(.bss .bss*)
. = ALIGN(4);
__bss_ocram_end__ = .;
__END_OCRAM_BSS = .;
} > m_data2
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

15
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if exist CMakeFiles (RD /s /Q CMakeFiles)
if exist Makefile (DEL /s /Q /F Makefile)
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
mingw32-make -j
if exist CMakeFiles (RD /s /Q CMakeFiles)
if exist Makefile (DEL /s /Q /F Makefile)
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
mingw32-make -j
IF "%1" == "" ( pause )

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#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
make -j
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
make -j

6
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@ -0,0 +1,6 @@
if exist CMakeFiles (RD /s /Q CMakeFiles)
if exist Makefile (DEL /s /Q /F Makefile)
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
mingw32-make -j 2> build_log.txt

7
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@ -0,0 +1,7 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_debug .
make -j 2>&1 | tee build_log.txt

6
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@ -0,0 +1,6 @@
if exist CMakeFiles (RD /s /Q CMakeFiles)
if exist Makefile (DEL /s /Q /F Makefile)
if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
mingw32-make -j 2> build_log.txt

7
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@ -0,0 +1,7 @@
#!/bin/sh
if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
if [ -f "Makefile" ];then rm -f Makefile; fi
if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flexspi_nor_release .
make -j 2>&1 | tee build_log.txt

3
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@ -0,0 +1,3 @@
RD /s /Q flexspi_nor_debug flexspi_nor_release CMakeFiles
DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
pause

3
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@ -0,0 +1,3 @@
#!/bin/sh
rm -rf flexspi_nor_debug flexspi_nor_release CMakeFiles
rm -rf Makefile cmake_install.cmake CMakeCache.txt

9
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@ -0,0 +1,9 @@
# config to select component, the format is CONFIG_USE_${component}
set(CONFIG_USE_component_wm8960_adapter_MIMXRT1052 true)
set(CONFIG_USE_component_lpi2c_adapter_MIMXRT1052 true)
set(CONFIG_USE_middleware_sdmmc_host_usdhc_MIMXRT1052 true)
set(CONFIG_USE_middleware_sdmmc_host_usdhc_freertos_MIMXRT1052 true)
set(CONFIG_USE_middleware_fatfs_sd_MIMXRT1052 true)
set(CONFIG_USE_component_serial_manager_uart_MIMXRT1052 true)
set(CONFIG_USE_driver_lpuart_MIMXRT1052 true)
set(CONFIG_USE_driver_common_MIMXRT1052 true)

231
boards/evkbimxrt1050/audio_examples/maestro_record/armgcc/flags.cmake Executable file
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SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_DEBUG " \
${CMAKE_ASM_FLAGS_FLEXSPI_NOR_DEBUG} \
-D__STARTUP_CLEAR_BSS \
-DDEBUG \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-mcpu=cortex-m7 \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
")
SET(CMAKE_ASM_FLAGS_FLEXSPI_NOR_RELEASE " \
${CMAKE_ASM_FLAGS_FLEXSPI_NOR_RELEASE} \
-D__STARTUP_CLEAR_BSS \
-DNDEBUG \
-D__STARTUP_INITIALIZE_NONCACHEDATA \
-mcpu=cortex-m7 \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
")
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG " \
${CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG} \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSTREAMER_ENABLE_EAP \
-DSTREAMER_ENABLE_VIT_SINK \
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
-DOPUS_ENCODE \
-DSTREAMER_ENABLE_ENCODER \
-DSTREAMER_ENABLE_CEI_OPUS \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDISABLEFLOAT16 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DHAVE_CONFIG_H \
-DSERIAL_PORT_TYPE_UART=1 \
-DSDK_OS_FREE_RTOS \
-DCASCFG_PLATFORM_FREERTOS \
-DFSL_OS_SELECTED=SDK_OS_FREERTOS \
-DFSL_OSA_TASK_ENABLE=1 \
-DSTREAMER_ENABLE_FILESRC \
-DSTREAMER_ENABLE_FILE_SINK \
-DSTREAMER_ENABLE_MEM_SRC \
-DSTREAMER_ENABLE_MEM_SINK \
-DMCUXPRESSO_SDK \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE " \
${CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE} \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DNDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSTREAMER_ENABLE_EAP \
-DSTREAMER_ENABLE_VIT_SINK \
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
-DOPUS_ENCODE \
-DSTREAMER_ENABLE_ENCODER \
-DSTREAMER_ENABLE_CEI_OPUS \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDISABLEFLOAT16 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DHAVE_CONFIG_H \
-DSERIAL_PORT_TYPE_UART=1 \
-DSDK_OS_FREE_RTOS \
-DCASCFG_PLATFORM_FREERTOS \
-DFSL_OS_SELECTED=SDK_OS_FREERTOS \
-DFSL_OSA_TASK_ENABLE=1 \
-DSTREAMER_ENABLE_FILESRC \
-DSTREAMER_ENABLE_FILE_SINK \
-DSTREAMER_ENABLE_MEM_SRC \
-DSTREAMER_ENABLE_MEM_SINK \
-DMCUXPRESSO_SDK \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-std=gnu99 \
")
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_DEBUG " \
${CMAKE_CXX_FLAGS_FLEXSPI_NOR_DEBUG} \
-DDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DMCUXPRESSO_SDK \
-g \
-O0 \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_CXX_FLAGS_FLEXSPI_NOR_RELEASE " \
${CMAKE_CXX_FLAGS_FLEXSPI_NOR_RELEASE} \
-DNDEBUG \
-DCPU_MIMXRT1052DVL6B \
-DSERIAL_PORT_TYPE_UART=1 \
-DMCUXPRESSO_SDK \
-Os \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-mthumb \
-MMD \
-MP \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mapcs \
-fno-rtti \
-fno-exceptions \
")
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_DEBUG " \
${CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_DEBUG} \
-g \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-Wl,--print-memory-usage \
-Xlinker \
--defsym=__stack_size__=0x1000 \
-Xlinker \
--defsym=__heap_size__=0x1000 \
-T${ProjDirPath}/MIMXRT1052xxxxx_flexspi_nor.ld -static \
")
SET(CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_RELEASE " \
${CMAKE_EXE_LINKER_FLAGS_FLEXSPI_NOR_RELEASE} \
-mcpu=cortex-m7 \
-Wall \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
--specs=nano.specs \
--specs=nosys.specs \
-fno-common \
-ffunction-sections \
-fdata-sections \
-ffreestanding \
-fno-builtin \
-mthumb \
-mapcs \
-Xlinker \
--gc-sections \
-Xlinker \
-static \
-Xlinker \
-z \
-Xlinker \
muldefs \
-Xlinker \
-Map=output.map \
-Wl,--print-memory-usage \
-Xlinker \
--defsym=__stack_size__=0x1000 \
-Xlinker \
--defsym=__heap_size__=0x1000 \
-T${ProjDirPath}/MIMXRT1052xxxxx_flexspi_nor.ld -static \
")

394
boards/evkbimxrt1050/audio_examples/maestro_record/board.c Normal file
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@ -0,0 +1,394 @@
/*
* Copyright 2017-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_debug_console.h"
#include "board.h"
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
#include "fsl_lpi2c.h"
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#include "fsl_iomuxc.h"
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* Get debug console frequency. */
uint32_t BOARD_DebugConsoleSrcFreq(void)
{
uint32_t freq;
/* To make it simple, we assume default PLL and divider settings, and the only variable
from application is use PLL3 source or OSC source */
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
{
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
else
{
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
return freq;
}
/* Initialize debug console. */
void BOARD_InitDebugConsole(void)
{
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
{
lpi2c_master_config_t lpi2cConfig = {0};
/*
* lpi2cConfig.debugEnable = false;
* lpi2cConfig.ignoreAck = false;
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
* lpi2cConfig.baudRate_Hz = 100000U;
* lpi2cConfig.busIdleTimeout_ns = 0;
* lpi2cConfig.pinLowTimeout_ns = 0;
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
*/
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
}
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = txBuff;
xfer.dataSize = txBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Read;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = rxBuff;
xfer.dataSize = rxBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = txBuff;
xfer.dataSize = txBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
status_t status;
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = NULL;
xfer.dataSize = 0;
status = LPI2C_MasterTransferBlocking(base, &xfer);
if (kStatus_Success == status)
{
xfer.subaddressSize = 0;
xfer.direction = kLPI2C_Read;
xfer.data = rxBuff;
xfer.dataSize = rxBuffSize;
status = LPI2C_MasterTransferBlocking(base, &xfer);
}
return status;
}
void BOARD_Accel_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
}
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
{
uint8_t data = (uint8_t)txBuff;
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
}
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
}
void BOARD_Codec_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
}
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
void BOARD_Camera_I2C_Init(void)
{
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
}
status_t BOARD_Camera_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Camera_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
rxBuffSize);
}
status_t BOARD_Camera_I2C_SendSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Camera_I2C_ReceiveSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
rxBuffSize);
}
status_t BOARD_Touch_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Touch_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
#endif /* SDK_I2C_BASED_COMPONENT_USED */
/* MPU configuration. */
void BOARD_ConfigMPU(void)
{
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
0 :
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
#endif
volatile uint32_t i = 0;
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
SCB_DisableICache();
}
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
{
SCB_DisableDCache();
}
/* Disable MPU */
ARM_MPU_Disable();
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/
/*
* Add default region to deny access to whole address space to workaround speculative prefetch.
* Refer to Arm errata 1013783-B for more details.
*
*/
/* Region 0 setting: Instruction access disabled, No data access permission. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
#endif
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
while ((size >> i) > 0x1U)
{
i++;
}
if (i != 0)
{
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t)(1 << i));
assert(i >= 5);
/* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}

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/*
* Copyright 2017-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include "clock_config.h"
#include "fsl_common.h"
#include "fsl_gpio.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "IMXRT1050-EVKB"
/* The UART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
#define BOARD_DEBUG_UART_INSTANCE 1U
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
#define BOARD_UART_IRQ LPUART1_IRQn
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
#endif /* BOARD_DEBUG_UART_BAUDRATE */
/*! @brief The USER_LED used for board */
#define LOGIC_LED_ON (0U)
#define LOGIC_LED_OFF (1U)
#ifndef BOARD_USER_LED_GPIO
#define BOARD_USER_LED_GPIO GPIO1
#endif
#ifndef BOARD_USER_LED_GPIO_PIN
#define BOARD_USER_LED_GPIO_PIN (9U)
#endif
#define USER_LED_INIT(output) \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
#define USER_LED_ON() \
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
#define USER_LED_TOGGLE() \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
/*! @brief Define the port interrupt number for the board switches */
#ifndef BOARD_USER_BUTTON_GPIO
#define BOARD_USER_BUTTON_GPIO GPIO5
#endif
#ifndef BOARD_USER_BUTTON_GPIO_PIN
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
#endif
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
#define BOARD_USER_BUTTON_NAME "SW8"
/*! @brief The hyper flash size */
#define BOARD_FLASH_SIZE (0x4000000U)
/*! @brief The ENET PHY address. */
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
#define BOARD_ARDUINO_I2C_INDEX (1)
#define BOARD_HAS_SDCARD (1U)
/* @Brief Board accelerator sensor configuration */
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
/* Clock divider for LPI2C clock source */
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
#define BOARD_CODEC_I2C_INSTANCE 1U
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
/* @Brief Board CAMERA configuration */
#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
#define BOARD_CAMERA_I2C_CLOCK_FREQ \
(CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
#define BOARD_CAMERA_I2C_SCL_PIN 16
#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
#define BOARD_CAMERA_I2C_SDA_PIN 17
#define BOARD_CAMERA_PWDN_GPIO GPIO1
#define BOARD_CAMERA_PWDN_PIN 4
/* @Brief Board touch panel configuration */
#define BOARD_TOUCH_I2C_BASEADDR LPI2C1
#define BOARD_TOUCH_RST_GPIO GPIO1
#define BOARD_TOUCH_RST_PIN 2
#define BOARD_TOUCH_INT_GPIO GPIO1
#define BOARD_TOUCH_INT_PIN 11
/* @Brief Board Bluetooth HCI UART configuration */
#define BOARD_BT_UART_BASEADDR LPUART3
#define BOARD_BT_UART_INSTANCE 3
#define BOARD_BT_UART_BAUDRATE 3000000
#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
#define BOARD_BT_UART_IRQ LPUART3_IRQn
#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
uint32_t BOARD_DebugConsoleSrcFreq(void);
void BOARD_InitDebugConsole(void);
void BOARD_ConfigMPU(void);
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
void BOARD_Accel_I2C_Init(void);
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Codec_I2C_Init(void);
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Camera_I2C_Init(void);
status_t BOARD_Camera_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Camera_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
status_t BOARD_Camera_I2C_SendSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Camera_I2C_ReceiveSCCB(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
status_t BOARD_Touch_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Touch_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */

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/*
* Copyright 2017-2020,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v8.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 10.0.0
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
- {id: CCM_ANALOG.PLL5.div, value: '31'}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.postDivider = 8, /* Divider after PLL */
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
/* Set Flexio2 clock source. */
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Video PLL. */
uint32_t pllVideo;
/* Disable Video PLL output before initial Video PLL. */
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* Bypass PLL first */
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
CCM_ANALOG->PLL_VIDEO = pllVideo;
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
{
}
/* Disable bypass for Video PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
/* Enable Usb2 PLL output. */
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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/*
* Copyright 2017-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*${header:start}*/
#include "cmd.h"
#include <string.h>
#include <stdint.h>
#include "fsl_debug_console.h"
#include "fsl_shell.h"
#include "app_streamer.h"
#include "fsl_sd_disk.h"
#include "portable.h"
#ifdef VIT_PROC
#include "PL_platformTypes_CortexM.h"
#include "VIT.h"
#include "vit_proc.h"
#endif
/*${header:end}*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*${macro:start}*/
/*${macro:end}*/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*${prototype:start}*/
static shell_status_t shellEcho(shell_handle_t shellHandle, int32_t argc, char **argv);
static shell_status_t shellRecMIC(shell_handle_t shellHandle, int32_t argc, char **argv);
#ifdef OPUS_ENCODE
static shell_status_t shellOpusEncode(shell_handle_t shellHandle, int32_t argc, char **argv);
#endif
/*${prototype:end}*/
/*******************************************************************************
* Variables
******************************************************************************/
/*${variable:start}*/
SHELL_COMMAND_DEFINE(version, "\r\n\"version\": Display component versions\r\n", shellEcho, 0);
SHELL_COMMAND_DEFINE(record_mic,
"\r\n\"record_mic\": Record MIC audio and either:\r\n"
#ifdef VIT_PROC
" - perform voice recognition (VIT)\r\n"
#endif
" - playback on WM8904 codec\r\n"
" - store samples to file.\r\n"
"\r\n"
#ifdef VIT_PROC
" USAGE: record_mic [audio|file|<file_name>|vit] 20 [en|cn]\r\n"
#else
" USAGE: record_mic [audio|file|<file_name>] 20\r\n"
#endif
" The number defines length of recording in seconds.\r\n"
#ifdef VIT_PROC
" For voice recognition say supported WakeWord and in 3s frame supported command.\r\n"
" Please note that this VIT demo is near-field and uses 1 on-board microphone.\r\n"
#endif
" NOTES: This command returns to shell after record finished.\r\n"
" To store samples to a file, the \"file\" option can be used to create a file\r\n"
" with a predefined name, or any file name (without whitespaces) can be specified\r\n"
" instead of the \"file\" option.\r\n",
shellRecMIC,
SHELL_IGNORE_PARAMETER_COUNT);
#ifdef OPUS_ENCODE
SHELL_COMMAND_DEFINE(opus_encode,
"\r\n\"opus_encode\": Initializes the streamer with the Opus memory-to-memory pipeline and\r\n"
"encodes a hardcoded buffer.\r\n",
shellOpusEncode,
0);
#endif
SDK_ALIGN(static uint8_t s_shellHandleBuffer[SHELL_HANDLE_SIZE], 4);
static shell_handle_t s_shellHandle;
extern serial_handle_t g_serialHandle;
streamer_handle_t streamerHandle;
/*${variable:end}*/
/*******************************************************************************
* Code
******************************************************************************/
/*${function:start}*/
static shell_status_t shellEcho(shell_handle_t shellHandle, int32_t argc, char **argv)
{
PRINTF(" Maestro version: 1.2\r\n");
#ifdef VIT_PROC
PRINTF(" VIT version: 5.4.0\r\n");
#endif
return kStatus_SHELL_Success;
}
static shell_status_t shellRecMIC(shell_handle_t shellHandle, int32_t argc, char **argv)
{
status_t ret;
out_sink_t out_sink;
int duration = 20;
char *file_name = NULL;
#ifdef VIT_PROC
Vit_Language = EN;
#endif
if ((argc > 1) && (strcmp(argv[1], "file") == 0))
{
out_sink = FILE_SINK;
}
else if ((argc > 1) && (strcmp(argv[1], "audio") == 0))
{
out_sink = AUDIO_SINK;
}
#ifdef VIT_PROC
else if ((argc > 1) && (strcmp(argv[1], "vit") == 0))
{
out_sink = VIT_SINK;
}
#endif
else
{
/* Save the samples to the file with the defined name */
out_sink = FILE_SINK;
file_name = argv[1];
}
if ((argc > 2))
{
if (strcmp(argv[2], "\0") != 0)
{
duration = abs(atoi(argv[2]));
}
}
#ifdef VIT_PROC
if ((argc > 3))
{
if (strcmp(argv[3], "cn") == 0)
{
Vit_Language = CN;
}
}
#endif
if (duration <= 0)
{
PRINTF("Record length in seconds must be greater than 0\r\n");
return kStatus_SHELL_Success;
}
if (out_sink == FILE_SINK)
{
if (!SDCARD_inserted())
{
PRINTF("Insert the SD card first\r\n");
return kStatus_SHELL_Success;
}
else
PRINTF("Recording to a file on sd-card\r\n");
}
PRINTF("\r\nStarting streamer demo application for %d sec\r\n", duration);
STREAMER_Init();
ret = STREAMER_mic_Create(&streamerHandle, out_sink, file_name);
if (ret != kStatus_Success)
{
PRINTF("STREAMER_Create failed\r\n");
goto error;
}
PRINTF("Starting recording\r\n");
#ifdef VIT_PROC
if (out_sink == VIT_SINK)
{
PRINTF("\r\nTo see VIT functionality say wake-word and command.\r\n");
}
#endif
STREAMER_Start(&streamerHandle);
OSA_TimeDelay(duration * 1000);
STREAMER_Stop(&streamerHandle);
error:
PRINTF("Cleanup\r\n");
STREAMER_Destroy(&streamerHandle);
/* Delay for cleanup */
OSA_TimeDelay(100);
return kStatus_SHELL_Success;
}
#ifdef OPUS_ENCODE
static shell_status_t shellOpusEncode(shell_handle_t shellHandle, int32_t argc, char **argv)
{
void *outBuf = NULL;
MEMSRC_SET_BUFFER_T inBufInfo = {0};
SET_BUFFER_DESC_T outBufInfo = {0};
bool streamerInitialized = false;
uint32_t i = 0;
status_t ret;
CeiBitstreamInfo info = {
.sample_rate = 48000, .num_channels = 1, .endian = 0, .sign = true, .sample_size = 16, .interleaved = true};
PRINTF("Starting streamer with the preliminary Opus memory-to-memory pipeline.\r\n");
PRINTF("Allocating buffers...\r\n");
outBuf = OSA_MemoryAllocate(OPUSMEM2MEM_OUTBUF_SIZE);
if (outBuf == NULL)
{
PRINTF("Outbuf allocation failed\r\n");
goto error;
}
memset(outBuf, 0, OPUSMEM2MEM_OUTBUF_SIZE);
inBufInfo = (MEMSRC_SET_BUFFER_T){.location = (int8_t *)&OPUSMEM2MEM_INBUF_CONTENT, .size = OPUSMEM2MEM_INBUF_SIZE};
outBufInfo = (SET_BUFFER_DESC_T){.ptr = (int8_t *)outBuf, .size = OPUSMEM2MEM_OUTBUF_SIZE};
PRINTF("Initializing streamer...\r\n");
STREAMER_Init();
streamerInitialized = true;
ret = STREAMER_opusmem2mem_Create(&streamerHandle, &info, &inBufInfo, &outBufInfo);
if (ret != kStatus_Success)
{
PRINTF("Streamer create failed\r\n");
goto error;
}
CeiOpusConfig cfg;
streamer_get_property(streamerHandle.streamer, PROP_ENCODER_CONFIG, (uint32_t *)&cfg, true);
cfg.bitrate = 512000;
cfg.application = OPUS_APPLICATION_AUDIO;
cfg.predictionDisabled = 1;
streamer_set_property(streamerHandle.streamer,
(ELEMENT_PROPERTY_T){.prop = PROP_ENCODER_CONFIG, .val = (uintptr_t)&cfg}, true);
PRINTF("Start encoding...\r\n");
STREAMER_Start(&streamerHandle);
while (streamerHandle.audioPlaying)
{
;
}
PRINTF("Encoding finished.\r\n");
/* Compare the result with the reference */
for (i = 0; i < OPUSMEM2MEM_OUTBUF_SIZE; i++)
{
if (OPUSMEM2MEM_REFERENCE_CONTENT[i] != outBufInfo.ptr[i])
{
break;
}
}
if (i == OPUSMEM2MEM_OUTBUF_SIZE)
{
PRINTF("The result of the OPUS encoder fully corresponds to the expected result.\r\n");
}
else
{
PRINTF("The result of the OPUS encoder doesn't match the expected result. The difference is in %u byte.\r\n",
i);
}
error:
PRINTF("Cleanup\r\n");
if (outBuf != NULL)
{
OSA_MemoryFree(outBuf);
outBuf = NULL;
}
if (streamerInitialized)
{
STREAMER_Destroy(&streamerHandle);
}
/* Delay for cleanup */
OSA_TimeDelay(100);
return kStatus_SHELL_Success;
}
#endif
void shellCmd(void)
{
/* Init SHELL */
s_shellHandle = &s_shellHandleBuffer[0];
SHELL_Init(s_shellHandle, g_serialHandle, ">> ");
/* Add new command to commands list */
SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(version));
SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(record_mic));
#ifdef OPUS_ENCODE
SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(opus_encode));
#endif
#if !(defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
while (1)
{
SHELL_Task(s_shellHandle);
}
#endif
}
/*${function:end}*/

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CMD_H_
#define _CMD_H_
/*${header:start}*/
#include "main.h"
#ifdef OPUS_ENCODE
#include "opusmem2mem_file.h"
#endif
/*${header:end}*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*${macro:start}*/
typedef void handleShellMessageCallback_t(void *arg);
/*${macro:end}*/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Common function for getting user input using shell console.
*
* @param[in] handleShellMessageCallback Callback to function which should
* handle serialized message.
* @param[in] arg Data to pass to callback handler.
*/
void shellCmd(void);
/*${prototype:end}*/
/** Constants **/
#ifdef OPUS_ENCODE
#define OPUSMEM2MEM_INBUF_SIZE 96000
#define OPUSMEM2MEM_OUTBUF_SIZE 32960
#endif
#endif

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/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#include "dcd.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.dcd_data"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.dcd_data"
#endif
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: DCDx V2.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 9.0.1
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
const uint8_t dcd_data[] = {
/* HEADER */
/* Tag */
0xD2,
/* Image Length */
0x04, 0x10,
/* Version */
0x41,
/* COMMANDS */
/* group: 'Imported Commands' */
/* #1.1-113, command header bytes for merged 'Write - value' command */
0xCC, 0x03, 0x8C, 0x04,
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */
0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B,
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
/* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
/* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
/* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
/* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
/* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
/* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
/* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
/* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07,
/* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
/* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
/* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
/* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
/* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
/* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
/* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
/* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
/* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
/* #3.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
/* #5.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
/* #7.1-3, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x1C, 0x04,
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30,
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
};
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
#else
const uint8_t dcd_data[] = {0x00};
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef __DCD__
#define __DCD__
#include <stdint.h>
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.1. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_VERSION (0x41)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_ARRAY_SIZE 1
#endif /* __DCD__ */

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#ifndef _FFCONF_H_
#define _FFCONF_H_
/*---------------------------------------------------------------------------/
/ FatFs Functional Configurations
/---------------------------------------------------------------------------*/
#define FFCONF_DEF 86631 /* Revision ID */
/*---------------------------------------------------------------------------/
/ MSDK adaptation configuration
/---------------------------------------------------------------------------*/
#define SD_DISK_ENABLE
/*---------------------------------------------------------------------------/
/ Function Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_READONLY 0
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: Basic functions are fully enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
/ are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define FF_USE_FIND 0
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#define FF_USE_MKFS 0
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define FF_USE_FASTSEEK 0
/* This option switches fast seek function. (0:Disable or 1:Enable) */
#define FF_USE_EXPAND 0
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#define FF_USE_CHMOD 0
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
#define FF_USE_LABEL 0
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define FF_USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
#define FF_USE_STRFUNC 1
#define FF_PRINT_LLI 0
#define FF_PRINT_FLOAT 0
#define FF_STRF_ENCODE 3
/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and
/ f_printf().
/
/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion.
/
/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2
makes f_printf() support floating point argument. These features want C99 or later.
/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character
/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE
/ to be read/written via those functions.
/
/ 0: ANSI/OEM in current CP
/ 1: Unicode in UTF-16LE
/ 2: Unicode in UTF-16BE
/ 3: Unicode in UTF-8
*/
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define FF_CODE_PAGE 932
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect code page setting can cause a file open failure.
/
/ 437 - U.S.
/ 720 - Arabic
/ 737 - Greek
/ 771 - KBL
/ 775 - Baltic
/ 850 - Latin 1
/ 852 - Latin 2
/ 855 - Cyrillic
/ 857 - Turkish
/ 860 - Portuguese
/ 861 - Icelandic
/ 862 - Hebrew
/ 863 - Canadian French
/ 864 - Arabic
/ 865 - Nordic
/ 866 - Russian
/ 869 - Greek 2
/ 932 - Japanese (DBCS)
/ 936 - Simplified Chinese (DBCS)
/ 949 - Korean (DBCS)
/ 950 - Traditional Chinese (DBCS)
/ 0 - Include all code pages above and configured by f_setcp()
*/
#define FF_USE_LFN 3
#define FF_MAX_LFN 255
/* The FF_USE_LFN switches the support for LFN (long file name).
/
/ 0: Disable LFN. FF_MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
/ specification.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
#define FF_LFN_UNICODE 0
/* This option switches the character encoding on the API when LFN is enabled.
/
/ 0: ANSI/OEM in current CP (TCHAR = char)
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
/ 2: Unicode in UTF-8 (TCHAR = char)
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
/
/ Also behavior of string I/O functions will be affected by this option.
/ When LFN is not enabled, this option has no effect. */
#define FF_LFN_BUF 255
#define FF_SFN_BUF 12
/* This set of options defines size of file name members in the FILINFO structure
/ which is used to read out directory items. These values should be suffcient for
/ the file names to read. The maximum possible length of the read file name depends
/ on character encoding. When LFN is not enabled, these options have no effect. */
#define FF_FS_RPATH 2
/* This option configures support for relative path.
/
/ 0: Disable relative path and remove related functions.
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
*/
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#define FF_VOLUMES 3
/* Number of volumes (logical drives) to be used. (1-10) */
#define FF_STR_VOLUME_ID 0
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
/ not defined, a user defined volume string table needs to be defined as:
/
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
*/
#define FF_MULTI_PARTITION 0
/* This option switches support for multiple volumes on the physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
/ When this function is enabled (1), each logical drive number can be bound to
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
/ funciton will be available. */
#define FF_MIN_SS 512
#define FF_MAX_SS 4096
/* This set of options configures the range of sector size to be supported. (512,
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
/ harddisk, but a larger value may be required for on-board flash memory and some
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
/ for variable sector size mode and disk_ioctl() function needs to implement
/ GET_SECTOR_SIZE command. */
#define FF_LBA64 0
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
#define FF_MIN_GPT 0x10000000
/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
#define FF_USE_TRIM 0
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
#define FF_FS_EXFAT 0
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
#define FF_FS_NORTC 1
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2021
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_NOFSINFO 0
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
#define FF_FS_LOCK 0
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
/ is 1.
/
/ 0: Disable file lock function. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock function. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock control is independent of re-entrancy. */
#define FF_FS_REENTRANT 1
#define FF_FS_TIMEOUT 1000
#if FF_FS_REENTRANT
#include "FreeRTOS.h"
#include "semphr.h"
#define FF_SYNC_t SemaphoreHandle_t
#endif
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this function.
/
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function, must be added to the project. Samples are available in
/ option/syscall.c.
/
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
/ included somewhere in the scope of ff.h. */
/*--- End of configuration options ---*/
#endif /* _FFCONF_H_ */

256
boards/evkbimxrt1050/audio_examples/maestro_record/maestro_record_v3_10.xml Normal file
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@ -0,0 +1,256 @@
<?xml version="1.0" encoding="UTF-8"?>
<ksdk:examples xmlns:ksdk="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nxp.com/ksdk/2.0/ksdk_manifest_v3.0.xsd manifest.xsd">
<externalDefinitions>
<definition extID="platform.drivers.lpi2c.MIMXRT1052"/>
<definition extID="platform.drivers.sai.MIMXRT1052"/>
<definition extID="driver.wm8960.MIMXRT1052"/>
<definition extID="driver.codec.MIMXRT1052"/>
<definition extID="platform.drivers.common.MIMXRT1052"/>
<definition extID="component.wm8960_adapter.MIMXRT1052"/>
<definition extID="component.codec_i2c.MIMXRT1052"/>
<definition extID="component.lpi2c_adapter.MIMXRT1052"/>
<definition extID="platform.drivers.sai_edma.MIMXRT1052"/>
<definition extID="platform.drivers.dmamux.MIMXRT1052"/>
<definition extID="platform.drivers.edma.MIMXRT1052"/>
<definition extID="middleware.sdmmc.sd.MIMXRT1052"/>
<definition extID="middleware.sdmmc.common.MIMXRT1052"/>
<definition extID="middleware.sdmmc.host.usdhc.MIMXRT1052"/>
<definition extID="middleware.sdmmc.host.usdhc.freertos.MIMXRT1052"/>
<definition extID="platform.drivers.cache_armv7_m7.MIMXRT1052"/>
<definition extID="middleware.vit.cm7_RT105x.MIMXRT1052"/>
<definition extID="CMSIS_DSP_Source.MIMXRT1052"/>
<definition extID="platform.drivers.flexram.MIMXRT1052"/>
<definition extID="component.igpio_adapter.MIMXRT1052"/>
<definition extID="middleware.freertos-kernel.heap_4.MIMXRT1052"/>
<definition extID="middleware.maestro_framework.MIMXRT1052"/>
<definition extID="utility.shell.MIMXRT1052"/>
<definition extID="middleware.fatfs.MIMXRT1052"/>
<definition extID="middleware.fatfs.sd.MIMXRT1052"/>
<definition extID="middleware.maestro_framework.opus.MIMXRT1052"/>
<definition extID="platform.drivers.clock.MIMXRT1052"/>
<definition extID="device.MIMXRT1052_CMSIS.MIMXRT1052"/>
<definition extID="utility.debug_console.MIMXRT1052"/>
<definition extID="component.lpuart_adapter.MIMXRT1052"/>
<definition extID="component.serial_manager.MIMXRT1052"/>
<definition extID="component.lists.MIMXRT1052"/>
<definition extID="component.serial_manager_uart.MIMXRT1052"/>
<definition extID="platform.drivers.lpuart.MIMXRT1052"/>
<definition extID="device.MIMXRT1052_startup.MIMXRT1052"/>
<definition extID="platform.drivers.iomuxc.MIMXRT1052"/>
<definition extID="platform.utilities.assert.MIMXRT1052"/>
<definition extID="platform.drivers.igpio.MIMXRT1052"/>
<definition extID="platform.drivers.xip_device.MIMXRT1052"/>
<definition extID="platform.drivers.xip_board.evkbimxrt1050.MIMXRT1052"/>
<definition extID="component.silicon_id.MIMXRT1052"/>
<definition extID="CMSIS_Include_core_cm.MIMXRT1052"/>
<definition extID="middleware.sdmmc.osa.freertos.MIMXRT1052"/>
<definition extID="component.osa_free_rtos.MIMXRT1052"/>
<definition extID="middleware.freertos-kernel.MIMXRT1052"/>
<definition extID="middleware.freertos-kernel.extension.MIMXRT1052"/>
<definition extID="platform.drivers.usdhc.MIMXRT1052"/>
<definition extID="driver.soc_flexram_allocate.MIMXRT1052"/>
<definition extID="middleware.maestro_framework.doc.MIMXRT1052"/>
<definition extID="middleware.maestro_framework.streamer.MIMXRT1052"/>
<definition extID="platform.utilities.misc_utilities.MIMXRT1052"/>
<definition extID="device.MIMXRT1052_system.MIMXRT1052"/>
<definition extID="iar"/>
<definition extID="armgcc"/>
<definition extID="mcuxpresso"/>
<definition extID="com.nxp.mcuxpresso"/>
<definition extID="com.crt.advproject.config.exe.debug"/>
<definition extID="com.crt.advproject.config.exe.release"/>
<definition extID="mdk"/>
</externalDefinitions>
<example id="evkbimxrt1050_maestro_record" name="maestro_record" dependency="platform.drivers.lpi2c.MIMXRT1052 platform.drivers.sai.MIMXRT1052 driver.wm8960.MIMXRT1052 driver.codec.MIMXRT1052 platform.drivers.common.MIMXRT1052 component.wm8960_adapter.MIMXRT1052 component.codec_i2c.MIMXRT1052 component.lpi2c_adapter.MIMXRT1052 platform.drivers.sai_edma.MIMXRT1052 platform.drivers.dmamux.MIMXRT1052 platform.drivers.edma.MIMXRT1052 middleware.sdmmc.sd.MIMXRT1052 middleware.sdmmc.common.MIMXRT1052 middleware.sdmmc.host.usdhc.MIMXRT1052 middleware.sdmmc.host.usdhc.freertos.MIMXRT1052 platform.drivers.cache_armv7_m7.MIMXRT1052 middleware.vit.cm7_RT105x.MIMXRT1052 CMSIS_DSP_Source.MIMXRT1052 platform.drivers.flexram.MIMXRT1052 component.igpio_adapter.MIMXRT1052 middleware.freertos-kernel.heap_4.MIMXRT1052 middleware.maestro_framework.MIMXRT1052 utility.shell.MIMXRT1052 middleware.fatfs.MIMXRT1052 middleware.fatfs.sd.MIMXRT1052 middleware.maestro_framework.opus.MIMXRT1052 platform.drivers.clock.MIMXRT1052 device.MIMXRT1052_CMSIS.MIMXRT1052 utility.debug_console.MIMXRT1052 component.lpuart_adapter.MIMXRT1052 component.serial_manager.MIMXRT1052 component.lists.MIMXRT1052 component.serial_manager_uart.MIMXRT1052 platform.drivers.lpuart.MIMXRT1052 device.MIMXRT1052_startup.MIMXRT1052 platform.drivers.iomuxc.MIMXRT1052 platform.utilities.assert.MIMXRT1052 platform.drivers.igpio.MIMXRT1052 platform.drivers.xip_device.MIMXRT1052 platform.drivers.xip_board.evkbimxrt1050.MIMXRT1052 component.silicon_id.MIMXRT1052 CMSIS_Include_core_cm.MIMXRT1052 middleware.sdmmc.osa.freertos.MIMXRT1052 component.osa_free_rtos.MIMXRT1052 middleware.freertos-kernel.MIMXRT1052 middleware.freertos-kernel.extension.MIMXRT1052 platform.drivers.usdhc.MIMXRT1052 driver.soc_flexram_allocate.MIMXRT1052 middleware.maestro_framework.doc.MIMXRT1052 middleware.maestro_framework.streamer.MIMXRT1052 platform.utilities.misc_utilities.MIMXRT1052 device.MIMXRT1052_system.MIMXRT1052" category="audio_examples">
<projects>
<project type="com.crt.advproject.projecttype.exe" nature="org.eclipse.cdt.core.cnature"/>
</projects>
<memory>
<memoryBlock id="BOARD_FLASH_evkbimxrt1050" name="BOARD_FLASH" addr="60000000" size="04000000" type="ExtFlash" access="RO"/>
<memoryBlock id="SRAM_DTC_evkbimxrt1050" name="SRAM_DTC" addr="20000000" size="00008000" type="RAM" access="RW"/>
<memoryBlock id="SRAM_OC_evkbimxrt1050" name="SRAM_OC" addr="20200000" size="00078000" type="RAM" access="RW"/>
<memoryBlock id="BOARD_SDRAM_evkbimxrt1050" name="BOARD_SDRAM" addr="80000000" size="01E00000" type="RAM" access="RW"/>
<memoryBlock id="NCACHE_REGION_evkbimxrt1050" name="NCACHE_REGION" addr="81E00000" size="00200000" type="RAM" access="RW"/>
</memory>
<toolchainSettings>
<toolchainSetting id_refs="com.nxp.mcuxpresso">
<option id="gnu.c.compiler.option.preprocessor.def.symbols" type="stringList">
<value>PLATFORM_RT1050</value>
<value>VIT_PROC</value>
<value>CPU_MIMXRT1052DVL6B</value>
<value>SDK_DEBUGCONSOLE=1</value>
<value>XIP_EXTERNAL_FLASH=1</value>
<value>XIP_BOOT_HEADER_ENABLE=1</value>
<value>STREAMER_ENABLE_EAP</value>
<value>STREAMER_ENABLE_VIT_SINK</value>
<value>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</value>
<value>OPUS_ENCODE</value>
<value>STREAMER_ENABLE_ENCODER</value>
<value>STREAMER_ENABLE_CEI_OPUS</value>
<value>DEBUG_CONSOLE_TRANSFER_NON_BLOCKING</value>
<value>OSA_USED</value>
<value>SHELL_TASK_STACK_SIZE=4000</value>
<value>SDK_I2C_BASED_COMPONENT_USED=1</value>
<value>BOARD_USE_CODEC=1</value>
<value>CODEC_WM8960_ENABLE</value>
<value>SD_ENABLED</value>
<value>SAI_XFER_QUEUE_SIZE=2</value>
<value>DISABLEFLOAT16</value>
<value>DEBUG_CONSOLE_RX_ENABLE=0</value>
<value>HAVE_CONFIG_H</value>
<value>SERIAL_PORT_TYPE_UART=1</value>
<value>SDK_OS_FREE_RTOS</value>
<value>CASCFG_PLATFORM_FREERTOS</value>
<value>FSL_OS_SELECTED=SDK_OS_FREERTOS</value>
<value>FSL_OSA_TASK_ENABLE=1</value>
<value>STREAMER_ENABLE_FILESRC</value>
<value>STREAMER_ENABLE_FILE_SINK</value>
<value>STREAMER_ENABLE_MEM_SRC</value>
<value>STREAMER_ENABLE_MEM_SINK</value>
<value>MCUXPRESSO_SDK</value>
</option>
<option id="com.crt.advproject.gas.hdrlib" type="enum">
<value>com.crt.advproject.gas.hdrlib.newlib</value>
</option>
<option id="com.crt.advproject.gas.specs" type="enum">
<value>com.crt.advproject.gas.specs.newlib</value>
</option>
<option id="com.crt.advproject.gcc.hdrlib" type="enum">
<value>com.crt.advproject.gcc.hdrlib.newlib</value>
</option>
<option id="com.crt.advproject.gcc.specs" type="enum">
<value>com.crt.advproject.gcc.specs.newlib</value>
</option>
<option id="com.crt.advproject.link.gcc.hdrlib" type="enum">
<value>com.crt.advproject.gcc.link.hdrlib.newlib.nohost</value>
</option>
<option id="com.crt.advproject.link.fpu" type="enum">
<value>com.crt.advproject.link.fpu.fpv5dp.hard</value>
</option>
<option id="gnu.c.link.option.nostdlibs" type="boolean">
<value>true</value>
</option>
<option id="com.crt.advproject.link.memory.sections" type="stringList">
<value>isd=*heap_4.o(.bss .bss*);region=SRAM_OC;type=.bss</value>
<value>isd=*(NonCacheable.init);region=SRAM_DTC;type=.data</value>
<value>isd=*(NonCacheable);region=SRAM_DTC;type=.bss</value>
</option>
<option id="com.crt.advproject.link.memory.heapAndStack" type="string">
<value>&amp;Heap:Default;Default;0x1000&amp;Stack:Default;Default;0x1000</value>
</option>
<option id="com.crt.advproject.gas.fpu" type="enum">
<value>com.crt.advproject.gas.fpu.fpv5dp.hard</value>
</option>
<option id="com.crt.advproject.gcc.fpu" type="enum">
<value>com.crt.advproject.gcc.fpu.fpv5dp.hard</value>
</option>
<option id="gnu.c.compiler.option.optimization.flags" type="string">
<value>-fno-common</value>
</option>
<option id="com.crt.advproject.c.misc.dialect" type="enum">
<value>com.crt.advproject.misc.dialect.gnu99</value>
</option>
<option id="gnu.c.compiler.option.misc.other" type="string">
<value>-c -ffunction-sections -fdata-sections -ffreestanding -fno-builtin</value>
</option>
<option id="gnu.c.compiler.option.warnings.allwarn" type="boolean">
<value>false</value>
</option>
<option id="gnu.c.compiler.option.warnings.toerrors" type="boolean">
<value>false</value>
</option>
</toolchainSetting>
</toolchainSettings>
<debug_configurations>
<debug_configuration id_refs="com.crt.advproject.config.exe.debug com.crt.advproject.config.exe.release">
<drivers>
<driver id_refs="BOARD_FLASH_evkbimxrt1050">
<driverBinary path="../../../../devices/MIMXRT1052/mcuxpresso" project_relative_path="binary" type="binary">
<files mask="MIMXRT1050-EVK_S26KS512S.cfx"/>
</driverBinary>
</driver>
</drivers>
</debug_configuration>
</debug_configurations>
<include_paths>
<include_path path="." project_relative_path="source" type="c_include"/>
<include_path path="." project_relative_path="board" type="c_include"/>
<include_path path="../.." project_relative_path="board" type="c_include"/>
<include_path path="." project_relative_path="evkbimxrt1050/audio_examples/maestro_record" type="c_include"/>
<include_path path="." project_relative_path="source" type="asm_include"/>
</include_paths>
<source path="iar" project_relative_path="./" type="workspace" toolchain="iar">
<files mask="maestro_record.ewd"/>
<files mask="maestro_record.ewp"/>
<files mask="maestro_record.eww"/>
</source>
<source path="armgcc" project_relative_path="./" type="workspace" toolchain="armgcc">
<files mask="build_all.bat"/>
<files mask="build_all.sh"/>
<files mask="clean.bat"/>
<files mask="clean.sh"/>
<files mask="CMakeLists.txt"/>
<files mask="flags.cmake"/>
<files mask="config.cmake"/>
<files mask="build_flexspi_nor_debug.bat"/>
<files mask="build_flexspi_nor_debug.sh"/>
<files mask="build_flexspi_nor_release.bat"/>
<files mask="build_flexspi_nor_release.sh"/>
</source>
<source path="." project_relative_path="source" type="src" toolchain="mcuxpresso">
<files mask="vit_proc.c"/>
</source>
<source path="." project_relative_path="source" type="c_include" toolchain="mcuxpresso">
<files mask="vit_proc.h"/>
</source>
<source path="." project_relative_path="source" type="c_include">
<files mask="opusmem2mem_file.h"/>
<files mask="app_streamer.h"/>
<files mask="cmd.h"/>
<files mask="main.h"/>
<files mask="FreeRTOSConfig.h"/>
<files mask="ffconf.h"/>
</source>
<source path="." project_relative_path="source" type="src">
<files mask="app_streamer.c"/>
<files mask="cmd.c"/>
<files mask="main.c"/>
</source>
<source path="." project_relative_path="board" type="src">
<files mask="pin_mux.c"/>
</source>
<source path="." project_relative_path="board" type="c_include">
<files mask="pin_mux.h"/>
</source>
<source path="." project_relative_path="source" type="src">
<files mask="streamer_pcm.c"/>
</source>
<source path="." project_relative_path="source" type="c_include">
<files mask="streamer_pcm_app.h"/>
</source>
<source path="iar" project_relative_path="evkbimxrt1050/audio_examples/common/linker" type="linker" toolchain="iar">
<files mask="MIMXRT1052xxxxx_flexspi_nor.icf"/>
</source>
<source path="armgcc" project_relative_path="evkbimxrt1050/audio_examples/common/linker" type="linker" toolchain="armgcc">
<files mask="MIMXRT1052xxxxx_flexspi_nor.ld"/>
</source>
<source path="." project_relative_path="board" type="src">
<files mask="sdmmc_config.c"/>
<files mask="board.c"/>
<files mask="clock_config.c"/>
<files mask="dcd.c"/>
</source>
<source path="." project_relative_path="board" type="c_include">
<files mask="sdmmc_config.h"/>
<files mask="board.h"/>
<files mask="clock_config.h"/>
<files mask="dcd.h"/>
</source>
<source path="." project_relative_path="source" type="c_include">
<files mask="app_definitions.h"/>
</source>
<source path="." project_relative_path="doc" type="doc" toolchain="iar mdk mcuxpresso armgcc">
<files mask="readme.txt"/>
</source>
</example>
</ksdk:examples>

363
boards/evkbimxrt1050/audio_examples/maestro_record/main.c Normal file
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@ -0,0 +1,363 @@
/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Board includes */
#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "main.h"
#include "cmd.h"
#include "fsl_sd.h"
#include "ff.h"
#include "diskio.h"
#include "fsl_sd_disk.h"
#include "sdmmc_config.h"
#include "fsl_debug_console.h"
#include "fsl_gpio.h"
#include "fsl_iomuxc.h"
#include "fsl_dmamux.h"
#include "fsl_codec_common.h"
/* Flexram reallocation needed in MCUXpresso for VIT support to extend OCRAM */
#ifdef __MCUXPRESSO
#include "fsl_flexram.h"
#endif
#include "fsl_wm8960.h"
#include "app_definitions.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define APP_SHELL_TASK_STACK_SIZE (1024)
#define SDCARD_TASK_STACK_SIZE (512)
/*******************************************************************************
* Prototypes
******************************************************************************/
int BOARD_CODEC_Init(void);
static void APP_SDCARD_DetectCallBack(bool isInserted, void *userData);
/*******************************************************************************
* Variables
******************************************************************************/
codec_handle_t codecHandle = {0};
wm8960_config_t wm8960Config = {
.i2cConfig = {.codecI2CInstance = BOARD_CODEC_I2C_INSTANCE, .codecI2CSourceClock = BOARD_CODEC_I2C_CLOCK_FREQ},
.route = kWM8960_RoutePlaybackandRecord,
.leftInputSource = kWM8960_InputDifferentialMicInput3,
.rightInputSource = kWM8960_InputDifferentialMicInput2,
.playSource = kWM8960_PlaySourceDAC,
.slaveAddress = WM8960_I2C_ADDR,
.bus = kWM8960_BusI2S,
.format = {.mclk_HZ = 6144000U, .sampleRate = kWM8960_AudioSampleRate48KHz, .bitWidth = kWM8960_AudioBitWidth16bit},
.master_slave = false,
};
codec_config_t boardCodecConfig = {.codecDevType = kCODEC_WM8960, .codecDevConfig = &wm8960Config};
#if (defined __GNUC__ && !defined __MCUXPRESSO)
extern uint32_t __bss_ocram_start__;
extern uint32_t __bss_ocram_end__;
#endif
static app_handle_t app;
/*******************************************************************************
* Code
******************************************************************************/
/*
* AUDIO PLL setting: Frequency = Fref * (DIV_SELECT + NUM / DENOM)
* = 24 * (30 + 66/625)
* = 722.5344 MHz
*/
const clock_audio_pll_config_t audioPllConfig = {
.loopDivider = 30, /* PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
.postDivider = 1, /* Divider after the PLL, should only be 1, 2, 4, 8, 16. */
.numerator = 66, /* 30 bit numerator of fractional loop divider. */
.denominator = 625, /* 30 bit denominator of fractional loop divider */
};
void BOARD_EnableSaiMclkOutput(bool enable)
{
if (enable)
{
IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK;
}
else
{
IOMUXC_GPR->GPR1 &= (~IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK);
}
}
int BOARD_CODEC_Init(void)
{
CODEC_Init(&codecHandle, &boardCodecConfig);
/* Initial volume kept low for hearing safety. */
CODEC_SetVolume(&codecHandle, kCODEC_PlayChannelHeadphoneLeft | kCODEC_PlayChannelHeadphoneRight, DEMO_VOLUME);
return 0;
}
void SystemInitHook(void)
{
#if defined(__MCUXPRESSO)
IOMUXC_GPR->GPR17 = (kFLEXRAM_BankDTCM << 0) | (kFLEXRAM_BankOCRAM << 2) | (kFLEXRAM_BankOCRAM << 4) |
(kFLEXRAM_BankOCRAM << 6) | (kFLEXRAM_BankOCRAM << 8) | (kFLEXRAM_BankOCRAM << 10) |
(kFLEXRAM_BankOCRAM << 12) | (kFLEXRAM_BankOCRAM << 14) | (kFLEXRAM_BankOCRAM << 16) |
(kFLEXRAM_BankOCRAM << 18) | (kFLEXRAM_BankOCRAM << 20) | (kFLEXRAM_BankOCRAM << 22) |
(kFLEXRAM_BankOCRAM << 24) | (kFLEXRAM_BankOCRAM << 26) | (kFLEXRAM_BankOCRAM << 28) |
(kFLEXRAM_BankOCRAM << 30);
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
#endif
#if (defined __GNUC__ && !defined __MCUXPRESSO)
/* Initialization of OCRAM BSS section. */
uint32_t startAddr; /* Address of the source memory. */
uint32_t endAddr; /* End of copied memory. */
/* Get the addresses for the OCRAM BSS section (zero-initialized data). */
startAddr = (uint32_t)&__bss_ocram_start__;
endAddr = (uint32_t)&__bss_ocram_end__;
/* Reset the .bss section. */
while (startAddr < endAddr)
{
/* Clear one byte. */
*((uint8_t *)startAddr) = 0U;
/* Increment the pointer. */
startAddr++;
}
#endif
}
#ifdef VIT_PROC
void update_MPU_config(void)
{
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
SCB_DisableICache();
}
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
{
SCB_DisableDCache();
}
/* Disable MPU */
ARM_MPU_Disable();
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}
#endif
static void APP_SDCARD_DetectCallBack(bool isInserted, void *userData)
{
app_handle_t *app = (app_handle_t *)userData;
app->sdcardInserted = isInserted;
xSemaphoreGiveFromISR(app->sdcardSem, NULL);
}
bool SDCARD_inserted(void)
{
return (app.sdcardInserted);
}
void APP_SDCARD_Task(void *param)
{
const TCHAR driverNumberBuffer[3U] = {SDDISK + '0', ':', '/'};
FRESULT error;
app_handle_t *app = (app_handle_t *)param;
app->sdcardSem = xSemaphoreCreateBinary();
BOARD_SD_Config(&g_sd, APP_SDCARD_DetectCallBack, BOARD_SDMMC_SD_HOST_IRQ_PRIORITY, app);
PRINTF("[APP_SDCARD_Task] start\r\n");
/* SD host init function */
if (SD_HostInit(&g_sd) != kStatus_Success)
{
PRINTF("[APP_SDCARD_Task] SD host init failed.\r\n");
vTaskSuspend(NULL);
}
/* Small delay for SD card detection logic to process */
vTaskDelay(100 / portTICK_PERIOD_MS);
while (1)
{
/* Block waiting for SDcard detect interrupt */
xSemaphoreTake(app->sdcardSem, portMAX_DELAY);
if (app->sdcardInserted != app->sdcardInsertedPrev)
{
app->sdcardInsertedPrev = app->sdcardInserted;
SD_SetCardPower(&g_sd, false);
if (app->sdcardInserted)
{
/* power on the card */
SD_SetCardPower(&g_sd, true);
if (f_mount(&app->fileSystem, driverNumberBuffer, 0U))
{
PRINTF("[APP_SDCARD_Task] Mount volume failed.\r\n");
continue;
}
#if (FF_FS_RPATH >= 2U)
error = f_chdrive((char const *)&driverNumberBuffer[0U]);
if (error)
{
PRINTF("[APP_SDCARD_Task] Change drive failed.\r\n");
continue;
}
#endif
PRINTF("[APP_SDCARD_Task] SD card drive mounted\r\n");
xSemaphoreGive(app->sdcardSem);
}
}
}
}
void APP_Shell_Task(void *param)
{
PRINTF("[APP_Shell_Task] start\r\n");
/* Handle shell commands. */
shellCmd();
vTaskSuspend(NULL);
while (1)
;
}
int main(void)
{
int ret;
BOARD_ConfigMPU();
#ifdef VIT_PROC
update_MPU_config();
#endif
BOARD_InitBootPins();
BOARD_BootClockRUN();
/* 1. Init SAI clock .*/
CLOCK_InitAudioPll(&audioPllConfig);
BOARD_InitDebugConsole();
/*Clock setting for LPI2C*/
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER);
CLOCK_SetMux(kCLOCK_Sai1Mux, DEMO_SAI1_CLOCK_SOURCE_SELECT);
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER);
CLOCK_SetDiv(kCLOCK_Sai1Div, DEMO_SAI1_CLOCK_SOURCE_DIVIDER);
/*Enable MCLK clock*/
BOARD_EnableSaiMclkOutput(true);
DMAMUX_Init(DEMO_DMAMUX);
DMAMUX_SetSource(DEMO_DMAMUX, DEMO_TX_CHANNEL, (uint8_t)DEMO_SAI_TX_SOURCE);
DMAMUX_EnableChannel(DEMO_DMAMUX, DEMO_TX_CHANNEL);
DMAMUX_SetSource(DEMO_DMAMUX, DEMO_RX_CHANNEL, (uint8_t)DEMO_SAI_RX_SOURCE);
DMAMUX_EnableChannel(DEMO_DMAMUX, DEMO_RX_CHANNEL);
PRINTF("\r\n");
PRINTF("*******************************\r\n");
PRINTF("Maestro audio record demo start\r\n");
PRINTF("*******************************\r\n");
PRINTF("\r\n");
/* Initialize OSA*/
OSA_Init();
ret = BOARD_CODEC_Init();
if (ret)
{
PRINTF("CODEC_Init failed\r\n");
return -1;
}
if (xTaskCreate(APP_SDCARD_Task, "SDCard Task", SDCARD_TASK_STACK_SIZE, &app, configMAX_PRIORITIES - 4, NULL) !=
pdPASS)
{
PRINTF("\r\nFailed to create application task\r\n");
while (1)
;
}
/* Set shell command task priority = 1 */
if (xTaskCreate(APP_Shell_Task, "Shell Task", APP_SHELL_TASK_STACK_SIZE, &app, configMAX_PRIORITIES - 5,
&app.shell_task_handle) != pdPASS)
{
PRINTF("\r\nFailed to create application task\r\n");
while (1)
;
}
/* Run RTOS */
vTaskStartScheduler();
/* Should not reach this statement */
return 0;
}
/**
* @brief Loop forever if stack overflow is detected.
*
* If configCHECK_FOR_STACK_OVERFLOW is set to 1,
* this hook provides a location for applications to
* define a response to a stack overflow.
*
* Use this hook to help identify that a stack overflow
* has occurred.
*
*/
void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName)
{
portDISABLE_INTERRUPTS();
/* Loop forever */
for (;;)
;
}
/**
* @brief Warn user if pvPortMalloc fails.
*
* Called if a call to pvPortMalloc() fails because there is insufficient
* free memory available in the FreeRTOS heap. pvPortMalloc() is called
* internally by FreeRTOS API functions that create tasks, queues, software
* timers, and semaphores. The size of the FreeRTOS heap is set by the
* configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h.
*
*/
void vApplicationMallocFailedHook()
{
PRINTF(("\r\nERROR: Malloc failed to allocate memory\r\n"));
/* Loop forever */
for (;;)
;
}

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/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __MAIN_H__
#define __MAIN_H__
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include "ff.h"
#include <stdbool.h>
/*******************************************************************************
* Definitions
******************************************************************************/
typedef struct _app_handle
{
TaskHandle_t shell_task_handle;
/* SD card management */
SemaphoreHandle_t sdcardSem;
volatile bool sdcardInserted;
volatile bool sdcardInsertedPrev;
FATFS fileSystem;
FIL fileObject;
} app_handle_t;
bool SDCARD_inserted(void);
#endif /* __MAIN_H__ */

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/*
* Copyright 2017-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v9.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 0.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: M13, peripheral: SAI1, signal: sai_mclk, pin_signal: GPIO_AD_B1_09, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: G12, peripheral: SAI1, signal: sai_tx_bclk, pin_signal: GPIO_AD_B1_14, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: H11, peripheral: SAI1, signal: sai_tx_data0, pin_signal: GPIO_AD_B1_13, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: J14, peripheral: SAI1, signal: sai_tx_sync, pin_signal: GPIO_AD_B1_15, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: H12, peripheral: SAI1, signal: sai_rx_data0, pin_signal: GPIO_AD_B1_12, software_input_on: Enable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: D13, peripheral: GPIO2, signal: 'gpio_io, 28', pin_signal: GPIO_B1_12, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Disable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0, slew_rate: Fast}
- {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14, software_input_on: Disable, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_47K_Ohm,
pull_keeper_select: Pull, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_4, slew_rate: Fast}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_GPIO2_IO28, 0x017089U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0x0170A1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0x017089U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0x014089U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0x017089U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0x017089U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0x017089U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0x017089U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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Overview
========
The maestro_demo application demonstrates audio processing on the ARM cortex core
utilizing the Maestro Audio Framework library.
Depending on target platform there are different features of the demo enabled.
- loopback from microphone to speaker
- recording microphone to a file
- wake words + voice commands recognition
The application is controlled by commands from a shell interface using serial console.
Type "help" to see the command list. Similar description will be displayed on serial console:
>> help
"help": List all the registered commands
"exit": Exit program
"version": Display component versions
"record_mic": Record MIC audio and either:
- perform voice recognition (VIT)
- playback on WM8904 codec
- store samples to file.
USAGE: record_mic [audio|file|vit] 20 [en|cn]
The number defines length of recording in seconds.
For voice recognition say supported WakeWord and in 3s frame supported command.
Please note that this VIT demo is near-field and uses 1 on-board microphone.
NOTE: this command returns to shell after record finished.
For custom VIT model generation (defining own wake words and voice commands) please use https://vit.nxp.com/
Toolchain supported
===================
- IAR embedded Workbench 9.30.1
- GCC ARM Embedded 10.3.1
- MCUXpresso 11.6.0
Hardware requirements
=====================
- Micro USB cable
- JTAG/SWD debugger
- EVKB-IMXRT1050 board
- Personal Computer
- Headphones with 3.5 mm stereo jack
Board settings
==============
Please insert a SDCARD into card slot(J20)
Prepare the Demo
================
1. Connect a micro USB cable between the PC host and the debug USB port (J41) on the board
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Connect the headphones into the headphone jack on EVKB-MIMXRT1050 board (J12).
5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Note:
There is limited RAM on this platform, which brings following limitations:
- VIT is not enabled
Running the demo
================
When the example runs successfully, you should see similar output on the serial terminal as below:
**********************************
Maestro audio solutions demo start
**********************************
[APP_SDCARD_Task] start
[APP_Shell_Task] start
SHELL build: Nov 5 2020
Copyright 2020 NXP
>> [APP_SDCARD_Task] SD card drive mounted

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/*
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "sdmmc_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
void BOARD_SDCardPowerControl(bool enable);
/*******************************************************************************
* Variables
******************************************************************************/
/*!brief sdmmc dma buffer */
AT_NONCACHEABLE_SECTION_ALIGN(static uint32_t s_sdmmcHostDmaBuffer[BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE],
SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE);
#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
/* two cache line length for sdmmc host driver maintain unalign transfer */
SDK_ALIGN(static uint8_t s_sdmmcCacheLineAlignBuffer[BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U],
BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE);
#endif
#if defined(SDIO_ENABLED) || defined(SD_ENABLED)
static sd_detect_card_t s_cd;
static sd_io_voltage_t s_ioVoltage = {
.type = BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE,
.func = NULL,
};
#endif
static sdmmchost_t s_host;
#ifdef SDIO_ENABLED
static sdio_card_int_t s_sdioInt;
#endif
GPIO_HANDLE_DEFINE(s_CardDetectGpioHandle);
GPIO_HANDLE_DEFINE(s_PowerResetGpioHandle);
/*******************************************************************************
* Code
******************************************************************************/
uint32_t BOARD_USDHC1ClockConfiguration(void)
{
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
/* Configure USDHC clock source and divider */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); /* USDHC clock root frequency maximum: 198MHZ */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
return 396000000U / 2U;
}
#if defined(SDIO_ENABLED) || defined(SD_ENABLED)
bool BOARD_SDCardGetDetectStatus(void)
{
uint8_t pinState;
if (HAL_GpioGetInput(s_CardDetectGpioHandle, &pinState) == kStatus_HAL_GpioSuccess)
{
if (pinState == BOARD_SDMMC_SD_CD_INSERT_LEVEL)
{
return true;
}
}
return false;
}
void SDMMC_SD_CD_Callback(void *param)
{
if (s_cd.callback != NULL)
{
s_cd.callback(BOARD_SDCardGetDetectStatus(), s_cd.userData);
}
}
void BOARD_SDCardDAT3PullFunction(uint32_t status)
{
if (status == kSD_DAT3PullDown)
{
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
IOMUXC_SW_PAD_CTL_PAD_DSE(1));
}
else
{
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(1));
}
}
void BOARD_SDCardDetectInit(sd_cd_t cd, void *userData)
{
uint8_t pinState;
/* install card detect callback */
s_cd.cdDebounce_ms = BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS;
s_cd.type = BOARD_SDMMC_SD_CD_TYPE;
s_cd.cardDetected = BOARD_SDCardGetDetectStatus;
s_cd.callback = cd;
s_cd.userData = userData;
if (BOARD_SDMMC_SD_CD_TYPE == kSD_DetectCardByGpioCD)
{
hal_gpio_pin_config_t sw_config = {
kHAL_GpioDirectionIn,
0,
BOARD_SDMMC_SD_CD_GPIO_PORT,
BOARD_SDMMC_SD_CD_GPIO_PIN,
};
HAL_GpioInit(s_CardDetectGpioHandle, &sw_config);
HAL_GpioSetTriggerMode(s_CardDetectGpioHandle, BOARD_SDMMC_SD_CD_INTTERUPT_TYPE);
HAL_GpioInstallCallback(s_CardDetectGpioHandle, SDMMC_SD_CD_Callback, NULL);
if (HAL_GpioGetInput(s_CardDetectGpioHandle, &pinState) == kStatus_HAL_GpioSuccess)
{
if (pinState == BOARD_SDMMC_SD_CD_INSERT_LEVEL)
{
if (cd != NULL)
{
cd(true, userData);
}
}
}
}
/* register DAT3 pull function switch function pointer */
if (BOARD_SDMMC_SD_CD_TYPE == kSD_DetectCardByHostDATA3)
{
s_cd.dat3PullFunc = BOARD_SDCardDAT3PullFunction;
/* make sure the card is power on for DAT3 pull up */
BOARD_SDCardPowerControl(true);
}
}
void BOARD_SDCardPowerResetInit(void)
{
hal_gpio_pin_config_t sw_config = {
kHAL_GpioDirectionOut,
1,
BOARD_SDMMC_SD_POWER_RESET_GPIO_PORT,
BOARD_SDMMC_SD_POWER_RESET_GPIO_PIN,
};
HAL_GpioInit(s_PowerResetGpioHandle, &sw_config);
}
void BOARD_SDCardPowerControl(bool enable)
{
if (enable)
{
HAL_GpioSetOutput(s_PowerResetGpioHandle, 1);
}
else
{
/* Power off the card only when the card is inserted, since the card detect circuit is depend on the power on
* the EVK, card detect will not work if the power is off */
if (BOARD_SDCardGetDetectStatus() == true)
{
HAL_GpioSetOutput(s_PowerResetGpioHandle, 0);
}
}
}
void BOARD_SD_Pin_Config(uint32_t freq)
{
uint32_t speed = 0U, strength = 0U;
if (freq <= 50000000)
{
speed = 0U;
strength = 7U;
}
else if (freq <= 100000000)
{
speed = 2U;
strength = 7U;
}
else
{
speed = 3U;
strength = 7U;
}
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
}
#endif
#ifdef SD_ENABLED
void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData)
{
assert(card);
s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer;
s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL;
#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
#endif
((sd_card_t *)card)->host = &s_host;
((sd_card_t *)card)->host->hostController.base = BOARD_SDMMC_SD_HOST_BASEADDR;
((sd_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
((sd_card_t *)card)->usrParam.cd = &s_cd;
((sd_card_t *)card)->usrParam.pwr = BOARD_SDCardPowerControl;
((sd_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config;
((sd_card_t *)card)->usrParam.ioVoltage = &s_ioVoltage;
((sd_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ;
BOARD_SDCardPowerResetInit();
BOARD_SDCardDetectInit(cd, userData);
NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, hostIRQPriority);
}
#endif
#ifdef SDIO_ENABLED
void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt)
{
assert(card);
s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer;
s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL;
#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
#endif
((sdio_card_t *)card)->host = &s_host;
((sdio_card_t *)card)->host->hostController.base = BOARD_SDMMC_SDIO_HOST_BASEADDR;
((sdio_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
((sdio_card_t *)card)->usrParam.cd = &s_cd;
((sdio_card_t *)card)->usrParam.pwr = BOARD_SDCardPowerControl;
((sdio_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config;
((sdio_card_t *)card)->usrParam.ioVoltage = &s_ioVoltage;
((sdio_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ;
if (cardInt != NULL)
{
s_sdioInt.cardInterrupt = cardInt;
((sdio_card_t *)card)->usrParam.sdioInt = &s_sdioInt;
}
BOARD_SDCardPowerResetInit();
BOARD_SDCardDetectInit(cd, NULL);
NVIC_SetPriority(BOARD_SDMMC_SDIO_HOST_IRQ, hostIRQPriority);
}
#endif
#ifdef MMC_ENABLED
static void BOARD_MMC_Pin_Config(uint32_t freq)
{
uint32_t speed = 0U, strength = 0U;
if (freq <= 50000000)
{
speed = 0U;
strength = 7U;
}
else if (freq <= 100000000)
{
speed = 2U;
strength = 7U;
}
else
{
speed = 3U;
strength = 7U;
}
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
}
void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority)
{
assert(card);
s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer;
s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL;
#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
#endif
((mmc_card_t *)card)->host = &s_host;
((mmc_card_t *)card)->host->hostController.base = BOARD_SDMMC_MMC_HOST_BASEADDR;
((mmc_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
((mmc_card_t *)card)->usrParam.ioStrength = BOARD_MMC_Pin_Config;
((mmc_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ;
((mmc_card_t *)card)->hostVoltageWindowVCC = BOARD_SDMMC_MMC_VCC_SUPPLY;
((mmc_card_t *)card)->hostVoltageWindowVCCQ = BOARD_SDMMC_MMC_VCCQ_SUPPLY;
NVIC_SetPriority(BOARD_SDMMC_MMC_HOST_IRQ, hostIRQPriority);
}
#endif

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/*
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _SDMMC_CONFIG_H_
#define _SDMMC_CONFIG_H_
#ifdef SD_ENABLED
#include "fsl_sd.h"
#endif
#ifdef MMC_ENABLED
#include "fsl_mmc.h"
#endif
#ifdef SDIO_ENABLED
#include "fsl_sdio.h"
#endif
#include "clock_config.h"
#include "fsl_adapter_gpio.h"
#include "fsl_sdmmc_host.h"
#include "fsl_sdmmc_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* @brief host basic configuration */
#define BOARD_SDMMC_SD_HOST_BASEADDR USDHC1
#define BOARD_SDMMC_SD_HOST_IRQ USDHC1_IRQn
#define BOARD_SDMMC_MMC_HOST_BASEADDR USDHC1
#define BOARD_SDMMC_MMC_HOST_IRQ USDHC1_IRQn
#define BOARD_SDMMC_SDIO_HOST_BASEADDR USDHC1
#define BOARD_SDMMC_SDIO_HOST_IRQ USDHC1_IRQn
/* @brief card detect configuration */
#define BOARD_SDMMC_SD_CD_GPIO_BASE GPIO2
#define BOARD_SDMMC_SD_CD_GPIO_PORT 2
#define BOARD_SDMMC_SD_CD_GPIO_PIN 28U
#define BOARD_SDMMC_SD_CD_INTTERUPT_TYPE kHAL_GpioInterruptEitherEdge
#define BOARD_SDMMC_SD_CD_INSERT_LEVEL (0U)
/* @brief card detect type
*
* Note: Please pay attention, DAT3 card detection cannot works during the card access,
* since the DAT3 will be used for data transfer, thus the functionality of card detect will be disabled. Using card
* detect pin for card detection is recommended.
*/
#define BOARD_SDMMC_SD_CD_TYPE kSD_DetectCardByGpioCD
#define BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS (100U)
/*! @brief SD power reset */
#define BOARD_SDMMC_SD_POWER_RESET_GPIO_BASE GPIO1
#define BOARD_SDMMC_SD_POWER_RESET_GPIO_PORT 1
#define BOARD_SDMMC_SD_POWER_RESET_GPIO_PIN 5U
/*! @brief SD IO voltage */
#define BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE kSD_IOVoltageCtrlByHost
#define BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
#define BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ (180000000U)
/*! @brief mmc configuration */
#define BOARD_SDMMC_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
#define BOARD_SDMMC_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
/*! @brief align with cache line size */
#define BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE (32U)
/*!@ brief host interrupt priority*/
#define BOARD_SDMMC_SD_HOST_IRQ_PRIORITY (5U)
#define BOARD_SDMMC_MMC_HOST_IRQ_PRIORITY (5U)
#define BOARD_SDMMC_SDIO_HOST_IRQ_PRIORITY (5U)
/*!@brief dma descriptor buffer size */
#define BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE (32U)
/*! @brief cache maintain function enabled for RW buffer */
#define BOARD_SDMMC_HOST_CACHE_CONTROL kSDMMCHOST_CacheControlRWBuffer
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief BOARD SD configurations.
* @param card card descriptor
* @param cd card detect callback
* @param userData user data for callback
*/
#ifdef SD_ENABLED
void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData);
#endif
/*!
* @brief BOARD SDIO configurations.
* @param card card descriptor
* @param cd card detect callback
* @param cardInt card interrupt
*/
#ifdef SDIO_ENABLED
void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt);
#endif
/*!
* @brief BOARD MMC configurations.
* @param card card descriptor
* @param cd card detect callback
* @param userData user data for callback
*/
#ifdef MMC_ENABLED
void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority);
#endif
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */

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/*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "board.h"
#include "streamer_pcm_app.h"
#include "fsl_codec_common.h"
#include "fsl_wm8960.h"
#include "app_definitions.h"
#include "fsl_cache.h"
AT_NONCACHEABLE_SECTION_INIT(static pcm_rtos_t pcmHandle) = {0};
extern codec_handle_t codecHandle;
/*! @brief SAI Transmit IRQ handler.
*
* This function is used to handle or clear error state.
*/
static void SAI_UserTxIRQHandler(void)
{
/* Clear the FEF (Tx FIFO underrun) flag. */
SAI_TxClearStatusFlags(DEMO_SAI, kSAI_FIFOErrorFlag);
SAI_TxSoftwareReset(DEMO_SAI, kSAI_ResetTypeFIFO);
SDK_ISR_EXIT_BARRIER;
}
/*! @brief SAI Receive IRQ handler.
*
* This function is used to handle or clear error state.
*/
static void SAI_UserRxIRQHandler(void)
{
/* Clear the FEF (Rx FIFO overflow) flag. */
SAI_RxClearStatusFlags(DEMO_SAI, kSAI_FIFOErrorFlag);
SAI_RxSoftwareReset(DEMO_SAI, kSAI_ResetTypeFIFO);
SDK_ISR_EXIT_BARRIER;
}
/*! @brief SAI IRQ handler.
*
* This function checks FIFO overrun/underrun errors and clears error state.
*/
void SAI1_IRQHandler(void)
{
if (DEMO_SAI->TCSR & kSAI_FIFOErrorFlag)
SAI_UserTxIRQHandler();
if (DEMO_SAI->RCSR & kSAI_FIFOErrorFlag)
SAI_UserRxIRQHandler();
}
/*! @brief SAI EDMA transmit callback
*
* This function is called by the EDMA interface after a block of data has been
* successfully written to the SAI.
*/
static void saiTxCallback(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData)
{
pcm_rtos_t *pcm = (pcm_rtos_t *)userData;
BaseType_t reschedule = -1;
xSemaphoreGiveFromISR(pcm->semaphoreTX, &reschedule);
portYIELD_FROM_ISR(reschedule);
}
static void saiRxCallback(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData)
{
pcm_rtos_t *pcm = (pcm_rtos_t *)userData;
BaseType_t reschedule = -1;
xSemaphoreGiveFromISR(pcm->semaphoreRX, &reschedule);
portYIELD_FROM_ISR(reschedule);
}
void streamer_pcm_init(void)
{
edma_config_t dmaConfig;
NVIC_SetPriority(LPI2C1_IRQn, 5);
NVIC_SetPriority(DEMO_SAI_TX_IRQ, 5U);
NVIC_SetPriority(DEMO_SAI_RX_IRQ, 5U);
NVIC_SetPriority(DMA1_DMA17_IRQn, 4U);
NVIC_SetPriority(DMA0_DMA16_IRQn, 4U);
EDMA_GetDefaultConfig(&dmaConfig);
EDMA_Init(DEMO_DMA, &dmaConfig);
/* Create DMA handle. */
EDMA_CreateHandle(&pcmHandle.dmaTxHandle, DEMO_DMA, DEMO_TX_CHANNEL);
EDMA_CreateHandle(&pcmHandle.dmaRxHandle, DEMO_DMA, DEMO_RX_CHANNEL);
/* SAI init */
SAI_Init(DEMO_SAI);
EnableIRQ(DEMO_SAI_RX_IRQ);
EnableIRQ(DEMO_SAI_TX_IRQ);
}
pcm_rtos_t *streamer_pcm_open(uint32_t num_buffers)
{
pcmHandle.semaphoreTX = xSemaphoreCreateBinary();
SAI_TransferTxCreateHandleEDMA(DEMO_SAI, &pcmHandle.saiTxHandle, saiTxCallback, (void *)&pcmHandle,
&pcmHandle.dmaTxHandle);
return &pcmHandle;
}
pcm_rtos_t *streamer_pcm_rx_open(uint32_t num_buffers)
{
pcmHandle.semaphoreRX = xSemaphoreCreateBinary();
SAI_TransferRxCreateHandleEDMA(DEMO_SAI, &pcmHandle.saiRxHandle, saiRxCallback, (void *)&pcmHandle,
&pcmHandle.dmaRxHandle);
return &pcmHandle;
}
void streamer_pcm_start(pcm_rtos_t *pcm)
{
/* Interrupts already enabled - nothing to do.
* App/streamer can begin writing data to SAI. */
}
void streamer_pcm_close(pcm_rtos_t *pcm)
{
/* Stop playback. This will flush the SAI transmit buffers. */
SAI_TransferTerminateSendEDMA(DEMO_SAI, &pcm->saiTxHandle);
vSemaphoreDelete(pcmHandle.semaphoreTX);
}
void streamer_pcm_rx_close(pcm_rtos_t *pcm)
{
/* Stop playback. This will flush the SAI transmit buffers. */
SAI_TransferTerminateReceiveEDMA(DEMO_SAI, &pcm->saiRxHandle);
vSemaphoreDelete(pcmHandle.semaphoreRX);
}
int streamer_pcm_write(pcm_rtos_t *pcm, uint8_t *data, uint32_t size)
{
/* Ensure write size is a multiple of 32, otherwise EDMA will assert
* failure. Round down for the last chunk of a file/stream. */
pcm->saiTx.dataSize = size - (size % 32);
pcm->saiTx.data = data;
DCACHE_CleanByRange((uint32_t)pcm->saiTx.data, pcm->saiTx.dataSize);
/* Start the consecutive transfer */
while (SAI_TransferSendEDMA(DEMO_SAI, &pcm->saiTxHandle, &pcm->saiTx) == kStatus_SAI_QueueFull)
{
/* Wait for transfer to finish */
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
{
return -1;
}
}
return 0;
}
int streamer_pcm_read(pcm_rtos_t *pcm, uint8_t *data, uint32_t size)
{
/* Ensure write size is a multiple of 32, otherwise EDMA will assert
* failure. Round down for the last chunk of a file/stream. */
pcm->saiRx.dataSize = size - (size % 32);
pcm->saiRx.data = data;
/* Start the first transfer */
if (pcm->isFirstRx)
{
SAI_TransferReceiveEDMA(DEMO_SAI, &pcm->saiRxHandle, &pcm->saiRx);
pcm->isFirstRx = 0;
}
/* Wait for the previous transfer to finish */
if (xSemaphoreTake(pcm->semaphoreRX, portMAX_DELAY) != pdTRUE)
return -1;
DCACHE_InvalidateByRange((uint32_t)pcm->saiRx.data, pcm->saiRx.dataSize);
/* Start the consecutive transfer */
SAI_TransferReceiveEDMA(DEMO_SAI, &pcm->saiRxHandle, &pcm->saiRx);
/* Enable SAI Tx due to clock availability for the codec (see board schematic). */
if (pcm->dummy_tx_enable)
SAI_TxEnable(DEMO_SAI, true);
return 0;
}
/*! @brief Map an integer sample rate (Hz) to internal SAI enum */
static sai_sample_rate_t _pcm_map_sample_rate(uint32_t sample_rate)
{
switch (sample_rate)
{
case 8000:
return kSAI_SampleRate8KHz;
case 11025:
return kSAI_SampleRate11025Hz;
case 12000:
return kSAI_SampleRate12KHz;
case 16000:
return kSAI_SampleRate16KHz;
case 24000:
return kSAI_SampleRate24KHz;
case 22050:
return kSAI_SampleRate22050Hz;
case 32000:
return kSAI_SampleRate32KHz;
case 44100:
return kSAI_SampleRate44100Hz;
case 48000:
default:
return kSAI_SampleRate48KHz;
}
}
/*! @brief Map an integer bit width (bits) to internal SAI enum */
static sai_word_width_t _pcm_map_word_width(uint32_t bit_width)
{
switch (bit_width)
{
case 8:
return kSAI_WordWidth8bits;
case 16:
return kSAI_WordWidth16bits;
case 24:
return kSAI_WordWidth24bits;
case 32:
return kSAI_WordWidth32bits;
default:
return kSAI_WordWidth16bits;
}
}
/*! @brief Map an integer number of channels to internal SAI enum */
static sai_mono_stereo_t _pcm_map_channels(uint8_t num_channels)
{
if (num_channels >= 2)
return kSAI_Stereo;
else
return kSAI_MonoRight;
}
int streamer_pcm_setparams(pcm_rtos_t *pcm,
uint32_t sample_rate,
uint32_t bit_width,
uint8_t num_channels,
bool transfer,
bool dummy_tx,
int volume)
{
sai_transfer_format_t format = {0};
sai_transceiver_t saiConfig, saiConfig2;
uint32_t masterClockHz = 0U;
pcm->isFirstRx = transfer ? pcm->isFirstRx : 1U;
pcm->sample_rate = sample_rate;
pcm->bit_width = bit_width;
pcm->num_channels = num_channels;
pcm->dummy_tx_enable = dummy_tx;
masterClockHz = streamer_set_master_clock(sample_rate);
format.channel = 0U;
format.bitWidth = _pcm_map_word_width(bit_width);
format.sampleRate_Hz = _pcm_map_sample_rate(sample_rate);
format.stereo = _pcm_map_channels(num_channels);
#if (defined FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER && FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
format.masterClockHz = masterClockHz;
#endif
/* I2S transfer mode configurations */
if (transfer)
{
if (pcm->num_channels > 2)
{
SAI_GetTDMConfig(&saiConfig, kSAI_FrameSyncLenOneBitClk, kSAI_WordWidth32bits, DEMO_CHANNEL_NUM,
kSAI_Channel0Mask);
saiConfig.frameSync.frameSyncEarly = true;
}
else
{
SAI_GetClassicI2SConfig(&saiConfig, _pcm_map_word_width(bit_width), format.stereo, 1U << DEMO_SAI_CHANNEL);
/* If there wasn't first RX transfer, we need to set SAI mode to Async */
if (pcm->isFirstRx)
{
saiConfig.syncMode = kSAI_ModeAsync;
}
else
/* Otherwise we need to sync the SAI for the loopback */
{
saiConfig.syncMode = kSAI_ModeSync;
}
}
saiConfig.masterSlave = kSAI_Master;
SAI_TransferTerminateSendEDMA(DEMO_SAI, &pcm->saiTxHandle);
SAI_TransferTxSetConfigEDMA(DEMO_SAI, &pcmHandle.saiTxHandle, &saiConfig);
/* set bit clock divider */
SAI_TxSetBitClockRate(DEMO_SAI, masterClockHz, _pcm_map_sample_rate(sample_rate),
_pcm_map_word_width(bit_width), DEMO_CHANNEL_NUM);
/* Enable SAI transmit and FIFO error interrupts. */
SAI_TxEnableInterrupts(DEMO_SAI, kSAI_FIFOErrorInterruptEnable);
}
else
{
if (pcm->num_channels > 2)
{
SAI_GetTDMConfig(&saiConfig, kSAI_FrameSyncLenOneBitClk, kSAI_WordWidth32bits, DEMO_CHANNEL_NUM,
kSAI_Channel0Mask);
saiConfig.frameSync.frameSyncEarly = true;
}
else
{
SAI_GetClassicI2SConfig(&saiConfig, _pcm_map_word_width(bit_width), format.stereo, 1U << DEMO_SAI_CHANNEL);
saiConfig.syncMode = kSAI_ModeAsync;
saiConfig.masterSlave = kSAI_Master;
}
if (dummy_tx)
SAI_GetClassicI2SConfig(&saiConfig2, _pcm_map_word_width(bit_width), format.stereo, 1U << DEMO_SAI_CHANNEL);
SAI_TransferRxSetConfigEDMA(DEMO_SAI, &pcmHandle.saiRxHandle, &saiConfig);
/* set bit clock divider */
SAI_RxSetBitClockRate(DEMO_SAI, masterClockHz, _pcm_map_sample_rate(sample_rate),
_pcm_map_word_width(bit_width), DEMO_CHANNEL_NUM);
if (dummy_tx)
{
saiConfig2.syncMode = kSAI_ModeSync;
saiConfig2.masterSlave = kSAI_Master;
SAI_TransferTxSetConfigEDMA(DEMO_SAI, &pcmHandle.saiTxHandle, &saiConfig2);
/* set bit clock divider */
SAI_TxSetBitClockRate(DEMO_SAI, masterClockHz, _pcm_map_sample_rate(sample_rate),
_pcm_map_word_width(bit_width), DEMO_CHANNEL_NUM);
/* Enable SAI transmit and FIFO error interrupts. */
SAI_TxEnableInterrupts(DEMO_SAI, kSAI_FIFOErrorInterruptEnable);
}
/* Enable SAI transmit and FIFO error interrupts. */
SAI_RxEnableInterrupts(DEMO_SAI, kSAI_FIFOErrorInterruptEnable);
}
streamer_pcm_set_volume(pcm, 0);
CODEC_SetFormat(&codecHandle, masterClockHz, format.sampleRate_Hz, format.bitWidth);
streamer_pcm_set_volume(pcm, DEMO_VOLUME);
return 0;
}
void streamer_pcm_getparams(pcm_rtos_t *pcm, uint32_t *sample_rate, uint32_t *bit_width, uint8_t *num_channels)
{
*sample_rate = pcm->sample_rate;
*bit_width = pcm->bit_width;
*num_channels = pcm->num_channels;
}
int streamer_pcm_mute(pcm_rtos_t *pcm, bool mute)
{
CODEC_SetMute(&codecHandle, DEMO_CODEC_CHANNEL, mute);
return 0;
}
int streamer_pcm_set_volume(pcm_rtos_t *pcm, int volume)
{
int channel;
channel = (pcm->num_channels == 1) ? kCODEC_PlayChannelHeadphoneLeft : DEMO_CODEC_CHANNEL;
if (volume <= 0)
CODEC_SetMute(&codecHandle, channel, true);
else
CODEC_SetVolume(&codecHandle, channel, volume > CODEC_VOLUME_MAX_VALUE ? CODEC_VOLUME_MAX_VALUE : volume);
return 0;
}
int streamer_set_master_clock(int sample_rate)
{
int master_clock;
#if DEMO_CODEC_CS42448
int divider = DEMO_SAI1_CLOCK_SOURCE_DIVIDER;
int predivider = DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER;
#endif
if (sample_rate % 8000 == 0 || sample_rate % 6000 == 0)
{
/* Configure Audio PLL clock to 786.432 MHz to to be divisible by 48000 Hz */
const clock_audio_pll_config_t audioPllConfig48 = {
.loopDivider = 32, /* PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
.postDivider = 1, /* Divider after the PLL, should only be 1, 2, 4, 8, 16. */
.numerator = 96, /* 30 bit numerator of fractional loop divider. */
.denominator = 125, /* 30 bit denominator of fractional loop divider */
};
CLOCK_InitAudioPll(&audioPllConfig48);
}
else
{
/* Configure Audio PLL clock to 722.5344 MHz to be divisible by 44100 Hz */
const clock_audio_pll_config_t audioPllConfig = {
.loopDivider = 30, /* PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
.postDivider = 1, /* Divider after the PLL, should only be 1, 2, 4, 8, 16. */
.numerator = 66, /* 30 bit numerator of fractional loop divider. */
.denominator = 625, /* 30 bit denominator of fractional loop divider */
};
CLOCK_InitAudioPll(&audioPllConfig);
}
#if DEMO_CODEC_CS42448
switch (sample_rate)
{
case 11025:
case 12000:
case 24000:
{
divider = 63;
break;
}
case 8000:
{
predivider = 1;
}
case 16000:
{
divider = 47;
break;
}
case 32000:
{
divider = 23;
break;
}
case 22050:
case 44100:
case 48000:
default:
divider = 31;
break;
}
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, predivider);
CLOCK_SetDiv(kCLOCK_Sai1Div, divider);
master_clock = CLOCK_GetFreq(kCLOCK_AudioPllClk) / (divider + 1U) / (predivider + 1U);
#else
master_clock = DEMO_SAI_CLK_FREQ;
#endif
return master_clock;
}

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/*
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_STREAMER_PCM_APP_H_
#define _FSL_STREAMER_PCM_APP_H_
#include "fsl_dmamux.h"
#include "fsl_sai_edma.h"
#include "FreeRTOS.h"
#include "portable.h"
#include "semphr.h"
#include "streamer_pcm.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PCM interface structure */
struct _pcm_rtos_t
{
sai_transfer_t saiTx;
sai_edma_handle_t saiTxHandle;
edma_handle_t dmaTxHandle;
sai_transfer_t saiRx;
sai_edma_handle_t saiRxHandle;
edma_handle_t dmaRxHandle;
uint32_t sample_rate;
uint32_t bit_width;
uint8_t num_channels;
SemaphoreHandle_t semaphoreRX;
SemaphoreHandle_t semaphoreTX;
uint8_t isFirstRx;
bool dummy_tx_enable;
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Set PCM interface master clock
*
* This function is called by the application interface to align the master
* clock of the audio peripherals with the sample rate.
*
* @param sample_rate Desired sample rate
* @return master clock that has been set
*/
int streamer_set_master_clock(int sample_rate);
#if defined(__cplusplus)
}
#endif
#endif

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <string.h>
#include <math.h>
#include "app_definitions.h"
#include "fsl_debug_console.h"
#include "fsl_os_abstraction.h"
#include "vit_proc.h"
#include "VIT_Model_en.h"
#include "VIT_Model_cn.h"
#include "VIT.h"
#define VIT_CMD_TIME_SPAN 3.0
#if (defined(DEMO_CODEC_CS42448) && (DEMO_CODEC_CS42448 > 0))
#define NUMBER_OF_CHANNELS 2
#define BYTE_DEPTH 4
#elif (defined(PLATFORM_RT1170) || defined(PLATFORM_RT1160))
#define NUMBER_OF_CHANNELS 1
#define BYTE_DEPTH 4
#else
#define NUMBER_OF_CHANNELS 1
#define BYTE_DEPTH 2
#endif
#define MODEL_LOCATION VIT_MODEL_IN_ROM
#if (NUMBER_OF_CHANNELS == 1)
#define VIT_OPERATING_MODE VIT_WAKEWORD_ENABLE | VIT_VOICECMD_ENABLE
#else
#define VIT_OPERATING_MODE VIT_WAKEWORD_ENABLE | VIT_VOICECMD_ENABLE | VIT_AFE_ENABLE
#endif
#if (NUMBER_OF_CHANNELS == 1)
#define VIT_MIC1_MIC2_DISTANCE 0
#else
#define VIT_MIC1_MIC2_DISTANCE 65
#endif
#define VIT_MIC1_MIC3_DISTANCE 0
#if defined(PLATFORM_RT1040)
#define DEVICE_ID VIT_IMXRT1040
#elif defined(PLATFORM_RT1050)
#define DEVICE_ID VIT_IMXRT1050
#elif defined(PLATFORM_RT1060)
#define DEVICE_ID VIT_IMXRT1060
#elif defined(PLATFORM_RT1160)
#define DEVICE_ID VIT_IMXRT1160
#elif defined(PLATFORM_RT1170)
#define DEVICE_ID VIT_IMXRT1170
#else
#error "No platform selected"
#endif
#define MEMORY_ALIGNMENT 8 // in bytes
static VIT_Handle_t VITHandle = PL_NULL; // VIT handle pointer
static VIT_InstanceParams_st VITInstParams; // VIT instance parameters structure
static VIT_ControlParams_st VITControlParams; // VIT control parameters structure
static PL_MemoryTable_st VITMemoryTable; // VIT memory table descriptor
static PL_BOOL InitPhase_Error = PL_FALSE;
static VIT_DataIn_st VIT_InputBuffers = {PL_NULL, PL_NULL,
PL_NULL}; // Resetting Input Buffer addresses provided to VIT_process() API
static PL_INT8 *pMemory[PL_NR_MEMORY_REGIONS];
#if DEMO_CODEC_CS42448 || PLATFORM_RT1170 || PLATFORM_RT1160
static PL_INT16 DeInterleavedBuffer[VIT_SAMPLES_PER_FRAME * DEMO_CHANNEL_NUM];
#endif
VIT_ReturnStatus_en VIT_ModelInfo(void)
{
VIT_ReturnStatus_en VIT_Status;
VIT_ModelInfo_st Model_Info;
VIT_Status = VIT_GetModelInfo(&Model_Info);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_GetModelInfo error: %d\r\n", VIT_Status);
return VIT_INVALID_MODEL;
}
PRINTF("\n VIT Model info\r\n");
PRINTF(" VIT Model Release: 0x%04x\r\n", Model_Info.VIT_Model_Release);
if (Model_Info.pLanguage != PL_NULL)
{
PRINTF(" Language supported: %s \r\n", Model_Info.pLanguage);
}
PRINTF(" Number of WakeWords supported : %d \r\n", Model_Info.NbOfWakeWords);
PRINTF(" Number of Commands supported : %d \r\n", Model_Info.NbOfVoiceCmds);
if (!Model_Info.WW_VoiceCmds_Strings) // Check here if Model is containing WW and CMDs strings
{
PRINTF(" VIT_Model integrating WakeWord and Voice Commands strings: NO\r\n");
}
else
{
const char *ptr;
PRINTF(" VIT_Model integrating WakeWord and Voice Commands strings: YES\r\n");
PRINTF(" WakeWords supported : \r\n");
ptr = Model_Info.pWakeWord;
if (ptr != PL_NULL)
{
for (PL_UINT16 i = 0; i < Model_Info.NbOfWakeWords; i++)
{
PRINTF(" '%s' \r\n", ptr);
ptr += strlen(ptr) + 1; // to consider NULL char
}
}
PRINTF(" Voice commands supported: \r\n");
ptr = Model_Info.pVoiceCmds_List;
if (ptr != PL_NULL)
{
for (PL_UINT16 i = 0; i < Model_Info.NbOfVoiceCmds; i++)
{
PRINTF(" '%s' \r\n", ptr);
ptr += strlen(ptr) + 1; // to consider NULL char
}
}
}
/*
* VIT Get Library information
*/
VIT_LibInfo_st Lib_Info;
VIT_Status = VIT_GetLibInfo(&Lib_Info);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_GetLibInfo error: %d\r\n", VIT_Status);
return VIT_INVALID_STATE;
}
PRINTF("\n VIT Lib Info\r\n");
PRINTF(" VIT LIB Release: 0x%04x\r\n", Lib_Info.VIT_LIB_Release);
PRINTF(" VIT Features supported by the lib: 0x%04x\r\n", Lib_Info.VIT_Features_Supported);
PRINTF(" Number of channels supported by VIT lib: %d\r\n", Lib_Info.NumberOfChannels_Supported);
if (Lib_Info.WakeWord_In_Text2Model)
{
PRINTF(" VIT WakeWord in Text2Model\r\n\r\n");
}
else
{
PRINTF(" VIT WakeWord in Audio2Model\r\n\r\n");
}
/*
* Configure VIT Instance Parameters
*/
// Check that NUMBER_OF_CHANNELS is supported by VIT
// Retrieve from VIT_GetLibInfo API the number of channel supported by the VIT lib
PL_UINT16 max_nb_of_Channels = Lib_Info.NumberOfChannels_Supported;
if (NUMBER_OF_CHANNELS > max_nb_of_Channels)
{
PRINTF("VIT lib is supporting only: %d channels\r\n", max_nb_of_Channels);
return VIT_INVALID_PARAMETER_OUTOFRANGE;
}
return VIT_SUCCESS;
}
int VIT_Initialize(void *arg)
{
VIT_ReturnStatus_en VIT_Status;
uint16_t i, minIdx; /* loop index */
int32_t temp32; /* temporary address */
int16_t j; /* loop index */
uint16_t order[PL_NR_MEMORY_REGIONS];
switch (Vit_Language)
{
case CN:
VIT_Status = VIT_SetModel(VIT_Model_cn, VIT_MODEL_IN_ROM);
break;
default:
VIT_Status = VIT_SetModel(VIT_Model_en, VIT_MODEL_IN_ROM);
}
if (VIT_Status != VIT_SUCCESS)
{
return VIT_Status;
}
VIT_Status = VIT_ModelInfo();
if (VIT_Status != VIT_SUCCESS)
{
return VIT_Status;
}
/*
* Configure VIT Instance Parameters
*/
VITInstParams.SampleRate_Hz = VIT_SAMPLE_RATE;
VITInstParams.SamplesPerFrame = VIT_SAMPLES_PER_FRAME;
VITInstParams.NumberOfChannel = NUMBER_OF_CHANNELS;
VITInstParams.DeviceId = DEVICE_ID;
/*
* VIT get memory table: Get size info per memory type
*/
VIT_Status = VIT_GetMemoryTable(PL_NULL, // VITHandle param should be NULL
&VITMemoryTable, &VITInstParams);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_GetMemoryTable error: %d\r\n", VIT_Status);
return VIT_Status;
}
/* Initialize order variable */
for (i = 0; i < PL_NR_MEMORY_REGIONS; i++)
{
order[i] = i;
}
/* Sort region indexes by region size */
for (i = 0; i < (PL_NR_MEMORY_REGIONS - 1); i++)
{
minIdx = i;
for (j = i + 1; j < PL_NR_MEMORY_REGIONS; j++)
if (VITMemoryTable.Region[order[j]].Size < VITMemoryTable.Region[order[minIdx]].Size)
minIdx = j;
/* Swap indexes */
temp32 = order[minIdx];
order[minIdx] = order[i];
order[i] = temp32;
}
/*
* Reserve memory space: Malloc for each memory type
*/
for (j = (PL_NR_MEMORY_REGIONS - 1); j >= 0; j--)
{
/* Log the memory size */
if (VITMemoryTable.Region[order[j]].Size != 0)
{
// reserve memory space
// NB: VITMemoryTable.Region[PL_MEMREGION_PERSISTENT_FAST_DATA] should be allocated
// in the fastest memory of the platform (when possible) - this is not the case in this example.
pMemory[j] = OSA_MemoryAllocate(VITMemoryTable.Region[order[j]].Size + MEMORY_ALIGNMENT);
if (!pMemory[j])
{
return VIT_INVALID_NULLADDRESS;
}
VITMemoryTable.Region[order[j]].pBaseAddress = (void *)pMemory[j];
}
}
/*
* Create VIT Instance
*/
VITHandle = PL_NULL; // force to null address for correct memory initialization
VIT_Status = VIT_GetInstanceHandle(&VITHandle, &VITMemoryTable, &VITInstParams);
if (VIT_Status != VIT_SUCCESS)
{
InitPhase_Error = PL_TRUE;
PRINTF("VIT_GetInstanceHandle error: %d\r\n", VIT_Status);
}
/*
* Test the reset (OPTIONAL)
*/
if (!InitPhase_Error)
{
VIT_Status = VIT_ResetInstance(VITHandle);
if (VIT_Status != VIT_SUCCESS)
{
InitPhase_Error = PL_TRUE;
PRINTF("VIT_ResetInstance error: %d\r\n", VIT_Status);
}
}
/*
* Set and Apply VIT control parameters
*/
VITControlParams.OperatingMode = VIT_OPERATING_MODE;
VITControlParams.MIC1_MIC2_Distance = VIT_MIC1_MIC2_DISTANCE;
VITControlParams.MIC1_MIC3_Distance = VIT_MIC1_MIC3_DISTANCE;
VITControlParams.Command_Time_Span = VIT_CMD_TIME_SPAN;
if (!InitPhase_Error)
{
VIT_Status = VIT_SetControlParameters(VITHandle, &VITControlParams);
if (VIT_Status != VIT_SUCCESS)
{
InitPhase_Error = PL_TRUE;
PRINTF("VIT_SetControlParameters error: %d\r\n", VIT_Status);
}
}
/*
//Public call to VIT_GetStatusParameters
VIT_StatusParams_st* pVIT_StatusParam_Buffer = (VIT_StatusParams_st*)&VIT_StatusParams_Buffer;
VIT_GetStatusParameters(VITHandle, pVIT_StatusParam_Buffer, sizeof(VIT_StatusParams_Buffer));
PRINTF("\nVIT Status Params\n");
PRINTF(" VIT LIB Release = 0x%04x\n", pVIT_StatusParam_Buffer->VIT_LIB_Release);
PRINTF(" VIT Model Release = 0x%04x\n", pVIT_StatusParam_Buffer->VIT_MODEL_Release);
PRINTF(" VIT Features supported by the lib = 0x%04x\n", pVIT_StatusParam_Buffer->VIT_Features_Supported);
PRINTF(" VIT Features Selected = 0x%04x\n", pVIT_StatusParam_Buffer->VIT_Features_Selected);
PRINTF(" Number of channels supported by VIT lib = %d\n", pVIT_StatusParam_Buffer->NumberOfChannels_Supported);
PRINTF(" Number of channels selected = %d\n", pVIT_StatusParam_Buffer->NumberOfChannels_Selected);
PRINTF(" Device Selected: device id = %d\n", pVIT_StatusParam_Buffer->Device_Selected);
if (pVIT_StatusParam_Buffer->WakeWord_In_Text2Model)
{
PRINTF(" VIT WakeWord in Text2Model\n ");
}
else
{
PRINTF(" VIT WakeWord in Audio2Model\n ");
}
*/
return VIT_Status;
}
int VIT_Execute(void *arg, void *inputBuffer, int size)
{
VIT_ReturnStatus_en VIT_Status;
VIT_VoiceCommand_st VoiceCommand; // Voice Command info
VIT_WakeWord_st WakeWord; // Wakeword info
VIT_DetectionStatus_en VIT_DetectionResults = VIT_NO_DETECTION; // VIT detection result
if (size != VIT_SAMPLES_PER_FRAME * NUMBER_OF_CHANNELS * BYTE_DEPTH)
{
PRINTF("Input buffer format issue\r\n");
return VIT_INVALID_FRAME_SIZE;
}
#if DEMO_CODEC_CS42448 || PLATFORM_RT1170 || PLATFORM_RT1160
DeInterleave(inputBuffer, DeInterleavedBuffer, VIT_SAMPLES_PER_FRAME, DEMO_CHANNEL_NUM);
#endif
/*
* VIT Process
*/
// Current VIT library is supporting only one channel
// VIT_InputBuffers.pBuffer_Chan1 should be set to the input buffer address
// VIT_InputBuffers.pBuffer_Chan1 setting can be done out of the while loop
// Application should take care of the ping pong buffers (when present) handling - no pingpong buffer in this
// example app.
if (VITInstParams.NumberOfChannel == _1CHAN)
{
#if PLATFORM_RT1170 || PLATFORM_RT1160
VIT_InputBuffers.pBuffer_Chan1 = DeInterleavedBuffer;
#else
VIT_InputBuffers.pBuffer_Chan1 = (PL_INT16 *)inputBuffer; // PCM buffer: 16-bit - 16kHz - mono
#endif
VIT_InputBuffers.pBuffer_Chan2 = PL_NULL;
VIT_InputBuffers.pBuffer_Chan3 = PL_NULL;
}
#if DEMO_CODEC_CS42448
if (VITInstParams.NumberOfChannel == _2CHAN)
{
VIT_InputBuffers.pBuffer_Chan1 =
&DeInterleavedBuffer[VIT_SAMPLES_PER_FRAME * 4]; // PCM buffer: 16-bit - 16kHz - mono
VIT_InputBuffers.pBuffer_Chan2 = &DeInterleavedBuffer[VIT_SAMPLES_PER_FRAME * 5];
VIT_InputBuffers.pBuffer_Chan3 = PL_NULL;
}
#endif
VIT_Status = VIT_Process(VITHandle,
&VIT_InputBuffers, // temporal audio input data
&VIT_DetectionResults);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_Process error: %d\r\n", VIT_Status);
return VIT_Status; // will stop processing VIT and go directly to MEM free
}
if (VIT_DetectionResults == VIT_WW_DETECTED)
{
// Retrieve id of the WakeWord detected
// String of the Command can also be retrieved (when WW and CMDs strings are integrated in Model)
VIT_Status = VIT_GetWakeWordFound(VITHandle, &WakeWord);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_GetWakeWordFound error : %d\r\n", VIT_Status);
return VIT_Status; // will stop processing VIT and go directly to MEM free
}
else
{
PRINTF(" - WakeWord detected %d", WakeWord.WW_Id);
// Retrieve WakeWord Name : OPTIONAL
// Check first if WakeWord string is present
if (WakeWord.pWW_Name != PL_NULL)
{
PRINTF(" %s\r\n", WakeWord.pWW_Name);
}
}
}
else if (VIT_DetectionResults == VIT_VC_DETECTED)
{
// Retrieve id of the Voice Command detected
// String of the Command can also be retrieved (when WW and CMDs strings are integrated in Model)
VIT_Status = VIT_GetVoiceCommandFound(VITHandle, &VoiceCommand);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_GetVoiceCommandFound error: %d\r\n", VIT_Status);
return VIT_Status; // will stop processing VIT and go directly to MEM free
}
else
{
PRINTF(" - Voice Command detected %d", VoiceCommand.Cmd_Id);
// Retrieve CMD Name: OPTIONAL
// Check first if CMD string is present
if (VoiceCommand.pCmd_Name != PL_NULL)
{
PRINTF(" %s\r\n", VoiceCommand.pCmd_Name);
}
else
{
PRINTF("\r\n");
}
}
}
return VIT_Status;
}
int VIT_Deinit(void)
{
VIT_ReturnStatus_en VIT_Status; /* Function call status */
// retrieve size of the different MEM tables allocated
VIT_Status =
VIT_GetMemoryTable(VITHandle, // Should provide VIT_Handle to retrieve the size of the different MemTabs
&VITMemoryTable, &VITInstParams);
if (VIT_Status != VIT_SUCCESS)
{
PRINTF("VIT_GetMemoryTable error: %d\r\n", VIT_Status);
}
// Free the MEM tables
for (int i = 0; i < PL_NR_MEMORY_REGIONS; i++)
{
if (pMemory[i] != NULL)
{
OSA_MemoryFree((PL_INT8 *)pMemory[i]);
pMemory[i] = NULL;
}
}
return VIT_Status;
}
// de-Interleave Multichannel signal
// example: A1.B1.C1.A2.B2.C2.A3.B3.C3....An.Bn.Cn (3 Channels case : A, B, C)
// will become
// A1.A2.A3....An.B1.B2.B3....Bn.C1.C2.C3....Cn
// Simple helper function for de-interleaving Multichannel stream
// The caller function shall ensure that all arguments are correct.
// This function assumes the input data as 32 bit width and transforms it into 16 bit width
void DeInterleave(const PL_INT16 *pDataInput, PL_INT16 *pDataOutput, PL_UINT16 FrameSize, PL_UINT16 ChannelNumber)
{
for (PL_UINT16 ichan = 0; ichan < ChannelNumber; ichan++)
{
for (PL_UINT16 i = 0; i < FrameSize; i++)
{
/* Select the 16 MSB of the 32 input bits */
pDataOutput[i + (ichan * FrameSize)] = pDataInput[(i * 2 * ChannelNumber) + (ichan * 2) + 1];
}
}
return;
}
VIT_Initialize_T VIT_Initialize_func = VIT_Initialize;
VIT_Execute_T VIT_Execute_func = VIT_Execute;
VIT_Deinit_T VIT_Deinit_func = VIT_Deinit;
VIT_Language_T Vit_Language;

30
boards/evkbimxrt1050/audio_examples/maestro_record/vit_proc.h Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _VIT_PROC_H_
#define _VIT_PROC_H_
#include "PL_platformTypes_CortexM.h"
#include "VIT.h"
typedef int (*VIT_Initialize_T)(void *arg);
typedef int (*VIT_Execute_T)(void *arg, void *inputBuffer, int size);
typedef int (*VIT_Deinit_T)(void);
void DeInterleave(const PL_INT16 *pDataInput, PL_INT16 *pDataOutput, PL_UINT16 FrameSize, PL_UINT16 ChannelNumber);
extern VIT_Initialize_T VIT_Initialize_func;
extern VIT_Execute_T VIT_Execute_func;
extern VIT_Deinit_T VIT_Deinit_func;
typedef enum
{
EN,
CN
} VIT_Language_T;
extern VIT_Language_T Vit_Language;
#endif

8
boards/evkbimxrt1050/audio_examples/maestro_usb_mic/armgcc/flags.cmake
View File

@ -29,10 +29,14 @@ SET(CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG " \
-DSTREAMER_ENABLE_EAP \
-DSTREAMER_ENABLE_VIT_SINK \
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DSERIAL_PORT_TYPE_UART=1 \
-DSDK_OS_FREE_RTOS \
@ -72,10 +76,14 @@ SET(CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE " \
-DSTREAMER_ENABLE_EAP \
-DSTREAMER_ENABLE_VIT_SINK \
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DSERIAL_PORT_TYPE_UART=1 \
-DSDK_OS_FREE_RTOS \

4
boards/evkbimxrt1050/audio_examples/maestro_usb_mic/maestro_usb_mic_v3_10.xml
View File

@ -85,10 +85,14 @@
<value>STREAMER_ENABLE_EAP</value>
<value>STREAMER_ENABLE_VIT_SINK</value>
<value>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</value>
<value>DEBUG_CONSOLE_TRANSFER_NON_BLOCKING</value>
<value>OSA_USED</value>
<value>SHELL_TASK_STACK_SIZE=4000</value>
<value>SDK_I2C_BASED_COMPONENT_USED=1</value>
<value>BOARD_USE_CODEC=1</value>
<value>CODEC_WM8960_ENABLE</value>
<value>SD_ENABLED</value>
<value>SAI_XFER_QUEUE_SIZE=2</value>
<value>DEBUG_CONSOLE_RX_ENABLE=0</value>
<value>SERIAL_PORT_TYPE_UART=1</value>
<value>SDK_OS_FREE_RTOS</value>

2
boards/evkbimxrt1050/audio_examples/maestro_usb_mic/main.c
View File

@ -128,7 +128,7 @@ void APP_Shell_Task(void *param)
/* Handle shell commands. Return when 'exit' command entered. */
shellCmd(handleShellMessage, param);
vTaskSuspend(NULL);
while (1)
;
}

7
boards/evkbimxrt1050/audio_examples/maestro_usb_mic/usb_device_ch9.c
View File

@ -992,7 +992,12 @@ static usb_status_t USB_DeviceControlCallback(usb_device_handle handle,
uint8_t state = 0U;
/* endpoint callback length is USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) when transfer is canceled */
if ((USB_CANCELLED_TRANSFER_LENGTH == message->length) || (NULL == callbackParam))
if (USB_CANCELLED_TRANSFER_LENGTH == message->length)
{
return kStatus_USB_Success;
}
if (NULL == callbackParam)
{
return status;
}

8
boards/evkbimxrt1050/audio_examples/maestro_usb_speaker/armgcc/flags.cmake
View File

@ -29,10 +29,14 @@ SET(CMAKE_C_FLAGS_FLEXSPI_NOR_DEBUG " \
-DSTREAMER_ENABLE_EAP \
-DSTREAMER_ENABLE_VIT_SINK \
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DSERIAL_PORT_TYPE_UART=1 \
-DSDK_OS_FREE_RTOS \
@ -72,10 +76,14 @@ SET(CMAKE_C_FLAGS_FLEXSPI_NOR_RELEASE " \
-DSTREAMER_ENABLE_EAP \
-DSTREAMER_ENABLE_VIT_SINK \
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
-DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING \
-DOSA_USED \
-DSHELL_TASK_STACK_SIZE=4000 \
-DSDK_I2C_BASED_COMPONENT_USED=1 \
-DBOARD_USE_CODEC=1 \
-DCODEC_WM8960_ENABLE \
-DSD_ENABLED \
-DSAI_XFER_QUEUE_SIZE=2 \
-DDEBUG_CONSOLE_RX_ENABLE=0 \
-DSERIAL_PORT_TYPE_UART=1 \
-DSDK_OS_FREE_RTOS \

4
boards/evkbimxrt1050/audio_examples/maestro_usb_speaker/maestro_usb_speaker_v3_10.xml
View File

@ -85,10 +85,14 @@
<value>STREAMER_ENABLE_EAP</value>
<value>STREAMER_ENABLE_VIT_SINK</value>
<value>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</value>
<value>DEBUG_CONSOLE_TRANSFER_NON_BLOCKING</value>
<value>OSA_USED</value>
<value>SHELL_TASK_STACK_SIZE=4000</value>
<value>SDK_I2C_BASED_COMPONENT_USED=1</value>
<value>BOARD_USE_CODEC=1</value>
<value>CODEC_WM8960_ENABLE</value>
<value>SD_ENABLED</value>
<value>SAI_XFER_QUEUE_SIZE=2</value>
<value>DEBUG_CONSOLE_RX_ENABLE=0</value>
<value>SERIAL_PORT_TYPE_UART=1</value>
<value>SDK_OS_FREE_RTOS</value>

2
boards/evkbimxrt1050/audio_examples/maestro_usb_speaker/main.c
View File

@ -128,7 +128,7 @@ void APP_Shell_Task(void *param)
/* Handle shell commands. Return when 'exit' command entered. */
shellCmd(handleShellMessage, param);
vTaskSuspend(NULL);
while (1)
;
}

24
boards/evkbimxrt1050/audio_examples/maestro_usb_speaker/streamer_pcm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -118,19 +118,15 @@ int streamer_pcm_write(pcm_rtos_t *pcm, uint8_t *data, uint32_t size)
DCACHE_CleanByRange((uint32_t)pcm->saiTx.data, pcm->saiTx.dataSize);
if (pcm->isFirstTx)
{
pcm->isFirstTx = 0;
}
else
{
/* Wait for the previous transfer to finish */
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
return -1;
}
/* Start the consecutive transfer */
SAI_TransferSendEDMA(DEMO_SAI, &pcm->saiTxHandle, &pcm->saiTx);
while (SAI_TransferSendEDMA(DEMO_SAI, &pcm->saiTxHandle, &pcm->saiTx) == kStatus_SAI_QueueFull)
{
/* Wait for transfer to finish */
if (xSemaphoreTake(pcm->semaphoreTX, portMAX_DELAY) != pdTRUE)
{
return -1;
}
}
return 0;
}
@ -256,7 +252,6 @@ int streamer_pcm_setparams(pcm_rtos_t *pcm,
sai_transceiver_t saiConfig;
uint32_t masterClockHz = 0U;
pcm->isFirstTx = transfer ? 1U : pcm->isFirstTx;
pcm->sample_rate = sample_rate;
pcm->bit_width = bit_width;
pcm->num_channels = num_channels;
@ -302,6 +297,7 @@ int streamer_pcm_setparams(pcm_rtos_t *pcm,
/* I2S transfer mode configurations */
if (transfer)
{
SAI_TransferTerminateSendEDMA(DEMO_SAI, &pcm->saiTxHandle);
SAI_GetClassicI2SConfig(&saiConfig, _pcm_map_word_width(bit_width), format.stereo, 1U << DEMO_SAI_CHANNEL);
saiConfig.syncMode = kSAI_ModeAsync;

4
boards/evkbimxrt1050/audio_examples/maestro_usb_speaker/streamer_pcm_app.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -32,8 +32,6 @@ struct _pcm_rtos_t
uint8_t num_channels;
SemaphoreHandle_t semaphoreTX;
uint8_t isFirstTx;
};
#endif

7
boards/evkbimxrt1050/audio_examples/maestro_usb_speaker/usb_device_ch9.c
View File

@ -992,7 +992,12 @@ static usb_status_t USB_DeviceControlCallback(usb_device_handle handle,
uint8_t state = 0U;
/* endpoint callback length is USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) when transfer is canceled */
if ((USB_CANCELLED_TRANSFER_LENGTH == message->length) || (NULL == callbackParam))
if (USB_CANCELLED_TRANSFER_LENGTH == message->length)
{
return kStatus_USB_Success;
}
if (NULL == callbackParam)
{
return status;
}

3
boards/evkbimxrt1050/aws_examples/aws_httpscli_corehttp/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/aws_httpscli_corehttp/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/aws_httpscli_corehttp/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

30
boards/evkbimxrt1050/aws_examples/aws_tests_wifi_nxp/app_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -7,8 +7,6 @@
/*
* Supported Wi-Fi boards (modules):
* WIFI_88W8977_BOARD_PAN9026_SDIO
* WIFI_88W8977_BOARD_AW_AM281_USD
* WIFI_88W8801_BOARD_AW_NM191_USD
* WIFI_IW416_BOARD_AW_AM457_USD
* WIFI_IW416_BOARD_AW_AM510_USD
@ -16,8 +14,6 @@
* WIFI_88W8801_BOARD_MURATA_2DS_USD
* WIFI_IW416_BOARD_MURATA_1XK_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_M2
* WIFI_BOARD_IW61x
*/
/* @TEST_ANCHOR */
#define WIFI_IW416_BOARD_AW_AM510_USD
@ -25,30 +21,8 @@
/* Wi-Fi boards configuration list */
/* Panasonic PAN9026 SDIO ADAPTER */
#if defined(WIFI_88W8977_BOARD_PAN9026_SDIO)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define SDMMCHOST_OPERATION_VOLTAGE_3V3
#define SD_CLOCK_MAX (25000000U)
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* Azurewave AW-AM281-uSD */
#elif defined(WIFI_88W8977_BOARD_AW_AM281_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* AzureWave AW-NM191-uSD */
#elif defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#if defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8801
#define SDMMCHOST_OPERATION_VOLTAGE_1V8

3
boards/evkbimxrt1050/aws_examples/aws_tests_wifi_nxp/mcux/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/aws_tests_wifi_nxp/mcux/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/aws_tests_wifi_nxp/mcux/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

2
boards/evkbimxrt1050/aws_examples/aws_tests_wifi_nxp/wifi_config.h
View File

@ -12,7 +12,7 @@
#define CONFIG_MAX_AP_ENTRIES 1
#if defined(SD8977) || defined(SD8978) || defined(SD8987)
#if defined(SD8978) || defined(SD8987)
#define CONFIG_5GHz_SUPPORT 1
#endif

3
boards/evkbimxrt1050/aws_examples/greengrass_discovery_enet/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/greengrass_discovery_enet/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/greengrass_discovery_enet/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

30
boards/evkbimxrt1050/aws_examples/greengrass_discovery_wifi_nxp/app_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -7,8 +7,6 @@
/*
* Supported Wi-Fi boards (modules):
* WIFI_88W8977_BOARD_PAN9026_SDIO
* WIFI_88W8977_BOARD_AW_AM281_USD
* WIFI_88W8801_BOARD_AW_NM191_USD
* WIFI_IW416_BOARD_AW_AM457_USD
* WIFI_IW416_BOARD_AW_AM510_USD
@ -16,8 +14,6 @@
* WIFI_88W8801_BOARD_MURATA_2DS_USD
* WIFI_IW416_BOARD_MURATA_1XK_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_M2
* WIFI_BOARD_IW61x
*/
/* @TEST_ANCHOR */
#define WIFI_IW416_BOARD_AW_AM510_USD
@ -25,30 +21,8 @@
/* Wi-Fi boards configuration list */
/* Panasonic PAN9026 SDIO ADAPTER */
#if defined(WIFI_88W8977_BOARD_PAN9026_SDIO)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define SDMMCHOST_OPERATION_VOLTAGE_3V3
#define SD_CLOCK_MAX (25000000U)
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* Azurewave AW-AM281-uSD */
#elif defined(WIFI_88W8977_BOARD_AW_AM281_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* AzureWave AW-NM191-uSD */
#elif defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#if defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8801
#define SDMMCHOST_OPERATION_VOLTAGE_1V8

3
boards/evkbimxrt1050/aws_examples/greengrass_discovery_wifi_nxp/mcux/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/greengrass_discovery_wifi_nxp/mcux/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/greengrass_discovery_wifi_nxp/mcux/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

2
boards/evkbimxrt1050/aws_examples/greengrass_discovery_wifi_nxp/wifi_config.h
View File

@ -12,7 +12,7 @@
#define CONFIG_MAX_AP_ENTRIES 1
#if defined(SD8977) || defined(SD8978) || defined(SD8987)
#if defined(SD8978) || defined(SD8987)
#define CONFIG_5GHz_SUPPORT 1
#endif

3
boards/evkbimxrt1050/aws_examples/ota_demo_enet/mcux/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/ota_demo_enet/mcux/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/ota_demo_enet/mcux/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

30
boards/evkbimxrt1050/aws_examples/ota_demo_wifi/app_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -7,8 +7,6 @@
/*
* Supported Wi-Fi boards (modules):
* WIFI_88W8977_BOARD_PAN9026_SDIO
* WIFI_88W8977_BOARD_AW_AM281_USD
* WIFI_88W8801_BOARD_AW_NM191_USD
* WIFI_IW416_BOARD_AW_AM457_USD
* WIFI_IW416_BOARD_AW_AM510_USD
@ -16,8 +14,6 @@
* WIFI_88W8801_BOARD_MURATA_2DS_USD
* WIFI_IW416_BOARD_MURATA_1XK_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_M2
* WIFI_BOARD_IW61x
*/
/* @TEST_ANCHOR */
#define WIFI_IW416_BOARD_AW_AM510_USD
@ -25,30 +21,8 @@
/* Wi-Fi boards configuration list */
/* Panasonic PAN9026 SDIO ADAPTER */
#if defined(WIFI_88W8977_BOARD_PAN9026_SDIO)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define SDMMCHOST_OPERATION_VOLTAGE_3V3
#define SD_CLOCK_MAX (25000000U)
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* Azurewave AW-AM281-uSD */
#elif defined(WIFI_88W8977_BOARD_AW_AM281_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* AzureWave AW-NM191-uSD */
#elif defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#if defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8801
#define SDMMCHOST_OPERATION_VOLTAGE_1V8

3
boards/evkbimxrt1050/aws_examples/ota_demo_wifi/mcux/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/ota_demo_wifi/mcux/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/ota_demo_wifi/mcux/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

2
boards/evkbimxrt1050/aws_examples/ota_demo_wifi/wifi_config.h
View File

@ -12,7 +12,7 @@
#define CONFIG_MAX_AP_ENTRIES 1
#if defined(SD8977) || defined(SD8978) || defined(SD8987)
#if defined(SD8978) || defined(SD8987)
#define CONFIG_5GHz_SUPPORT 1
#endif

3
boards/evkbimxrt1050/aws_examples/remote_control_enet/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/remote_control_enet/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/remote_control_enet/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

30
boards/evkbimxrt1050/aws_examples/remote_control_wifi_nxp/app_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -7,8 +7,6 @@
/*
* Supported Wi-Fi boards (modules):
* WIFI_88W8977_BOARD_PAN9026_SDIO
* WIFI_88W8977_BOARD_AW_AM281_USD
* WIFI_88W8801_BOARD_AW_NM191_USD
* WIFI_IW416_BOARD_AW_AM457_USD
* WIFI_IW416_BOARD_AW_AM510_USD
@ -16,8 +14,6 @@
* WIFI_88W8801_BOARD_MURATA_2DS_USD
* WIFI_IW416_BOARD_MURATA_1XK_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_M2
* WIFI_BOARD_IW61x
*/
/* @TEST_ANCHOR */
#define WIFI_IW416_BOARD_AW_AM510_USD
@ -25,30 +21,8 @@
/* Wi-Fi boards configuration list */
/* Panasonic PAN9026 SDIO ADAPTER */
#if defined(WIFI_88W8977_BOARD_PAN9026_SDIO)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define SDMMCHOST_OPERATION_VOLTAGE_3V3
#define SD_CLOCK_MAX (25000000U)
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* Azurewave AW-AM281-uSD */
#elif defined(WIFI_88W8977_BOARD_AW_AM281_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* AzureWave AW-NM191-uSD */
#elif defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#if defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8801
#define SDMMCHOST_OPERATION_VOLTAGE_1V8

3
boards/evkbimxrt1050/aws_examples/remote_control_wifi_nxp/mcux/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/remote_control_wifi_nxp/mcux/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/remote_control_wifi_nxp/mcux/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

2
boards/evkbimxrt1050/aws_examples/remote_control_wifi_nxp/wifi_config.h
View File

@ -12,7 +12,7 @@
#define CONFIG_MAX_AP_ENTRIES 1
#if defined(SD8977) || defined(SD8978) || defined(SD8987)
#if defined(SD8978) || defined(SD8987)
#define CONFIG_5GHz_SUPPORT 1
#endif

3
boards/evkbimxrt1050/aws_examples/shadow_enet/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/shadow_enet/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/shadow_enet/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

30
boards/evkbimxrt1050/aws_examples/shadow_wifi_nxp/app_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -7,8 +7,6 @@
/*
* Supported Wi-Fi boards (modules):
* WIFI_88W8977_BOARD_PAN9026_SDIO
* WIFI_88W8977_BOARD_AW_AM281_USD
* WIFI_88W8801_BOARD_AW_NM191_USD
* WIFI_IW416_BOARD_AW_AM457_USD
* WIFI_IW416_BOARD_AW_AM510_USD
@ -16,8 +14,6 @@
* WIFI_88W8801_BOARD_MURATA_2DS_USD
* WIFI_IW416_BOARD_MURATA_1XK_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_USD
* WIFI_88W8987_BOARD_MURATA_1ZM_M2
* WIFI_BOARD_IW61x
*/
/* @TEST_ANCHOR */
#define WIFI_IW416_BOARD_AW_AM510_USD
@ -25,30 +21,8 @@
/* Wi-Fi boards configuration list */
/* Panasonic PAN9026 SDIO ADAPTER */
#if defined(WIFI_88W8977_BOARD_PAN9026_SDIO)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define SDMMCHOST_OPERATION_VOLTAGE_3V3
#define SD_CLOCK_MAX (25000000U)
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* Azurewave AW-AM281-uSD */
#elif defined(WIFI_88W8977_BOARD_AW_AM281_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8977
#define WIFI_BT_USE_USD_INTERFACE
#define WLAN_ED_MAC_CTRL \
{ \
.ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
}
/* AzureWave AW-NM191-uSD */
#elif defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#if defined(WIFI_88W8801_BOARD_AW_NM191_USD)
#define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
#define SD8801
#define SDMMCHOST_OPERATION_VOLTAGE_1V8

3
boards/evkbimxrt1050/aws_examples/shadow_wifi_nxp/mcux/linkscripts/bss.ldt Normal file
View File

@ -0,0 +1,3 @@
<#if memory.name=="SRAM_OC">
*(.bss*)
</#if>

4
boards/evkbimxrt1050/aws_examples/shadow_wifi_nxp/mcux/linkscripts/data.ldt Normal file
View File

@ -0,0 +1,4 @@
<#if memory.name=="SRAM_ITC">
*mflash_drv.o(.text .text* .rodata .rodata*)
*fsl_flexspi.o(.text .text* .rodata .rodata*)
</#if>

1
boards/evkbimxrt1050/aws_examples/shadow_wifi_nxp/mcux/linkscripts/main_text.ldt Normal file
View File

@ -0,0 +1 @@
*(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o) .text*)

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