Have arm_set_cpsr() handle the two core state flags, updating
the CPU state. This eliminates code in various debug_entry()
paths, and marginally improves handling of the J bit.
Catch and comment a few holes in the handling of the J bit on
ARM926ejs cores ... it's unlikely our users will care about
Jazelle mode, but we can at least warn of Impending Doom. If
anyone does use it, these breadcrumbs may help them to find
the right path through the code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Define arm_reg_current() ... returning handle to a given register,
and encapsulating the current mode's register shadowing. It's got
one current use, for reporting the current register set to GDB.
This will let later patches clean up much ARMV4_5_CORE_REG_MODE()
nastiness, saving a bit of code.
Define and use arm_set_cpsr() ... initially it updates the cached
CPSR and sets up state used by arm_reg_current(), plus any SPSR
handle. (Later: can also set up for T and J bits.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Stash a pointer to the CPSR in the "struct arm", to help get rid
of the (common) references to its index in the register cache.
This removes almost all references to CPSR offsets outside of the
toplevel ARM code ... except a pair related to the current ARM11
"simulator" logic (which should be removable soonish).
This is a net minor code shrink of a few hundred bytes of object
code, and also makes the code more readable.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Implementations need to access the register struct they modify;
make it easier and less error-prone to identify the instance.
(This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...)
Plus some minor fixes noted when making these updates: ARM7/ARM9
accessor methods should be static; don't leave CPSR wrongly marked
"dirty"; note significant XScale omissions in register handling;
and have armv4_5_build_reg_cache() record its result.
Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used
for more than those older architecture generations.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:
- armv4_5_invalidate_core_regs()
- armv7m_invalidate_core_regs
- mips32_invalidate_core_regs() too.
Make cache->num_regs be unsigned, avoiding various errors.
Net code shrink and simplification.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Just pre-allocate memory for the cached register value.
Shrinks heap overhead; increases locality-of-reference.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Combine register names with other per-register data into a
single template structure. This saves space, and makes it
easier to change how registers get handled (by shrinking
the number of places that care about cache indices).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We don't want an ARMv7-specific core state enumeration just to
add ThumbEE state. Update the generic stuff to handle that,
and replace the V7-specific bits with it.
For Cortex-A8: on debug entry, check both the T and J bits
instead of just the T bit. When the J bit is set, set the
right state and warn appropriately.
(And while we're at it, move the generic arm struct to the front
of the v7a structure, for somewhat better code generation.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Change the layout to show the "Secure Monitor" registers too,
when they're present.
Instead of lining registers for each of six (or seven) modes up
in adjacent vertical columns, display each mode's registers (or
shadows) in a single block, avoiding duplicate value displays.
This also lets us shrink the line length to fits in standard 80
character lines ... six or seven 18-character columns can't fit.
Relabel "r13" as "sp", so it's more meaningful.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
If the core doesn't provide an optimized version of this
method, provide one without core-specific optimizations.
Use this to make Cortex-A8 support the "arm reg" command.
Related: make the two register access methods properly static,
have the "set" log a "not halted" error too, and make sure
that the "valid" flag is set on successful reads.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Teach the "armv4_5" register code to understand about the
secure monitor mode:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Catch malloc/calloc failures building that register cache
This should kick in for Cortex-A8 and ARM1176.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
It's used to flag cores with the "TrustZone" extension,
and is used in subsequent patches to set up support for
the registers shadowed by its new secure monitor mode.
The ARM1176 and Cortex-A8 both support this new mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add a new is_arm_mode() predicate, and use it to replace almost
all calls to current armv4_5_mode_to_number().
Eventually those internal mode numbers should vanish... along
with their siblings in the armv7a.c file.
Remove a handful of superfluous checks ... e.g. the mode number
was just initialized, or (debug entry methods) already validated.
Move one of the macros using internal mode numbers into the only
file which uses that macro. Make the tables manipulated with
those numbers be read-only and, where possible, static so they're
not confused with part of the generic ARM interface.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add and use arm_mode_name() to map from PSR bits to user
meaningful names. It uses a new table which, later, can
be used to hold other mode-coupled data.
Add definitions for the "Secure Monitor" mode, as seen on
some ARM11 cores (like ARM1176) and on Cortex-A8. The
previous mode name scheme didn't understand that mode.
Remove the old mechanism ... there were two copies, caused
by Cortex-A8 needing to add "Secure Monitor" mode support.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
All ARM cores need to provide obsolete FPA registers in their
GDB register dumps. (Even though cores with floating point
support now generally use some version of VFP...)
Clean up that support a bit by sharing the same dummy registers,
and removing the duplicate copies. Eventually we shouldn't need
to export those dummies.
(This makes the ARMv7-M support include the armv4_5 header, and
cleans up related #includes, but doesn't yet use anything from
there except those dummies.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
No need to indirect from registered integers to pointers.
Just stash the pointers directly in the register struct,
and don't even bother registering.
This is a small code shrink, speeds register access just
a smidgeon, and gets rid of another rude exit() path.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Have ARM11 register the "standard" ARM commands. For now, only
disassembly really works.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rename the "armv4_5" command prefix to straight "arm" so it makes
more sense for newer cores. Add a simple compatibility script.
Make sure all the commands give the same "not an ARM" diagnostic
message (and fail properly) when called against non-ARM targets.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Tweak "standard" ARM disassembler diagnostics to fail if the target
is not "an ARM" (vs. not "an ARMV4/5"), so it makes more sense for
cores inheriting this as the "generic" disassembler.
Also, to use the Thumb2 entry instead of the original Thumb entry.
This makes it work better for both newer cores (which support those
added instructions) and for BL and BLX instructions on older cores.
(Those instructions are 32-bits, which requires curious state-aware
code to go through a 16-bit decode interface...)
Plus minor cleanups, notably to have fewer exit paths and to make
sure they all return failure codes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
They're really too big to inline, at least for code that's
not in any performance-critical loops.
Also move the associated string table to the rodata section.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Don't include it in more headers than necessary; just
use it in the few files that actually need it.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The ARRAY_SIZE macro was defined in several target files, so move it
to types.h.
This patch also removes two other identical macros: DIM (from jtag.h)
and asizeof (from arm11.h).
Same deal: "register.h" got needlessly included all over the
place because of being in a few widely included headers.
So take it out of the header files which included it, and put
it in files which use it ... reduce needless interdependencies.
Also, don't need that extra "types.h" inclusion.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Most files in the tree seem to have ended up including this,
and *quite* needlessly ... only code implementing or using
downloadable algorithms actually needs these declarations.
So take it out of the header files which included it, and put
it in files which use it ... reduce needless interdependencies.
Also: "algorithm.h" doesn't need to include "types.h" again;
it already comes from a different header.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Most files in the tree seem to have ended up including this,
and *quite* needlessly ... only code implementing or using
breakpoints actually needs these declarations.
So take it out of the header files which included it, and put
it in files which use it ... reduce needless interdependencies.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The arm7_9_checksum_memory() and arm7_9_blank_check_memory()
routines are not actually specific to the ARM7 and ARM9 core
generations ... they can work for any core which can run
algorithms using basic ARM (not Thumb) instructions.
Rename them; move the declarations to a more generic site;
likewise move the code (and tidy it a bit in the process).
NOTE: the blank_check() method falsely returned a success
status (0) on one error path, when the algorithm failed.
Fixed this bug.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We have too many different registers, and too many version and
context dependent interpretations, for this type of bitfield
management to be scalable.
(Anyone who really wants bitfield interpretation *can* do that
in Tcl code...)
There are ... quite a few copies of the same ARM dummy registers.
There should eventually be one copy; this many is craziness.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Remove most remaining uses of target->arch_info from ARM
infrastructure, where it hasn't already been updated.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Optionally shave time off the armv4_5 run_algorithm() code: let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.
Enable this by using BKPT to terminate execution instead of "branch
to here" loops. Then pass zero as the exit address, except when
running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.
Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps. Some other algorithms
could use this too (mostly flavors of flash operation).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the key command_*() helper functions, fixng the bugs that turned up.
Several of these bugs were from misuse of PRIi64; that's for 64-bit
integers, NOT for "long long" or "u64" (which work best with %lld).
git-svn-id: svn://svn.berlios.de/openocd/trunk@1873 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- cleaned up headers to match rest of code
- added missing svn props for previously added files
git-svn-id: svn://svn.berlios.de/openocd/trunk@987 b42882b7-edfa-0310-969c-e2dbd0fdcd60
converts a number of 'simple string lookup tables' into NVP tables.
These NVP tables will be used by various commands coming in the next patch.
git-svn-id: svn://svn.berlios.de/openocd/trunk@962 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Wrote a default flash erase check fn which uses CFI's target algorithm
w/fallback to memory reads.
- "flash info" no longer prints erase status as it is stale.
- "flash erase_check" now prints erase status. erase check can take a
*long* time. Work in progress
- arm7/9 with seperate srst & trst now supports reset init/halt
after a power outage. arm7/9 no longer makes any assumptions
about state of target when reset is asserted.
- fixes for srst & trst capable arm7/9 with reset init/halt
- prepare_reset_halt retired. This code needs to be inside
assert_reset anyway
- haven't been able to get stm32 write algorithm to work. Fallback
flash write does work. Haven't found a version of openocd trunk
where this works.
- added target_free_all_working_areas_restore() which can
let be of restoring backups. This is needed when asserting
reset as the target must be assumed to be an unknown state.
Added some comments to working areas API
- str9 reset script fixes
- some guidelines
- fixed dangling callbacks upon reset timeout
git-svn-id: svn://svn.berlios.de/openocd/trunk@536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
are up and running. The examination and validation is actually
"optional" from the point of view of GDB + telnet servers.
Multiple targets should work fine with this.
- jtag_speed is dropped(divisor is increased), if jtag examination and
validation fails.
- the chain is validated 10x to catch the worst jtag_speed offences
- added LOG_SILENT that can be used to shut up log. Feeble
ersatz for try+catch.
- GDB register packets are now always replied in order to make sure
that GDB connect works. If the target is not halted, then these
packets contain dummy values.
git-svn-id: svn://svn.berlios.de/openocd/trunk@483 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- switch to synchronous halt during connect. This fixes the bug
where poll() was not invoked between halt() and servicing the
'g' register packet
- halt() no longer returns error code when target is already halted, just
logs a warning. Only the halt() implementation can say anything
meaningful about why a halt() failed, so error messages are pushed
up to halt()
- fixed soft_reset_halt infinite loop bug in arm7_9_common.c. The rest
of the implementations are still busted.
- by using USER() instead of command_print() the log gets the
source + line #. Nice.
- no longer invoke exit() if soft_reset_halt fails. A reset can often
fix the problem.
git-svn-id: svn://svn.berlios.de/openocd/trunk@475 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- added arch_state to show status of currently selected target
- simplified target->type->arch_state() api.
- clean up telnet output a bit
- fixed GDB output for arch_state
- removed a couple of unecessary exit()'s
- cleaned up error propagation a bit in a few places
git-svn-id: svn://svn.berlios.de/openocd/trunk@332 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- added virtual address to working_area.
- Improved error messages in a number of places
- Added ERROR_COMMAND_SYNTAX_ERROR that commands can return to have syntax printed
- Added help for some config commands
- Added verification of sw breakpoints with ERROR() message
- Removed a couple of exit()'s and replaced with error message
- cosmetic fix to armv4_5.c, easier to read
- added polymorphic(with default) virt2phys and mmu enable query function to target.h
- added virt2phys command that uses target->type->virt2phys() fn
Thanks to Øyvind Harboe
git-svn-id: svn://svn.berlios.de/openocd/trunk@310 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- output all of EmbeddedICE version register in error message
- update OpenOCD's idea of the current core mode, and immediately change core mode, on CPSR changes
- added support for CFI cmdset 0002 (patch by Andrew Dyer, thanks a lot)
- enhanced CFI cmdset 0002 support to Atmel AT49 flashes (thanks to Joerg Krein for providing test hardware)
git-svn-id: svn://svn.berlios.de/openocd/trunk@138 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c
- free working area and register stuff if str7x block write algorithm failed
- check PC after exiting a target algorithm in armv4_5.c
git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- str75x flash support (Thanks to Spencer Oliver)
- correct reporting of T-Bit in CPSR (Thanks to John Hartman for reporting this)
- core-state (ARM/Thumb) can be switched by modifying CPSR
- fixed bug in gdb_server register handling
- register values > 32-bit should now be supported
- several minor fixes and enhancements
git-svn-id: svn://svn.berlios.de/openocd/trunk@100 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- added access to ARM920T vector catch register (via generic register mechanism)
- don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache
- read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands)
- memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes)
- made in_handler independent from in field (makes the handler more flexible)
- added timeout to ft2232 when using D2XX library
- fixed STR7x protection bit handling on second bank (thanks to Bernard)
- added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen)
- fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen)
git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- fixed some small memory leaks (thanks to Spencer Oliver)
- verify chip- and buswidth of cfi flash configurations
- added support for ARM966E based systems (tested only with ST micro STR9, thanks to Spencer Oliver)
git-svn-id: svn://svn.berlios.de/openocd/trunk@81 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Added state-move support to ftd2xx and bitbang JTAG drivers (required for XScale, possibly useful for other targets, too)
- various fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@78 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- OpenOCD now includes the ability to diassemble instructions on its own (only ARM for now, Thumb might follow).
The command is "armv4_5 disassemble <address> <count> ['thumb']" (thumb is currently unsupported).
I've compared the produced disassembly against GDB/GNU Objdump output, and it seems to be correct, but there may still be some bugs left.
git-svn-id: svn://svn.berlios.de/openocd/trunk@68 b42882b7-edfa-0310-969c-e2dbd0fdcd60
