No major cross dependencies, mostly changes internal to each
file/function.
Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6338
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
The current implementation of OpenOCD does not support watchpoints for
cortex_a architecture. So, I replaced the add_watchpoint and
remove_watchpoint with the specific implementation for the
cortex a and using the breakpoint implementation and the arm
documentation [1] as reference. In particular, I have made the
following changes:
* added the following functions
- cortex_a_add_watchpoint
This wrapper function check whether there are any watchpoint
available on the target device by calling cortex_a_set_watchpoint.
- cortex_a_set_watchpoint
This function is responsible for settings the watchpoint register
pair. In particular, it sets the WVR and the WCR registers with
the cortex_a_dap command.
- cortex_a_remove_watchpoint
This wrapper function the selected watchpoint on the target device
by calling cortex_a_unset_watchpoint.
- cortex_a_unset_watchpoint
This function sets both the WVR and the WCR registers to zero, thus
unsetting the watchpoint.
[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html
Change-Id: I86611dab474cb84836662af572b17636dc68e282
Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-on: http://openocd.zylin.com/3913
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
The field 'wp_pc' was originally introduced in commit 55eeea7fce
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.
Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.
Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
There is no method to free the register cache, allocated in
armv4_5, so we get a memory leak.
Issue identified by valgrind.
Implement the method arm_free_reg_cache() and call it in cortex_a
deinit and to exit for error during arm_dpm_setup().
Tested on dual cortex-A stm32mp15x.
This change is inspired from similar fix in commit b01b5fe13a
("armv7m: Fix memory leak in register caching.").
The same allocation is also used by target types "arm7tdmi",
"arm9tdmi", "arm11" and "xscale" but they all lack the deinit
method and I do not have relevant HW to test the fix. For such
reasons they are not addressed in this patch.
Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5693
Tested-by: jenkins
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like parenthesis.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types SIZEOF_PARENTHESIS --fix-inplace -f {} \;
Change-Id: I8adb325bdb0e13211f8bae8b4770ec1979c176bf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5618
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
In a switch/case statement, a break placed after a goto or return
is never executed.
The script checkpatch available in Linux kernel v5.1 issues a
warning for such unused break statements.
In the process of reviewing the new checkpatch for its inclusion
in OpenOCD, let's get rid of these warnings.
The script checkpatch is unable to fixup automatically this case.
Thanks to having "break" command using a single code line, this
patch has been generated using the script below:
find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \
--types UNNECESSARY_BREAK -f {} \; \
| sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \
| awk 'function P() {print "sed -i '\''"b"'\'' "a};
{
if ($1!=a) {
if (a) {P()};
a=$1;
b=$2"{d}";
} else {
b=b";"$2"{d}"
}
};
END {P()}'
Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5617
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
The functions cortex_a_dap_{read,write}_coreregister_u32() are
duplicate of the functions dpm_{read,write}_reg().
Remove both duplicated functions in cortex_a.c while export only
dpm_read_reg(), since dpm_write_reg() is currently not used.
Rename dpm_read_reg() as arm_dpm_read_reg() to keep uniform the
naming style.
Change-Id: I501bc99dc402039e630c47917a086a0bb382782c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4747
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
The name of the function dpm_modeswitch() does not follow the
common style of the other function names in the same file.
Rename it as arm_dpm_modeswitch().
Change-Id: Idebf3c7bbddcd9b3c7b44f8d0dea1e5f7549b0eb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4756
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Neither the initial loop to clear dirty registers (which visits all
registers starting at R2 and counting upwards) nor the final explicit
flushes ensure a write-back in arm_dpm_write_dirty_registers.
This change makes sure that both our scratch registers (i.e. R0 and
R1) are written back to the target.
Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-on: http://openocd.zylin.com/4506
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This patch adds support in openOCD to read/write Arm vector/floating
point registers. This is compatible with Arm vfp v3 target xml in GDB.
Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml
Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4421
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
When ARM64 support was being merged, a comparison ended up being
inverted. This causes NULL pointer access when target attempts to
use core cache.
Change-Id: Ic8873ddd13dbdd8100856a71b4717f44cd336e23
Signed-off-by: Girts Folkmanis <opensource@girts.me>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4042
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Make DSCR_RUN_MODE() usable for armv8 and arm7 debug
Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Add or move ARMv8 related dpm function to their own source module
Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Add various function to read/write ARMv8 registers.
Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae
Signed-off-by: David Ung <david.ung.42@gmail.com>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Add new enum ARM_STATE_AARCH64 to the list of possible states.
Change-Id: I3cb2df70f8d5803a63d8374bf3eb75de988e24f8
Signed-off-by: David Ung <david.ung.42@gmail.com>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This bug was already attempted to fix in an earlier patch but
merging the "defer-examine" feature caused a regression, which this patch
tries to fix again.
Change-Id: Ie1ad1516f0d7f130d44e003d6c29dcc1a02a82ca
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3951
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Sometimes it is necessary to resume into a different state (ARM/Thumb)
than at debug state entry. According to the documentation this should
be possible with "arm core_state arm|thumb" before the resume command,
however the original code also restores the original CPSR, which
overrides whatever state the core was set to. This seems to work on some
cores (e.g. Cortex-A5) but not on others (e.g. Cortex-A9). Using the "BX"
instruction to set resume PC and core state works on Cortex-A9 and
ARM11, but is not sufficient on Cortex-A5, where an explicit write to
the PC (MOV pc, r0) is required additionally.
Change-Id: Ic03153b4b250fbb8cf6c75f8e329fb34829aa35f
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3386
Tested-by: jenkins
Reviewed-by: Alexander Stein <alexanders83@web.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Also make GPL notices consistent according to:
https://www.gnu.org/licenses/gpl-howto.html
Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3488
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch adds the fpv4-sp-d16 registers to the armv7m register set.
The work is inspired by Mathias K but takes a different approach:
instead of having both double and single presicion registers in the
cache this patch works only with the doubles and counts on GDB to
split the data in halves whenever needed.
Tested with HLA only (on an STM32F334 disco board).
Currently this patch makes all ARMv7-M targets report an FPU-enabled
target description to GDB. It shouldn't harm if the user is not trying
to access non-existing FPU. However, the plan is to make this depend
on actual FPU presence later.
Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a
Signed-off-by: Mathias K <kesmtp@freenet.de>
[fercerpav@gmail.com: rework to fit target description framework]
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/514
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The code treats registers that are shadowed in FIQ mode in a special
way: to read them out the target is first switches to USR mode. But
since USR != ANY the current implementation later skips register read,
and the loop becomes endless in case any !valid ARM_MODE_ANY is
present at the moment arm_dpm_full_context() is called. This was
reported in https://sourceforge.net/p/openocd/tickets/76/. The issue
surfaced because 2efb1f14f6 added two
ARM_MODE_ANY registers ("sp" and "lr") which were not normally read,
so at the time a user was calling "arm reg" they were not valid.
Fix this by changing the mode appropriately while keeping the "mode"
variable state intact so it would later match register's mode.
Compile-tested only.
Change-Id: I01840e8fa20ec392220138a3f1497ac25deb080a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2278
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.
For XScale, fix a dodgy sequence while stepping. It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic. It
should have done like ARM7/ARM9 does: init to NULL.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Generalize the core of watchpoint setup so that it can handle
breakpoints too. Create breakpoint add/remove routines which
will use that, and hook them up to target types which don't
provide their own breakpoint support (nothing, yet).
This suffices for hardware-only breakpoint support. The ARM11
code will be able to switch over to this without much trouble,
since it doesn't yet handle software breakpoints. Switching
Cortex-A8 will be a bit more involved.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The term "DPM" is probably not well known ("Device Power Management"?),
so identify its source in the current ARM architecture specification.
It's relevant to ARMv6, ARMv7-A, and ARMv7-R ... but not "M" profiles.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Until we manage breakpoints at runtime (patches not ready for 0.4)
the only way this code should touch them is to disable them at server
startup (a previous debug session may have left them active).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Abstract the DPM breakpoint and watchpoint data structures to
have a shared core for housekeeping.
Abstract the code updating the watchpoint registers so that it
can be used to update breakpoint registers. Then do so, when
something has set up the breakpoint state used by this code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Move most declarations in <target/armv4_5.h> to <target/arm.h>
and update users.
What's left in the older file is stuff that I think should be
removed ... the old register cache access stuff, which makes it
awkward to support microcontroller profile (Cortex-M) cores.
The armv4_5_run_algorithm() declaration was moved too, even
though it's not yet as generic as it probably ought to be.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Move the ARM opcode macros from <target/armv4_5.h>, and a few
Thumb2 ones from <target/armv7m.h>, to more appropriate homes
in a new <target/arm_opcodes.h> file.
Removed duplicate opcodes from that v7m/Thumb2 set. Protected
a few macro argument references by adding missing parentheses.
Tightening up some of the line lengths turned up a curious artifact:
the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
There's currently no explanation for why it's done that way...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The low two bits are defined as should-be-zero-or-presereved.
We'll take the zero option, it's easier to enforce.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that. Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.
Likewise with private copies of DSCR ... add one to the DPM
struct. Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Changes from the flat namespace to heirarchical one. Instead of writing:
#include "jtag.h"
the following form should be used.
#include <jtag/jtag.h>
The exception is from .c files in the same directory.
Save and display the address of the instruction which triggered the
watchpoint. Because of pipelining, that's well behind the PC value
when debug entry completes. (Example in a subroutine that had been
returned from...)
Remove unused A8 stuff, mostly watchpoint hooks from the header.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This is a NOP unless the underlying core exposes two new methods, and
neither of the two cores using this (ARM11xx, Cortex-A8) do so yet.
This patch only updates those cores so they pass a flag saying whether
or not to update breakpoint and watchpoint status before resuming; and
removing some now-needless anti-segfault code from ARM11. Cortex-A8
didn't have that code ... yes, it segfaulted when setting watchpoints.
NOTE: this uses a slightly different strategy for setting/clearing
breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone
unless it's *got* to change something, to speed halt/resume cycles
(including single stepping).
ALSO NOTE: this under-delivers for Cortex-A8, where regions with size
up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can
also handle (size 1/2/4 bytes). Should get fixed later.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
