this change is a preparation for STM32L5 support on top of L4 driver
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
a table with register offset will be introduced, thus correct register
addresses will be obtained using this table and the driver internal
function 'stm32l4_get_flash_reg' will be responsible of this.
Change-Id: I74bf61a83fe53575623640af0328b3253ecc796f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5508
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Michael Jung <mijung@gmx.net>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
According to RM0432 rev. 6, only 0x1001 "Z" rev. applies for STM32L4P5/Q5.
Verified on real device. Whether other revisions exist is unclear.
Change-Id: I761ae077d089b06925fc0fe1ff2b1e478b8a66fa
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/5521
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Fix build error on Mac OS X Catalina (10.15.4) caused by formatting
stm32l4_info->wrpxxr_mask, which is uint32_t, as uint16_t in the debug
log message. Adding casting to uint16_t before substitution because only
lower 16 bits are significant for debug purposes.
Change-Id: Iddb87cd156dfc84ab1f91cd15a1ddee6b646d412
Signed-off-by: Ilya Kharin <akscram@gmail.com>
Reviewed-on: http://openocd.zylin.com/5590
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some flash banks are not mapped in the target memory
(e.g. SPI flash, some special pages).
Add flash version of mdw/h/b which reads data using
the flash driver.
Change-Id: I66910e0a69cf523fe5ca1ed6ce7b9e8e176aef4a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4776
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If watchdog is enabled, there's no way we can disable it while the flashing firmware
is running. (Halt disables it, but software reset doesn't.) So let's have the flashing
firmware refresh the watchdog regularly, in case it has been enabled by previously
running software. Failure to do so could lead to a watchdog reset in the middle of
the chip bieng programmed.
Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0
Signed-off-by: Aurélien Martin <martaurel@gmail.com>
Reviewed-on: http://openocd.zylin.com/5266
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
For flash/nor/efm32 the EFM32GG12B Giant chip has been added to the
efm32_family along with its respective series and msc_rebase.
Testen on EFM32GG12B390F board
Change-Id: Idd7dfa93f26ac22566aed1be28f30db678cc0a25
Signed-off-by: tscn92 <tscn@kamstrup.com>
Reviewed-on: http://openocd.zylin.com/5567
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
In newlib, the argument of isalnum() and the similar functions in
ctype.h is checked to be either an int or an unsigned char.
Using a normal (signed) char triggers a compile time warning
warning: array subscript has type ‘char’ [-Wchar-subscripts]
Rewrite the function to separate the internal unsigned char
operations from the (signed) char parameter.
Change-Id: I5f19115f0b2de2b5b35dc07ef4b58a96161268ee
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Åke Rehnman <ake.rehnman@gmail.com>
Fixes: 5da746fa09 ("flash/nor/nrf5: detect newer devices without HWID table")
Reviewed-on: http://openocd.zylin.com/5545
Tested-by: jenkins
Reviewed-by: Ake Rehnman <ake.rehnman@gmail.com>
On stm32h747 writing/erasing bank 1 didn't work. It was because the
flash register base was always set for bank 0.
Tested on STM32H747I-DISCO board.
Change-Id: I7e8c43ecdda9dc70b114905f5ec6a6753ca29d82
Signed-off-by: Sasha Kozaruk <alkhozar@gmail.com>
Reviewed-on: http://openocd.zylin.com/5534
Reviewed-by: Christopher Head <chead@zaber.com>
Tested-by: jenkins
Change the current message when a flash driver does not implement
the protect_check function to LOG_INFO() from LOG_WARNING(). The
user is still notified that the procedure isn't available, but
changes the tone to indicate this is expected with this flash
driver and not something that necessarily is a problem to fix.
Change-Id: If8a2e86a23c852d562346ca36734e5d02df4a851
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5539
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This adds the ATmega256RFR2 to the list of know devices for flashing.
Change-Id: Ib24a508762aaa84ba08ba37409db2ae674b46288
Signed-off-by: Lars Pöschel <poeschell+openocd@mailbox.org>
Reviewed-on: http://openocd.zylin.com/5504
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The current method used for flash addressing uses 16 bit. Every access
to flash is 16 bit wide. With 16 address bits one can address 0x10000
unique locations á 16 bits thats 0x20000 bytes.
For flashes bigger than that avrs have an extended addressing with more
than 16 address bits. This is now implemented and used for flashs larger
than 0x20000 bytes.
Change-Id: Id8b6337dde3830fb3c56b9042872e040bb67c12d
Signed-off-by: Lars Pöschel <poeschell+openocd@mailbox.org>
Reviewed-on: http://openocd.zylin.com/5502
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32WB3x devices' flash are quite similar to STM32WB5x,
except the maximum flash size, which is 512K for WB3x and 1M for WB5x
Change-Id: I3098d7153a7429e0e72c75cec962c05768b0b018
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5475
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
contains a single bank of maximum 256 Kbytes of flash memory.
there is 3 variants with different Flash/RAM sizes:
STM32WLE5JC : 256K/64K
STM32WLE5JB : 128K/48K
STM32WLE5J8 : 64K/20K
the work-area size is set to 20 kb to fit in STM32WLE5J8
Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5450
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
+ minor changes in comments' alignment to please our eyes
Change-Id: Ifa35a1032afc4e9aee524f596c0298a9eea49c37
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5500
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.
Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.
Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Added fixes for issues found in additional code reviews.
Fixed host Endianness issues with using buffer reads
and writes instead of the *_u32 variants.
Changed code that tried to ID banks by hardcode
bank_number values to use instead the bank base
address. This fixes problems using configurations
with multiple devices.
Note that this replaces Change 4786 which has
been abandoned because of extensive changes to
the code to stop IDing banks by name. And I
think I really messed up a rebase/merge on the
document file.
Tested on MSP432P401R, MSP432P4111, and MSP432E401Y
Launchpads.
Change-Id: Id05798b3aa78ae5cbe725ee762a164d673ee5767
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5481
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Adopted only fast algorithm for flash programming:
- write_word and write_byte methods have been removed.
- start and end write alignments have been defined.
Moved flash controller registers offsets in a common file
shared with the flash algorithm.
- the flash base address is passed to the flash algorithm
as a parameter.
Removed unused functions
Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491
Signed-off-by: luca vinci <luca.vinci@st.com>
Reviewed-on: http://openocd.zylin.com/5393
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Michele Sardo <msmttchr@gmail.com>
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)
Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The aligning code generated a clang static analyzer warning and
imposed huge memory leak. This part of code was removed and
flash infrastructure to alignment is used instead.
Not tested on hw!
Change-Id: I7c71da87547e71d595a7e7071ae5adcc1cecc827
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5367
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Group device list based on the device family and add clear
device family names.
Change-Id: I7a2dab1d1c0c8d141df02656c1964cb2c3fcbcd1
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5423
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
this new device has the following features:
- single core cortex-M7
- 2MB flash - dual bank
- page size 8k
- write protection grouped by 4 sectors
- write block size 128 bits (16 bytes)
the bit definition of FLASH_CR is different than STM32H74x,
that's why we introduced a helper to compute the FLASH_CR value
Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5441
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types POINTER_LOCATION --fix-inplace -f {} \;
then manually reviewed.
OpenOCD coding style does not mention the space around pointer's
asterisk, so no check is enforced. This patch only makes the style
uniform across the files.
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: Iefb4998e69bebdfe0d1ae65cadfc8d2c4f166d13
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5197
Tested-by: jenkins
Change-Id: Ia212b1877abeda27f507de29a3aee2b171c1b8c6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5448
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Also add locking after option write, it was missing at all.
Change-Id: I0227c6a74866f0fe8e40aa58616f0b3115ad5af0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5361
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Report the 32-byte alignemnt requirement via the bank structure rather
than enforcing it ad-hoc in the write routine. This allows people to do
non-32-byte-aligned writes if they want, with the infrastructure fixing
up the addresses passed to the low-level driver.
Change-Id: I2c4f532f2000435954a900224dbc9f2c30d1cc94
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5388
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without this, a failed attempt to change option bytes will silently
appear to succeed but without actually changing the option bytes
(confusingly, the option bytes will still read back as if they had been
changed until a reboot as well!).
Change-Id: Id529c6c384a8a16be75f5702310670d99d8fac79
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5418
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
We have the macro ARRAY_SIZE() already available. Use it!
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types ARRAY_SIZE -f {} \;
Change-Id: Ic7da9b710edf118eacb08f9e222f34208c580842
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5198
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
this is to avoid confusion with STM32 L4, L4+ and L5 families
also:
- a warning message is changed to error
- stm32l0x and stm32l1x aliases has been created to permit
the usage of either names
Change-Id: If3f16d2a3b7d1369959aa7407da37a9076ea91d7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5437
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add driver for the RPC block in HF mode on Renesas R-Car Gen3 SoCs.
This driver allows operating the on-SIP HF memory.
Note that HF is CFI compliant flash, but it is not memory mapped,
hence the need to replace all the memory accessors and read/write
functions. The write function is entirely replaced to increase
performance and is Spansion/AMD specific, since there is no known
SIP with other HF from another vendor.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen3 SoC using HyperFlash:
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME rpchf 0x08000000 0x4000000 2 2 $_CHIPNAME.a57.0
Change-Id: Ie18729d017eeb46e1363333ffe002d010dfc5ead
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5149
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Fix comment of tested errors in asm src.
List all relevant errors in FLASH_ERROR mask: FLASH_PROGERR was missing
and any trial to re-program already programmed double word ended up
in the error bit held uncleared and flash write permanetly repeating
the error message until reset.
Lock the bank also after unsuccesfull write_block run.
Set async target algo block size to size of double word.
Remove warning in case of write_block success. In case of error
use LOG_ERROR instead of warning.
Change-Id: Ibf6d5e306a4c2eaa43de67d636b4902c737f02f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5360
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The original code paded the write chunk with random bytes by overrunning
the buffer. An user can easily regard the random bytes to
be a programming error.
Change-Id: Ib0f47b5bc406bc6a7c32f3d929bf324a17c7c1e1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5359
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The chip->hwid is uint32_t , fix the print format.
This was detected by TravisCI on OSX, where this triggers a build error.
Change-Id: I776a7bb50e396c8fccc24500dec4750190da7982
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5401
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ilya Kharin <akscram@gmail.com>
Add driver for the SH QSPI controller. This SPI controller is often
connected to the boot SPI NOR flash on R-Car Gen2 platforms.
Add the following two lines to board TCL file to bind the driver on
R-Car Gen2 SoC and make SRAM work area available:
flash bank flash0 sh_qspi 0xe6b10000 0 0 0 ${_TARGETNAME}0 cs0
${_TARGETNAME}0 configure -work-area-phys 0xe6300000 -work-area-virt 0xe6300000 -work-area-size 0x10000 -work-area-backup 0
To install mainline U-Boot on the board, use the following procedure:
proc update_uboot {} {
# SPL
flash erase_sector 0 0x0 0x0
flash write_bank 0 /u-boot/spl/u-boot-spl.bin 0x0
# U-Boot
flash erase_sector 0 0x5 0x6
flash write_bank 0 /u-boot/u-boot.img 0x140000
}
Change-Id: Ief22f61e93bcabae37f6e371156dece6c4be3459
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
V2: - Add Makefile and linker script for the SH QSPI IO algorithm
- Include the algorithm code instead of hard-coding it
Reviewed-on: http://openocd.zylin.com/5143
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This is a preparatory change, align the function name with the rest
of the API, no functional change.
Change-Id: I6a810d2a54edcd13ad9a87d24a7334802c41623b
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This is a preparatory change, align the function name with the rest
of the API, no functional change.
Change-Id: Ib967520f027b03eb1792b36ede52335df8e23941
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5390
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add possibility to supply custom CFI memory accessors via cfi_info
and override the default memory-mapped ones.
Change-Id: I1b6bc1db69fc33e8cdef96c41742c40e6d8917e9
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5147
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The size argument is always set to bank->bus_width and bank pointer
is now passed into cfi_target_{read,write}_memory(), so the size
can be accessed through the bank pointer inside the function instead
of being explicitly passed in.
Change-Id: I0abc1cc3bf513281c10cb5de7a21cb0e75cb7676
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5389
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Replace passing in struct target with passing in struct flash_bank,
so that the later can contain function pointers to custom per-driver
memory accessor functions.
Change-Id: Id2573a6d5f1a73ed9c4f73c53592a9a335a11c99
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5146
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32L4P/Q devices have:
- similar flash layout as STM32L4R/S devices
- 1024K of flash memory (some parts have 512K only)
tested on NUCLEO-L4P5ZG using board/st_nucleo_l4.cfg
Change-Id: I77047351bc7dcd7c76d0f31a77be73005104a06f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This rework is inspired from the 'flash/nor/stm32h7x.c'
This rework will ease the support of new devices on top of this driver:
for example: STM32WB have different flash base and size addresses
Notes:
- stm32l4_probe modified in order to charge the correct part_info from
the defined stm32l4_parts according to the device id
- stm32l4_flash_bank.bank2_start is replaced by .part_info->bank1_sectors
- STM32_FLASH_BASE is removed , part_info->flash_regs_base will be used instead
based on that flash register addresses are changed to offsets,
>> stm32l4_get_flash_reg was modified accordingly
- stm32l4_read_option and stm32l4_write_option was modified to accept an
offset instead of an absolute address, luckily this is the commands'
argument by default
- stm32l4_mass_erase modifications :
- use MER2 only on top of dual bank devices
- wait for BUSY bit before starting the mass erase
Change-Id: Ib35bfc3cbadc76bbeaaaba9005b82077b9e1e744
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4932
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Create separate memory read/write functions which facilitate access
to the CFI NOR, so that they can be replaced by controller-specific
functions if necessary. This would become necessary when implementing
support for e.g. HyperFlash controllers, which do not directly map
the HyperFlash into the address space.
Change-Id: I1bba1edfd397cb37bfedb43efe2dd03feb26a375
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5145
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Factor out the spansion unlock sequence to deduplicate the code.
Change-Id: Id78522e9a2f0e701870ef816772289d08257476a
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5144
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The current code assumes an STM32's flash bank is laid-out in either of
two configurations:
- 4 x 16kB + 1 x 64kB + n x 128kB
- 4 x 32kB + 1 x 128kB + n x 256kB
This is quite ad-hoc but works fine in practice, as long as there are at
least 5 sectors (if n=0). Unfortunately, some newer STM32s are shipping
with only 64 kB of flash (4 x 16kB sectors).
This patch still assumes the same sector layout, but only keeps adding
sectors to the bank if the bank's capacity has not been reached. This
prevents openocd from crashing on some newer STM32s.
Change-Id: If00e5d7a328d11b399babc0bb2111e3ad8a3217e
Signed-off-by: Romain Goyet <romain.goyet@numworks.com>
Signed-off-by: Keir Fraser <keir.xen@gmail.com>
Reviewed-on: http://openocd.zylin.com/4926
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
In commit cea40152f8 option bytes
reading was changed to direct access to option bytes area.
While there are no problems with stm32f0xx and stm32f3xx chips,
option block (0x1ffff800..0x1ffff80F) is unreadable from locked
stm32f10x chips.
As a result, stm32f1x unlock command writes dirty values to user
options, user data and write protection bits.
Option bytes reading reverted from direct access to option bytes area
to reading currently loaded bytes from FLASH_OBR/FLASH_WRPR registers.
Tested on stm32f100, stm32f103, stm32f107 as well as on stm32f030 and
stm32f303.
Change-Id: Iad476351ffdaca5ace12e02272dacea7f3d08f52
Signed-off-by: Oleksandr Redchuk <real@real.kiev.ua>
Reviewed-on: http://openocd.zylin.com/4940
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use assert to remove "Dereference of null pointer" warnings.
Change-Id: Ie204c234a71758e6470351e1d9f22da3dd887f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5357
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-fsize_base should be fsize_addr as it is the address of FLASH_SIZE register
-flash_base should be flash_regs_base to avoid confusion with flash block start
-add LOG_ERROR to functions stm32x_[read|write]_flash_reg(...)
Change-Id: I86f035314bcd616fc0bdf445692d945a85c15481
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5362
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Using a signed variable as a parameter of FLASH_SNB() macro
generated "warning: The result of the left shift is undefined
because the left operand is negative"
Change-Id: I8b3fe840f9308962460906097df6ddd848c07b25
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5356
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The new "Access control list" flash protection scheme used in nRF52840
is not yet supported. Do not prevent sector erase if protection
state is unknown.
Change-Id: Iae9a869a54ffbdc888fb3ec478dafb5c942d9ea0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5348
Tested-by: jenkins
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4
The second core creation is only done when
* DUAL_CORE variable is set to true
* non HLA interface is used
A second check for the second core existence is done in cpu1 examine-end
Once the second core is detected it gets examined.
Furthermore, the script provides a configurable CTI usage in order to halt
the cores simultaneously.
Tested on Rev X and V devices.
PS: the indentation was a mix of spaces and tabs, all changed to tabs.
Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5130
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
functions managing option bytes cache (stm32x_read/write_options)
have bee removed, and a new functions to modify a single option byte
have been introduced (stm32x_write/modify_option).
by the way, some helpers have been introduced to access flash registers:
- stm32x_read_flash_reg(bank, offset, *value): int
- stm32x_write_flash_reg(bank, offset, value): int
and a new commands to read and write a single flash option register:
- stm32h7x option_read <bank> <option_reg offset>
- stm32h7x option_write <bank> <option_reg offset> <value> [mask]
also lock and unlock handlers' have been reduced by using the same routine
(stm32x_set_rdp) and have been optimized to not write options unless
there is a change in RDP level.
finally, several functions have been fixed to lock flash / options in case
of failure.
Change-Id: I75057949ab9f5b4e0f602bafb76f9f80d53a522b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5293
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
To achieve that we need to avoid using FLASH_REG_BASE_B0, and use
bank registers instead:
For dual bank devices, each option register is mapped in 2 addresses
at the same offset from flash_bank_reg_base.
This is true for OPTCR, OPTKEYR, OPTSR_CUR/PRG, OPTCCR according to
RM0433 Rev6 (refer to section 3.9: FLASH registers)
In stm32x_write_options, according to RM0433 Rev6, after OBL launch we
should wait for OPTSR_CUR.BSY bit instead of FLASH_SR.QW
Change-Id: Ie24a91f069d03c9233797390fc2e925c737dad90
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5291
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Each bank had to store its options only, there is no need for bank1
to sneak into bank2 options.
Furthermore, some variants do not have a second bank.
Change-Id: I9229eb8ab4b5860ba2b0c5dbe626a54a84bca4d6
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5290
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Drop static pointer to allocated struct nrf5_info, iterate over
the flash bank list to find previously allocated nrf5 instances.
nrf5 is swd only device, so static allocation makes no harm,
but we should avoid copying the wrong code to other flash drivers.
Free sector array before allocating it to avoid memory leak on
re-probing device.
Change-Id: I781d8f4418a91c043f2393e5ecc5278fc6df3566
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4910
Tested-by: jenkins
Also refuse 'flash protect' on any nRF52.
Fail protection check on nRF52840 until ACL protection is implemented.
Change-Id: I84fcf117427e4894147c3ad92e2a3597566b4fcf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4864
Tested-by: jenkins
nrf5 flash driver detected devices by looking up the HWID in the table
of known devices. Unfortunately chips are produced with many different
HWIDs for each type.
All nRF52 devices have FICR INFO field suitable for device identification
without need of HWID lookup.
Some newer nRF51 devices have FICR INFO too although undocumented.
Use this information to identify the device.
nrf5_info() is reworked to show just concise info.
Decoding FICR and UICR registers was moved from nrf5_info()
to a new command 'nrf5 info' without functional changes.
The flash bank for UICR page has the same size as program flash sector.
Change-Id: I900095b9ae23ee995f8e2bef8539b75d00300da5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4848
Tested-by: jenkins
nRF5 flash controller can write a word at a time. Ask flash
infrastructure to handle alignment and padding.
Fix mixing of offset and address in nrf5_ll_flash_write()
- the original code worked just because NRF5_FLASH_BASE is 0
Change-Id: Ibe8bdf899a1764cf4117b2deda1a4618eeb16697
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4819
Tested-by: jenkins
Make driver_priv point directly into the corresponding chip bank structure
and add a pointer to it to get back to its chip when it's needed. This
removes the need to keep track of any bank number, either global or chip-
local.
In addition, it simplifies the cases where the chip structure was just used
to access the chip bank fields; now they are directly accessible.
Change-Id: Iaa353cd4fa7d8ff94c2ef69028c7cb32fade0420
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4775
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
According to the reference manual it should be 0x40000000. Flashing (and
booting) a firmware with this MSC base was successful.
Change-Id: I739e67d36555b8170a3b8e26f54cf1c09ce8424b
Signed-off-by: Christian Meusel <christian.meusel@posteo.de>
Reviewed-on: http://openocd.zylin.com/5263
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
PAGE_SIZE is defined in system includes on some systems, this would
avoid the unintended conflict
Fixes
| src/flash/nor/esirisc_flash.c:95:9: error: 'PAGE_SIZE' macro redefined [-Werror,-Wmacro-redefined]
| #define PAGE_SIZE 4096
| ^
| /mnt/a/yoe/build/tmp/work/core2-64-yoe-linux-musl/openocd/0.10+gitrAUTOINC+7ee618692f-r0/recipe-sysroot/usr/inclu
de/limits.h:89:9: note: previous definition is here
| #define PAGE_SIZE PAGESIZE
Change-Id: I195b303fc88a7c848ca4e55fd6ba893796df55cc
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-on: http://openocd.zylin.com/5180
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
There is no sense in displaying the max size (2M) as there is variants
of this device with reduced flash size
Change-Id: I40574064d75fdf2a038044c81038a6d7abc6c4dd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5288
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
SWM050 is a series of MCU product by Foshan Synwit Tech, which is
available in TSSOP-8 or SSOP-16 packages.
Adds flash driver for the internal 8KiB flash of the MCU. The registers
are based on reverse engineering the J-Flash blob provided by the
vendor.
Also adds a pre-made cfg file.
Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Caleb Szalacinski <contact@skiboy.net>
Reviewed-on: http://openocd.zylin.com/4927
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The command uses LOG_USER() instead of command_print().
Fix it.
This change was part of http://openocd.zylin.com/1815 from Paul
Fertser and has been extracted and rebased to simplify the review.
Change-Id: I92e5e5954a75b96093b3ed6af73a7536c063b639
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5083
Tested-by: jenkins
After replace CMD_CTX with CMD, the indentation is incorrect.
Fix it.
This change was part of http://openocd.zylin.com/1815 from Paul
Fertser and has been extracted and rebased to simplify the review.
Change-Id: I5d7c40227ceda2e9db8dab88088d74012d2254c4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5082
Tested-by: jenkins
To prepare for handling TCL return values consistently, all calls
to command_print/command_print_sameline should switch to CMD as
first parameter.
Change prototype of command_print() and command_print_sameline()
to pass CMD instead of CMD_CTX.
Since the first parameter is currently not used, the change can be
done though scripts without manual coding.
This patch is created using the command:
sed -i PATTERN $(find src/ doc/ -type f)
with all the following patters:
's/\(command_print(cmd\)->ctx,/\1,/'
's/\(command_print(CMD\)_CTX,/\1,/'
's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/'
's/\(command_print_sameline(cmd\)->ctx,/\1,/'
's/\(command_print_sameline(CMD\)_CTX,/\1,/'
's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/'
This change is inspired by http://openocd.zylin.com/1815 from Paul
Fertser but is now done through scripting.
Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/5081
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
To prepare for handling TCL return values consistently, all calls
to command_print/command_print_sameline should be ready to switch
to CMD as first parameter.
Change prototype of get_current_sam4() to pass CMD instead of
CMD_CTX.
This change was part of http://openocd.zylin.com/1815 from Paul
Fertser and has been extracted and rebased to simplify the review.
Change-Id: I8dfa66f3f6be318d6ba89649279b1b4502f375d9
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5055
Tested-by: jenkins
To prepare for handling TCL return values consistently, all calls
to command_print/command_print_sameline should be ready to switch
to CMD as first parameter.
Change prototype of get_current_sam3() to pass CMD instead of
CMD_CTX.
This change was part of http://openocd.zylin.com/1815 from Paul
Fertser and has been extracted and rebased to simplify the review.
Change-Id: Ia1e7af79d0fc89d229b4e10df37317a374bbab62
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5054
Tested-by: jenkins
Change-Id: I5dc16031c38576d853774b6123c93be1e1b4aa96
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5133
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Based on RM0433.rev5 > Section 3.3.9 : Flash program operations:
QW1/2: this bit indicates that a write, erase or option byte change
operation is pending in the write queue or command queue buffer.
It remains high until the write operation is complete.
It supersedes the BSY1/2 status bit.
On this basis, stm32x_wait_status_busy is renamed accordingly to be
'stm32x_wait_flash_op_queue'
Note : In this commit there is a fix of SR_ERROR_MASK value in flash loader algo
Note : This modification is mandatory for revision X, and backward compatible
with old revisions
Change-Id: I59d2973317d76b01fbb0fb5e4a472a47d0a7a5b5
Signed-off-by: Laurent LEMELE <laurent.lemele@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/4883
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Bit 29 of OPTSR is IO_HSLV. It ought to be read in stm32x_read_options
and written in stm32x_write_options. Adjust the bitmasks to do this.
Change-Id: I785a5291c991c98b774177f960dc58f2b5e045e2
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4745
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The missing field causes runtime debug message
BUG: command '%s' does not have the '.usage' field filled out
While there, fix some minor typo in the help messages:
s/deasert/deassert/
s/Deasert/Deassert/
Change-Id: If3dd18265cda103ca0d05609f67f4ca58e7cbb27
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5024
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Remove the numeric parameter <bank> from help and add it to usage
Change-Id: I630ca5450955210299f54e16fe5c9e8e51b3b266
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5022
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The only allowed parameter is the string "enable"
Change-Id: Iefdad38f1b4177e4194e58caf2be654357299ded
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5021
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Chained command require a subcommand as first argument. The usage
field for chained commands is not really important because the
"help" command will list all the subcommands with their respective
usage.
Add a empty usage field on all chained command.
The command "jlink config" can be either followed by a subcommand
or used alone, so use a dedicated usage string.
Change-Id: I43c3f8a766f96a9bdab4e709e3c90713be41fcef
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5017
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Keep using the same indentation rules while initializing struct
command_registration.
Change-Id: I900924600753ee7a72ca45da13db4112ab4b1522
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5015
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Keep using the same indentation rules while initializing struct
command_registration.
Change-Id: Ie69d9d6a786e1ef0abbcfd3eef89a61206238ebe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5014
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Setting of flash_sector::is_erased in flash erase and mass erase
is popular folklore. Make clear it is useless.
Change-Id: Ide397eb6d24fc8fa38931e6c8a0693d39668a5d2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4768
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Instances of struct flash_driver are never written to at runtime. For a
small amount of memory saving and also robustness (fewer things for
stray pointer writes to hit), mark them const.
Change-Id: Iadbbbc2fac0976d892699200000c5f02856729f3
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4803
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Use target_addr_t exclusively for comparison of sector boudaries and
address range.
Use the last addres for both address range end and sector end.
It avoids problems with a flash bank mapped at the very end of
target address space.
Change-Id: Idf97c837453d97cbc4cf8a1c76ad799f4142f19e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4985
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Bit 4 in OPTSR is IWDG1_SW (the code originally called it IWDG1_HW, but
the reference manual refers to it as IWDG1_SW). This is broken out into
a separate variable, independent_watchdog_selection, in stm32x_options.
However, this is not necessary: bit 4 is included in the user_options
field, which includes all of bits 2 through 7, and
independent_watchdog_selection is not referenced anywhere else. Delete
the field and just rely on user_options to transport that bit, along
with all the other bits it contains, between stm32x_read_options and
stm32x_write_options.
Change-Id: I4da63df9272cf091267b956c412b95671ea1d3c9
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4744
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This should allow users to configure flash at >32-bit addresses.
Change-Id: I7c9d3c5762579011a2d9708e5317e5765349845c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4919
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The OTP is part of the flash memory. It has 512 (1024 for F7) bytes
and is organized in 16 sectors with 32 (64 for F7) bytes each.
The OTP is exposed as separate flash bank 1 and can be used
with the usual flash commands.
Writing the OTP can be done as follows:
> stm32f2x otp 1 enable
> flash write bank 1 foo.bin 0
> mdw 0x1fff7800 4
> verify_image foo.bin 0x1fff7800
> stm32f2x otp 1 disable
Note: This patch is largely a rebase/cleanup of a patch
from 2012 by Laurent Charpentier and he did most of the work.
No new Clang-Analyzer warnings.
Change-Id: I5e6371f6a7c7a9929c1d7907d6ba4724f9d20d97
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/829
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Recent patches for STM32L4+ assumed all STM32L4 processors have a dual-
bank option. This is not the case for STM32L4{3,4,5,6}xx processors and
therefore, these processors (like STM32L433) failed when attempting to
flash the second half of the flash memory. This patch fixed this issue.
Tested on STM32L433xC, STM32L476xG and STM32L471xG.
Change-Id: I8262ba4f05190802c5868d753f3e7af50e581811
Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Reviewed-on: http://openocd.zylin.com/4913
Tested-by: jenkins
Reviewed-by: Peter Tettelaar <peter@float-iot.nl>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Mark Schulte <mschulte@lyft.com>
Added id, name, flash size and RAM size for following parts to samc20_parts[]:
SAMC20N18A
SAMC20N17A
And the following to samc21_parts[]:
SAMC21N18A
SAMC21N17A
Change-Id: Ie8cf1c531a60bfaed6e814d436d232afb89dae3f
Signed-off-by: Kevin Vermilion <kevin.vermilion@gmail.com>
Reviewed-on: http://openocd.zylin.com/4880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Adds ability to change the user data in STM32F1x/STM32F3x MCU's option byte.
Since OpenOCD prints the content of user data in option byte registers, it
is seems logical to also provide a way how to change this data.
Change-Id: Ie6cb756b4f11b5c6dabd34bc89434a358eb758ff
Signed-off-by: Jan Vojtech <honza.vojtech@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4663
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.
While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.
Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The new Microchip (former Atmel) series powered by Cortex-M4 looks
very similar to older M0+ powered SAM D2x at the first sight.
Unfortunately the new series differs a lot in important details.
NVMCTRL has different register addresses, moved important bits
and even changed binary command set. An universal driver for all SAM D/E
would be very complicated. That's why a new driver was derived.
Tested on Microchip SAM E54 Xplained Pro kit (board cfg included).
Adjusted for the restructured dap support.
Checked by valgrind and clang static analyzer.
Change-Id: I26c67047a552076f4b207b9b89285a53d69b4ca4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4272
Tested-by: jenkins
Reviewed-by: Andres Vahter <andres.vahter@gmail.com>
stm32x_write_options() uses stm32x_write_block() at STM32_OB_RDP address.
The change eliminates subtracting bank->base (and later adding it back).
Change-Id: Icdd24afc7178b814be58e6033d4b93fdfb2d2a16
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4859
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Change-Id: I1e9e62979c4629c8ba1d5ae89ca7392259969eb6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4858
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
samr34/r35 combine SAML21 and SX1276 (lora transceiver). This one was found on
xplaned pro evaluation kit. Ids for other r34/r35 chips are apparently not yet
documented.
Change-Id: I4054dd56ea53c9bae8d17abd5a3e4e65e1b9c8b1
Signed-off-by: Guillaume Revaillot <g.revaillot@gmail.com>
Reviewed-on: http://openocd.zylin.com/4872
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The functions dap_to_jtag() and dap_to_swd() have been introduced by
3ef9beb52c ("ADIv5 DAP ops switching to JTAG or SWD modes") in
arm_adi_v5.c by using the JTAG queue only.
Later, in 6f8b8593d6 ("ADIv5 transport support moves to separate
files") the functions has been moved in adi_v5_swd.c and adi_v5_jtag.c
but keeping the dependency from JTAG queue.
The functions does not work if the current transport is not JTAG.
Move back the functions in arm_adi_v5.c, replace the input parameter
"target" with "dap", use the transport to detect if the JTAG queue is
present, in case of SWD transport use the proper method, for other
transports report error.
Reuse the ADI v5 sequences already present in jtag/swd.h.
Also, OpenOCD does not support switching to another transport after
the initial selection, so do not change DAP's ops vector.
Change-Id: Ib681fbaa60cb342f732bc831eb92de25afa4e4db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4852
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This hardware id is e.g. used by the Insight SiP ISP1507-AX.
Change-Id: I82568d292f9882372ab061d8e3e36906b0cc5882
Signed-off-by: Mirko Vogt <mirko.vogt@sensorberg.com>
Reviewed-on: http://openocd.zylin.com/4845
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Valgrind and Clang Static Analyzer have no complaints about this change.
Change-Id: I7757615ec52448372bdc57729cdf97c7016d97e8
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4656
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
These devices differ from LPC8xx devices in that they have a different
IAP entry point, but everything else is the same. Using Tcl to pass
different IAP entry point.
no new Clang analyser warnings and no new build sanitizers issues.
Change-Id: I2d654dd250f416e74262c0228cad8713a283402f
Signed-off-by: Rod Boyce <developer@teamboyce.co.uk>
Reviewed-on: http://openocd.zylin.com/4684
Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Currently it is impossible to flash ELF with correct offsets. The reason
is a bogus offset calculation extracted from base.
Since any other spi drivers do not care about base, do the same for
ath79 as well.
Change-Id: I9e46e01c9e7a709c2d07da9203c634f302603afd
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4821
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Longest erase all FLASH for nRF5 series is 295.3 ms for nRF52832.
Timeout period now is set to 340 ms (295.3 + 15%)
Change-Id: Iae00ed7b634f111b9798db11e35e4e066d4aaa95
Signed-off-by: Jānis Skujenieks <janis.skujenieks@gmail.com>
Reviewed-on: http://openocd.zylin.com/4822
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
w600 is a wifi soc from winner micro(www.winnermicro.com).
Change-Id: Ib8ccd6e52baefca6547fb97d29db75db0ee73948
Signed-off-by: Simon Qian <versaloon@simonqian.com>
Reviewed-on: http://openocd.zylin.com/4801
Tested-by: jenkins
Reviewed-by: yichen <wdyichen@wdyichen.cn>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Slow version of blank check procedure reads target memory sector-by-sector
using 1 KB chunks. Due to bug in chunk size calculation algorithm the actual
size of the chunk is always 1 KB even if sector size is smaller.
This causes out-of-boundary read of the last sector.
Steps to reproduce:
1) Use target with small sectors (e.g. psoc6 with 512-byte sectors)
2) set WORKAREASIZE_CM0 0
3) flash erase_check 1
Running slow fallback erase check - add working memory
Info : SWD DPIDR 0x6ba02477
Error: Failed to read memory at 0x14008000
unknown error when checking erase state of flash bank #1 at 0x14000000
Bank is erased
Change-Id: I03d0d5fb3a1950ae6aac425f5e24c7fd94b38325
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4785
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This patch removes use of register write protection in protect() and
protect_check() now that Change 4765 has merged.
Change-Id: I42c429dc283c5b53989a6b98ebfc58214274ff16
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4791
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This patch adds support for instruction tracing to eSi-RISC targets. The
command interface is borrowed heavily from ETM; eSi-Trace uses a less
sophisticated model for tracing, however the setup and usage is similar.
This patch also cleans up the command interfaces of the other esirisc
command groups and adds additional debugging information to log messages
when dealing with CSRs.
This patch "finalizes" support for 32-bit eSi-RISC targets.
Change-Id: Ia2a9de79a3c7c066240b5212721fb1b7584a9a45
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4780
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Updates support for L4+ device id: 0x470 added by #4310
Extends #4641 to account for L4+ use of multiple DBANK option bits
Enables L4+ 1M and 2M devices to be programmed using sector erase
Change-Id: I42bb379d7d97986f4506423e3da503d07c787c6b
Signed-off-by: bob <rea952@gmail.com>
Reviewed-on: http://openocd.zylin.com/4777
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Remove inappropriate use of bank_number.
Change-Id: I11be1f2540cb09a3ccede35312f90bc8276af338
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4788
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Added fixes found in additional code reviews.
Remove inappropriate use of bank_number field and updated
documentation to reflect the change.
Restored functionality to cc2538.cfg file because previous
change removed the cc26xx.cfg file because the flash support
changes made it obsolete. Rolled the previous cc26xx.cfg
file into cc2538.cfg and updated it to work with other
recent changes. Tested using a SmartRF06 Evaluation
board with embedded XDS100v3 and external XDs110.
Change-Id: Ia19d00cf8055c5c0f1acc53aa23fd06a80fd2ebc
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4787
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The original code was written for and tested on little-endian
host only.
Rewrite it to be independent by host endianess.
Not tested on real HW; I don't own anymore a SPEAr device.
Change-Id: I2f427a804693f56cb9dea4936c525eb814c48c28
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4778
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Some flash drivers had a dummy method for erase_check.
Use default_flash_blank_check() instead if possible.
Change-Id: Iddfeff45ce477007328d061fcb5c553d93c3be98
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4766
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices
use variants for 4-byte addressing.
Some new flash and FRAM device ids added. FRAMs don't have write pages nor
erase commands or sector sizes. The corresponding entries are marked as
"not used" (i. e. zero). Checks in existing SPI flash drivers added to
handle these cases gracefully.
Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4773
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Make flash_driver methods protect() and protect_check()
optional.
Remove dummy definitions of these methods from the drivers
which do not implement protection handling.
Some drivers did not define protect method. It raised segfault
before this change and now it is handled properly.
Lot of drivers returned ERROR_OK from dummy protect()
- now flash_driver_protect() returns an error if not handled by the driver.
Change-Id: I2d4a0da316bf03c6379791b1b1c6198fbf22e66c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4765
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
The dual bank option was being incorrectly read and the
bank b base incorrectly set. This is tested with 512kB
dual bank configuration but needs checking with other
configurations (e.g. 256kb).
This fix should remove the need to use a mass_erase command
prior to programming with OpenOCD
Change-Id: I6e920f11b794c4c1fd34c0e44fb8fa01e7fe8f85
Signed-off-by: Alex J Lennon <alex.lennon@s19.tech>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4641
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Thomas Søhus <soehus@gmail.com>
Prepare for additional flash banks not located at address 0
Change-Id: I60b78c917f94fa52bf24df9e3315536f776eec84
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Reviewed-on: http://openocd.zylin.com/4440
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Handle write protection status in blocks instead of sectors, removing
unnecessary complexity in the process. Now closer to stm32f2x.
Support sequential modification of option bytes by read/modify/write
directly to option bytes area instead of always starting with the
currently loaded bytes from FLASH_OBR/WRPR registers.
Added new command 'options_load' to force re-load of option bytes w/o
having to power cycle target.
Change-Id: I5c76191e29c17a1e11482df06379d10ca8d6d04d
Signed-off-by: Dominik Peklo <dom.peklo@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4576
Tested-by: jenkins
Reviewed-by: Jan Vojtěch <honza.vojtech@gmail.com>
While on it correct RAM amount of SAMR21x16A devices
Change-Id: Ie9ab9de1551bdceff17af7597a9a2ee41f5aebe0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4734
Reviewed-by: Eduardo Montoya
Tested-by: jenkins
eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.
Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Enables the programming of Write protection lock bits.
- Updated/re-factored with option_read, option_write and option_load commands.
Change-Id: I86358c7eb1285c3c0baac1564e46da8ced5fd025
Signed-off-by: Thomas Søhus <tls@ceepro.dk>
Reviewed-on: http://openocd.zylin.com/4654
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Signed-off-by: Cody P Schafer <openocd@codyps.com>
Change-Id: Ia0169514d494bae2a98d92ebc97c8eccc10bc6c4
Reviewed-on: http://openocd.zylin.com/4657
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Read-modify-write setting of FMR register requires an USB turnaround.
Setting FMR before each page write is not necessary and decreases the
write speed.
Change-Id: I67844c898aaf117f155c762c979840b603c767ed
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4611
Tested-by: jenkins
Reviewed-by: Svetoslav Enchev <svetoslav.enchev@gmail.com>
Adding flash programming support for Maxim Integrated MAX32XXX
devices.
Change-Id: I5b0f57a885f9d813240e4bc2d9f765b743e1cfc3
Signed-off-by: Kevin Gillespie <kgills@gmail.com>
Reviewed-on: http://openocd.zylin.com/3543
Tested-by: jenkins
Reviewed-by: Ismail H. KOSE <ihkose@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change-Id: I429a9868deb0c4b51f47a4bbad844bdc348e8d21
Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/4608
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
There was already a github fork that had this fixed, but as we try
to use the latest, non-modified version of all software we use,
I would like to have this fix in the next releases of OpenOCD so
that if people uses $packagemanager, they will not have issues flashing
the last part of the flash of sam4sa16c chips.
Additionally, I've added some more logging related to the flash
bank that was used, and the chip ID that was detected.
Change-Id: I7ea5970105906e4560b727e46222ae9a91e41559
Signed-off-by: Erwin Oegema <blablaechthema@hotmail.com>
Reviewed-on: http://openocd.zylin.com/4599
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Added msp432 flash driver to support the TI MSP432P4x and
MSP432E4x microcontrollers. Implemented the flash algo
helper as used in the TI debug and flash tools. This
implemention supports the MSP432E4, Falcon, and Falcon 2M
variants. The flash driver automatically detects the
connected variant and configures itself appropriately.
Added command to mass erase device for consistency with
TI tools and added command to unlock the protected BSL
region.
Tested using MSP432E401Y, MSP432P401R, and MSP432P4111
LaunchPads.
Tested with embedded XDS110 debug probe in CMSIS-DAP
mode and with external SEGGER J-Link probe.
Removed ti_msp432p4xx.cfg file made obsolete by this
patch.
Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use the right word in flash protect command status messages based on
whether the target bank defines num_prot_blocks. Minor message style
tidy-up.
Change-Id: I5f40fb5627422536ce737f242fbf80feafe7a1fc
Signed-off-by: Dominik Peklo <dom.peklo@gmail.com>
Reviewed-on: http://openocd.zylin.com/4573
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
Corrects names of SAMD11D14AM and SAMD11D14ASS per datasheet.
Change-Id: I8beb15d5376966a4f8d7de76bfb2cbda2db440dc
Signed-off-by: Christopher Hoover <ch@murgatroid.com>
Reviewed-on: http://openocd.zylin.com/4597
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
psoc5lp_erase_check() was not properly adapted to the new
armv7m_blank_check_memory() in the hot fix 53376dbbed
This change fixes handling of num_sectors in dependecy of ecc_enabled.
Also add comments how ecc_enabled influences num_sectors.
Add pointer to default_flash_free_driver_priv() to all psoc5lp flash
drivers to keep valgrind happy.
Change-Id: Ie1806538becd364fe0efb7a414f0fe6a84b2055b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4569
Tested-by: jenkins
The name of the bit according to the reference manual is inconsistency
error, not increment error.
Change-Id: Ie3b73c0312db586e35519e03fd1a5cb225673d97
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4521
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On a specific early-return path, an allocated working area was not
freed. Free it.
Change-Id: I7c8fe51ff475f191624086996be1c77251780b77
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4520
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Flash operation errors that occur during algorithm programming are
reported via the algorithm return value. However, Flash operation
errors that occur during non-algorithm work (erasing, programming
without a work area, programming the last non-multiple-of-32-bytes on
an H7, etc.) generally end with a call to stm32x_wait_status_busy,
which reads the status register and clears the error flags but fails
to actually report that something went wrong should an error flag
(other than WRPERR) be set. Return an error status from
stm32x_wait_status_busy in those cases. Correct a log message
accordingly.
Change-Id: I09369ea5f924fe58833aec1f45e52320ab4aaf43
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4519
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Issue already identified by Alex https://sourceforge.net/u/alexbour/
in ticket #191https://sourceforge.net/p/openocd/tickets/191/
src/flash/nor/psoc5lp.c:237:2: error: ‘strncpy’ output
truncated before terminating nul copying 2 bytes from a
string of the same length [-Werror=stringop-truncation]
Fix it by assigning the value to the array elements.
Change-Id: I22468e5700efa64ea48ae8cdec930c48b4a7d8fb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4563
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The erase check routine checked sectors only if is_erased != 1
Check sector unconditionally.
While on it fix clang static analyzer warnings.
Change-Id: I9988615fd8530c55a9b0c54b1900f89b550345e9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4401
Tested-by: jenkins
Cached flash erase state in sectors[].is_erased is not reliable as running
target can change the flash.
Autoerase was issued before flash write on condition is_erased != 1
Remove autoerase completely as it is a quite non-standard feature.
Change-Id: I19bef459e6afdc4c5fcaa2ccd194cf05be8a42b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4400
Tested-by: jenkins
Added cc26xx flash driver to support the TI CC26xx and CC13xx
microcontrollers. Driver is capable of determining which MCU
is connected and configures itself accordingly. Added config
files for four specific variants: CC26x0, CC13x0, CC26x2, and
CC13x2.
Note that the flash loader code is based on the sources used
to support flash in Code Composer Studio and Uniflash from TI.
Removed cc26xx.cfg file made obsolete by this patch.
Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4358
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Erasing is not supported by the hardware, it can be written directly.
Tested on CY8CKIT-059, except modifying-write.
Change-Id: I6e920ed930dcd5c7f0b10c5b1b4791a828d9080a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3434
Tested-by: jenkins
Change #3432 was merged into git master without adapting it
to #4297 "prepare infrastructure for multi-block blank check".
This is a fast fix of PSoC5LP specific blank check.
Not tested on real PSoC5LP device.
Change-Id: I7dc13ee7bd1f07b2bfe5a93a5030c0c482d30f00
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4557
Tested-by: jenkins
Always probe for ECC mode and display ECC sectors if disabled.
Non-ECC write is implemented as zeroing the ECC/config bytes.
Erasing ECC sectors is ignored, erase-checking takes them into account.
Tested with CY8CKIT-059 (CY8C5888), except ECC mode.
Change-Id: If63b9ffca7ad8de038be3c086c49712b629ec554
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/3432
Tested-by: jenkins
Added cc3220sf flash driver to support the TI CC3220SF
microcontrollers. Implemented flash driver to support the
internal flash of the CC3220SF. The implementation does not
support the serial flash of the CC32xx family that requires
connection over UART, and not via JTAG/SWD debug. Added config
files for both CC32xx devices (no flash) and CC3220SF (with
flash).
Updated to implement comments from code review.
Additional updates to handle remaining comments from review.
Additional updates per review.
Added code to only request aligned writes and full 32-bit
words down to flash helper algorithm. Updated for recent
changes in OpenOCD flash code.
Removed cc32xx.cfg file made obsolete by this patch.
Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4319
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
flash_bank structure of 'virtual' flash driver is a full copy of
the master flash_bank structure including bank->sectors and
bank->prot_blocks pointers. These pointers point to memory
locations allocated by the master driver and thus master driver
is responsible for deallocating them.
Do not free bank->sectors and bank->prot_blocks of 'virtual'
driver since they were already released by master flash driver.
Change-Id: I01f373d4adb3fc79e2724964926b9276442c5c52
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4504
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
gcc (GCC) 8.1.0 generates new warnings and thus fails the build.
The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and
SMUL instructions decoding.
Reported by Eimers on IRC.
Change-Id: I200c70f75a9e07a1f13a592addc1c5fb37714440
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4526
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Flash loaders refactored to the new style - use generated .inc
instead of hexadecimal machine code in the flash driver source.
Change-Id: If65a2099589e210f9450819b467d67819fd841fc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4439
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Microchip (former Atmel) SAM drivers allocate a struct per chip.
at91sam3, at91sam34:
Deallocate all chip structs from the list at once, on the first bank
deallocation.
at91samd and at91sam4l drivers do not handle more than one bank.
Convert them to simple driver_priv allocation and use
default_flash_free_driver_priv().
Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4416
Tested-by: jenkins
Most of flash drivers have to ensure proper flash write block alignment
and padding. As there was no support for it in the flash infrastructure,
each driver does it its own way. Sometimes this part of code is not properly
tested and contains bugs.
flash_write(_unlock) joins all image sections targeted to one flash bank
using padded areas as a glue. This solves alignment problems on section
boundaries but imposes other problems.
Introduce new flash bank parameters write_start_alignment,
write_end_alignment and minimal_write_gap.
New flash drivers can just properly set these values instead of handling
alignment by its own.
Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command()
and handle_flash_write_bank_command()) to prepare write data padded
to an alignment required by the flash bank.
Rework flash_write_unlock() to discontinue write block when the gap
between sections is bigger than minimum specified in minimal_write_gap.
minimal_write_gap is set to one sector by default.
Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4399
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
'flash erase_check' command runs a check algorithm on a target
if possible. The algorithm is run repeatedly for each flash sector.
Unfortunately every start and stop of the algorithm impose not negligible
overhead.
In practice it means checking is faster than plain read only for
sectors of size approx 4 kByte or bigger. And checking sectors
as short as 512 bytes runs approx 4 times slower than plain read.
The patch changes API call target_blank_check_memory() and related
to take an array of sectors (or arbitrary memory blocks).
Changes in target-specific checking routines are kept minimal.
They use only the first block from the array and process it by
the unchanged algorithm.
default_flash_blank_check() routine repeats target_blank_check_memory()
until all blocks are checked, so it works with both multi-block
and single-block based checkers.
Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4297
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses.
Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b
Signed-off-by: Stefan Arnold <sarnold@sh-sw.de>
Reviewed-on: http://openocd.zylin.com/4260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
HWID originally added in commit 7829f31a6d
was accidentally omited during refactoring in commit
52885d2b53
While on it move old ingeneering sample of 51822 to block of 51822 rev 1
Change-Id: Ie9f15563792a27a72e71df6edbcc6b04490370ed
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4437
Tested-by: jenkins
All drivers which simply allocate one driver_priv memory block
per each bank now use default_flash_free_driver_priv()
Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4417
Tested-by: jenkins
Reviewed-by: Liviu Dudau <liviu@dudau.co.uk>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Protection read and setting of the second flash macro did not work.
Tested on CY8CKIT-046
Change-Id: I67789399ad1e89bbfc23a95547ecca7753130701
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4425
Tested-by: jenkins
flash_write_unlock() sorts sections by base address but does not check
if they overlap. In case of overlapped sections an item of padding[]
array can get negative and padding loop writes out of allocated buffer.
How to replicate: cat two copies of an ihex file to one file and try
to flash it.
Check for overlapped sections and abort write in such case.
Change-Id: I43eee7dc290a8d18faa59567b2118b88ad4bedca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4397
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Add support for more EFM32/EFR32 Series 1 families. The family IDs
come from the DEVICE_FAMILY list in the EFM32GG11 reference manual,
which is the most up to date source I could find. Register locations
have been checked against SiLab's header files.
No datasheets or headers were available for EFR32MG2, EFR32xG14 and
EFM32TG11B, so they are just assumed to follow the pattern. EFM32GG11B
has the MSC registers on a different address compared to other chips.
This commit attempts not to change current behavior when detecting
chips. One detail that has changed is that PAGE_SIZE is read before
applying the workaround for old Giant and Leopard Gecko revisions, but
this is believed to be OK because the register exists but just has an
invalid value in it.
The manuals disagree on which of 120 and 121 is WG, so this commit
leaves it as is.
Change-Id: Ia152b0b9e323defc5158cb02d9a6b04a27008f2a
Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-on: http://openocd.zylin.com/4263
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Flash ROM API command PSOC4_CMD_SET_IMO48 is now optional on new devices.
Also code tidy up:
- improved system ROM call error detection
- probe does not require the target to be halted
- default_padded_value and erased_value set to 0
- fixed endianess problem in flash write and protection setting
- removed fancy chip detection table as it would be updated too often
- psoc4 flash_autoerase is now on by default to ease programming
psoc4.cfg distinguishes chip family and uses either proprietary acquire
function of a KitProg adapter or TEST_MODE workaround to "reset halt"
Change-Id: I2c75ec46ed0a95e09274fad70b62d6eed7b9ecdf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3807
Tested-by: jenkins
Reviewed-by: David Girault <david.f.girault@gmail.com>
Microchip SAM R30 consist of a MCU SAM L21 and a radio.
Similarly SAM R21 = SAM D21 + radio. Therefore SAM R devices
was incorporated into SAM D21 and L21 device groups.
Change-Id: I3448d784cae888070b57c2f504583760ddffc97f
Suggested-by: Martin Deicke <martin.deicke@an-solutions.de>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4282
Tested-by: jenkins
I see no reason for not returning error from target_run_algorithm()
to higher level.
Reported by Clang static analyzer.
Change-Id: Iaaa8b66e487ecae88c0cf4ae2addba63341c032c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4391
Tested-by: jenkins
Reviewed-by: Ivan Meleca <ivan@artekit.eu>
Clang static analyzer says that in certain cases "Assigned value is
garbage or undefined" there.
Change-Id: Ib35a4cf7a553ba9461270a0dc4c4b9b205091e73
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4338
Tested-by: jenkins
Tested on FRDM-K28F. Thanks to Thomas Varghese for donating the kit.
Change-Id: Idcdd8bcf992acebd19e5335f7f833356500c45dd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4255
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Flash Configuration Field on Kinetis devices requires protection
because it is located in program flash space (at 0x400) and writing
an improper data to it may permanently lock the device. Even an erased
flash sector containing FCF engages security lock (not permanent one)
on the next reset or power cycle.
'kinetis fcf_source protection' mode was introduced in the change #3562.
Flash driver in this mode sets FCF immediately after sector erase to
prevent unintentional security lock. To do so the driver needs to know
FCF values before flash image data is actually processed. Flash
protection bits are available in bank structure, FOPT can be set by
'kinetis fopt' command and securing device by FSEC is not supported.
Nevertheless an inexperienced user flashed the device using an image
with FCF values different from those set in OpenOCD config and
concluded programming did not work as some verify errors showed.
This change tries to write maximum possible from image data
retaining FCF protection.
Check FCF in programmed data and report if some field differs from
values set by OpenOCD flash block protection and 'kinetis fopt' command.
Warn user about verify errors caused by FCF protection.
On devices with ECC flash (K26, K66 and KV5x) it is impossible to change
already programmed FCF - it would result in an ECC error. As FCF was
written just after erase in 'kinetis fcf_source protection' mode
the warning issued during flash write is the only possible action.
On non-ECC flash devices use cumulative flash programming to
set FCF values requested in programmed image data.
Use FSEC from programmed data only if it does not request a secure
mode. Device can be secured only in 'kinetis fcf_source write' mode.
Use FOPT from programmed data if its value was not configured
in OpenOCD config by 'kinetis fopt' command.
Change-Id: If65fbbd7700069f57e4ae32234dce371bff93674
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4228
Tested-by: jenkins
Reviewed-by: Robert Foss <robert.foss@memcpy.io>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reading options word can fail, so this needs to be handled.
Reported by Clang static analyzer.
Change-Id: I9754cab9c4446fa2b20d4b44b0e20724d1bc1beb
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4352
Tested-by: jenkins
Reviewed-by: Tim "mithro" Ansell <mithro@mithis.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:
1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:
The previous logic was erroneous. The delay in clock cyles from a bit
written to the jtag interface to a bit read by the jtag interface is:
* The number of BYPASSed TAPs before this (jtagspi) tap
* The length of the jtagspi data register (1)
* The number of BYPASSed TAPs before this one.
I.e. it is just the number of enabled TAPs. This also gets rid of the
configuration parameter DR_LENGTH.
3. Use marker bit to start spi transfer
If there are TAPs ahead of this one on the JTAG chain, and we are in
DR-SHIFT, there will be old bits toggled through first before the first
valid bit destined for the flash.
This delays the begin of the JTAGSPI transaction until the first high bit.
4. New jtagspi protocol
A JTAGSPI transfer now consists of:
* an arbitrary number of 0 bits (from BYPASS registers in front of the
JTAG2SPI DR)
* a marker bit (1) indicating the start of the JTAG2SPI transaction
* 32 bits (big endian) describing the length of the SPI transaction
* a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
* an arbitrary number of cycles (to shift MISO/TDO data through
subsequent BYPASS registers)
5. xilinx_bscan_spi: clean up, add ultrascale
This is tested on the following configurations:
* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E
Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Theese devices do not have a gap in sector numbering.
The driver translates sectors numbers 12 13... to 16 17... as used on dual
bank flash devices. Therefore erase of sector 12 and above fails with error
'stm32x device protected'
on F413/423.
Drop sector number translation for devices without has_large_mem flag.
Change-Id: I65531c0dfe02e2fd0f3d68f0615e0926e9901391
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4299
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A protection block comprises two adjacent sectors in dual bank mode.
As there are 64 and 128kB sectors joined in blocks 2 and 8, block size
should be computed as a sum of sector sizes.
Change-Id: Ie915df8cf7ca232c4565d7e0c514c8933e71fdfe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4271
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
GCC7 with -Wall warns about possible string truncation with
snprint()-type functions with "directive output may be truncated writing
1 byte into a region of size between 0 and 9
[-Werror=format-truncation=]" + "note: ‘snprintf’ output between 5 and
14 bytes into a destination of size 12" (or similar). Fix this by
increasing sizes of buffers.
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Ib848f2a56dd658783534158947ae1be7c0e99d45
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4175
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
GCC7 with -Wextra warns about switch-case blocks which fallthrough with
"this statement may fall through [-Werror=implicit-fallthrough=]". This
can be fixed by adding "special" comments: "/* fallthrough */".
See https://gcc.gnu.org/gcc-7/changes.html
Change-Id: Iba0be791dbdd86984489b2d9a0592bb59828da1e
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/4174
Tested-by: jenkins
Renaming of all nrf51 NOR flash code to nrf5, as to prepare the
code for being able to flash nrf51 and nrf52 chips.
The nrf51 command is retained for backwards compatability.
"nRF5" is also the name Nordic Semiconductor uses to describe
both the nrf51 and nrf52 chips.
Change-Id: I5f4e3f1ec780184b28ad44f735a746e68908c502
Signed-off-by: Slowcoder <slowcoder@gmail.com>
Reviewed-on: http://openocd.zylin.com/4209
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This cleans up the list of supported nrf51 chips considerably.
Change-Id: Ic74685657bb72a8703c0a49df4c48c54604ec2a7
Signed-off-by: Slowcoder <slowcoder@gmail.com>
Reviewed-on: http://openocd.zylin.com/4208
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Trying to read the L0 idcode at the L1 idcode address 0xE0042000 often
resulted in an uncatched error. Reading at the right L0 address 0x40015800
afterwards results in reading 0. So access to the device is denied..
Change-Id: I6de92cf99a5d5d46c72f9ba055613cbc5753a951
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3883
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds support for Blue Gecko and Mighty Gecko chips from
Silabs.
They have different EFM32_MSC_REGBASE and LOCK register offset.
Based on the original patch from Andreas Kemnade.
Change-Id: I166c14960ced7c880b68083badd1b31372fefabe
Cc: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-on: http://openocd.zylin.com/4034
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: chrysn <chrysn@fsfe.org>
Use unsigned constant for left shift operation in order to avoid the
following error with GCC >= 6.0:
../src/flash/nor/stm32f2x.c: In function ‘stm32x_handle_unlock_command’:
../src/flash/nor/stm32f2x.c:1324:67: error: left shift of negative value [-Werror=shift-negative-value]
stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors);
Change-Id: I0ac082bd0dbb8dc2f61ffff8fdf486ab7962d2e0
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4207
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Anton Fosselius <anton.fosselius@gmail.com>
Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com>
IDs for STM32F722, F723, F413 and F423 added, handling of PCROP
for F722/723 and additional nWPRT bits for F413/423 implemented.
The additional protection bit positions for F413/423 conflict
with other options bits for the F7xx variants, additionally the
last two sectors share a common bit.
Protection for F413 and F767/777 now use protection blocks
rather sectors for dealing with protections bits.
Checking for halted state in 'lock' and 'unlock' removed: When
PCROP is activated in F723, halted state is not detected properly,
but lock/unlock sequence is required to disable PCROP.
Tested with STM32F723E-Disco, STM32F413ZH-Nucleo.
Change-Id: Ie6ddab47a9ae8461087d369b4f289b7f9d1e031c
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4045
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
A footnote in RM0038r14.
Change-Id: Ic31894d846fbbe917a7290b2b7ff8fb582bb65da
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4198
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If a MCU has FlexNVM partitioned as EEPROM backup only
(no data flash), kinetis_probe_chip() detects zero fcfg2_maxaddr1
and adjusts flash banks count to 1, what is obviously wrong.
The change limits the test to devices without FlexNVM.
Computation of program flash/FlexNVM blocks is now more robust.
Missing case 0x07 is added to switch (fcfg1_depart)
Change-Id: I0bd6030a0fe1ab62aeb0223bbdf2aee1505bf6a0
Reported-by: simon.haines@scalardata.com
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4180
Tested-by: jenkins
Reviewed-by: Simon Haines <simon.haines@scalardata.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I2692b9877a7f877104528f279a69e8cc1cfbcdbf
Reported-by: David Miller Lowe <milhead@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4173
Tested-by: jenkins
Reviewed-by: Miller Lowe <miller.lowe@trailtech.net>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Recognise the family number for Silicon Labs EZR32HG devices and
select the correct flash page size.
Change-Id: I876e930f3a9f679557fa0d0acac33e9bbfb28c46
Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
Reviewed-on: http://openocd.zylin.com/3934
Tested-by: jenkins
Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Make 'offset' and 'length' parameters optional, if both are omitted
simply read the whole flash bank.
Additionally, check if the 'offset' and 'length' arguments are out of
bounds of the flash bank.
Change-Id: Ib9c1b0538a2c78ebcf702e2da11468dff407f8ff
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3862
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Respect the flash bank boundary and write only to the remaining part of
the bank even if the file content is larger.
Change-Id: I8f4c1b161c103a77bdb30c6bf052293b5ed48c41
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3861
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Make the 'offset' parameter optional, if omitted simply start at the
beginning of the flash bank.
Additionally, check if the argument is out of bounds of the flash bank.
Change-Id: I8e9632b539ad9e83211e1ac6a06da4c8109cbc60
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3860
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Respect the flash bank boundary and compare only the remaining content
of the bank even if the file content is larger.
Change-Id: I4d75979c7893fdd4d18372fa6b0321a0486b4fa9
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3859
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add support for flashing newer members of the NXP Kinetis KW family
Supported devices:
- KW20Z
- KW30Z
- KW40Z
- KW21Z
- KW31Z
- KW41Z
The earlier KW2xD and KW01Z devices are already supported by the code
for the older K-series.
Verified working on the FRDM-KW41Z development board.
Tested flashing both via GDB `load` and directly via OpenOCD flash
write commands.
Change-Id: I73eae477127a8b54a33005b3b526b5439450a808
Signed-off-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-on: http://openocd.zylin.com/4104
Tested-by: jenkins
Reviewed-by: Johann Fischer <johann_fischer@posteo.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This device differs a lot from others in KL series.
Unfortunately the System Integration Module, where device
identification resides, moved to a new address so probe now have
to try both addresses of SIM_SDID.
Introduce a new bank creation option: -sim-base to ensure error free probe.
WDOG32 is slightly different from KE1x and on different address.
System Mode Controler changed layout to word aligned.
Change-Id: I2c9dca0c4ad4228fcc941d6078d15f5e394833ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4059
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Active watchdog forces reset during armv7m_checksum_memory()
in verify_image command if run just after reset init.
COP watchdog in KL series and WDOG32 in KE1 series
have longer timeout however they need to be disabled too.
The change extends 'kinetis disable_wdog' command to optionally
probe the chip and use appropriate algorithm to disable watchdog.
Setting of cache type is also split from flash_support flags.
Tcl command 'kinetis disable_wdog' is called in reset-init event.
Change-Id: I3191e230f38b679ed74f2a97fe323ef8fb3fe22e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3901
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Kinetis flash driver services huge number of MCU types. They have
one, two or four flash banks with option of FlexNVM. It would
require ~36 config files just for Kx series, more for KLx, KVx and KE1x.
The change implements alternative approach:
- configuration file creates just one pflash bank (common for all devices)
- when a device is probed, additional pflash or flexnvm banks are created
based on flash layout of the connected MCU
- created banks have names with optional numbering e.g. kx.pflash0 kx.pflash1
kx.flexnvm0 kx.flexnvm1
- the first bank gets renamed if numbering is used
Automatic bank creation is enabled by tcl command 'kinetis create_banks'.
Used solution has a drawback: other banks than pflash0 are not accessible
until pflash0 is probed. Fortunately gdb attach and standard programming
accesses banks in right sequence.
Change-Id: I5b9037cbefdb8a4176b7715fbcc3af4da4c1ab60
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3925
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Kinetis flash driver probed and decoded chip repeatedly for each flash
bank. Bank ordering used global bank number so multi-target
configuration was broken.
The change introduces kinetis_probe_chip() which reads SIM SDID
and SIM FCFG registers, decodes Kinetis series and family
and fills struct kinetis_chip. This probe runs once for all banks.
struct kinetis_chip contains pointers to all flash banks embeded
in the MCU. It simplifies iteration over all or specific MCU banks.
kinetis_probe_chip() generates MCU name and some informational messages
are improved.
Change-Id: I990db5c63ba490667eec0e5459086d83936662fb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3924
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Real time control MCU has a Cortex-M7 and numerous changes in flash layout.
Introduced a new ID of MDM-AP.
While on it a LOG_DEBUG format error fixed.
Change-Id: I1018660ce0c3dd63ac5e2563408fabff3c3daef7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3900
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Secure devices KL81Z7 and KL82Z7 have no SERIESID field in ID register
so they have to be decoded in Kx branch (not KLx).
The flash controller in KL8x and also in K8x devices does not implement
FTFx_CMD_BLOCKSTAT command. Fix kinetis_blank_check() to work properly
using FTFx_CMD_SECTSTAT command only.
Introduce a new flag FS_NO_CMD_BLOCKSTAT to avoid use of FTFx_CMD_BLOCKSTAT
on these devices.
Change-Id: I3ff58718480acd8cce69f618f71667b6b1d9c4f3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3898
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The new Kinetis KE1x families use FTFE flash controller unlike KE0x.
Also SDID coding corresponds to new K, KL and KV families.
That's why KE1x is handled by kinetis driver instead of kinetis_ke
Change-Id: Ibb73e28e41dfbb086e761e1f006b089825dab854
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3896
Tested-by: jenkins
Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Before this change SAMD driver defined "sector" equal to a flash
protection block. Oversize sectors (16kB for the biggest flash size)
made problems for flashing firmware split to two or more parts.
Removed superfluous test of sector protection before erase.
Change-Id: I8e6a6bda6ccd91eda2df67ec48270c69faa1bdd1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3546
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
FWS=6 workaround removed, as this appears to be a copy-paste error
from the SAM3X family. Originally addressed in http://openocd.zylin.com/3837
but not all occurences were removed.
Atmel changed chip naming and removed 91 prefix for atsamg, samd...
Change-Id: Ia2b43da82b2ff9b1c85fdb456a0a198ab095243d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3926
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558
Extended and revised version of my original patch submitted by Dmytro
here: http://openocd.zylin.com/#/c/3390
This driver is using pure SPI mode, so the flash base address is not
used except some flash commands (e.g. "flash program") need it to
distinguish the banks.
Example config with all 3 chip selects:
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
Example usage:
> flash probe flash0
Found flash device 'win w25q128fv' (ID 0x001840ef)
flash 'ath79' found at 0x00000000
> flash probe flash1
No SPI flash found
> flash probe flash2
No SPI flash found
> flash banks
> flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
reading 4096 bytes from flash @0x00000000
wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
0x00000000 in 28.688066s (0.139 KiB/s)
Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: http://openocd.zylin.com/3612
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Micromips is 16bit oriented, branch and jumps are
16 bit based. The upper half 16bits of a 32bit instruction
with the major opcode, must go first in the instruction
stream, hence the SWAP16 macro and swap16 array function,
needed if the code is written as 32 bit word in little endian
cores. Endianess info added to ejtag_iinfo. Pointer to
ejtag_info and isa field added to pracc context.
MIPS32 code are renamed to MIPS32_ISA_...
To select the isa, the new code has an additional isa parameter
(1 for micromips, 0 for mips32).
In JR instruction the isa bit must be set to execute
micromips code.
The suffix u is added to the OP codes to avoid signed/unsigned
comparison errors and to make sure the right shift is
performed logically.
The isa in debug mode is updated in the poll function.
Code for miniprograms, in kernel mode, need to be converted.
CFI code only for mips32.
Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4032
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Silicon Labs EM3587 and EM3588 may have 512K of flash.
This fix allows for 512K to be specifiied on the command line
when flashing a device.
Change-Id: I18cc4bd0d14e1f2069066734a7396bcccf3de941
Signed-off-by: Byron Kubert <byronk@google.com>
Reviewed-on: http://openocd.zylin.com/3795
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Make the 'offset' parameter optional, if omitted simply start at the
beginning of the flash bank.
Additionally, check if the argument is out of bounds of the flash bank.
Change-Id: Id1959eee5c395666c35f26342c3c50134dd564e5
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3858
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
