Cortex-M0+ and M4 motor control MCUs KV10, KV11, KV30, KV31,
KV42, KV44 and KV46 added to SDID identification.
Watchdog disable code changed to work on Cortex-M0+ (KV1x)
Protection size set to 1K for 16K flash devices (KV10Z16)
- cherry picked from Andrey Smirnov's change #2051
Change-Id: Ia6f4868eaf7e2cb6ad6a736210c703a67e0027be
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3235
Tested-by: jenkins
Reviewed-by: Kyle Manna <kyle.manna@fuel7.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Change-Id: I55ab830aed34a02c53f3419facc81c7354368e30
Signed-off-by: Peter D. Gray <peter@conalgo.com>
Reviewed-on: http://openocd.zylin.com/3422
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Färber <afaerber@suse.de>
To avoid conflicts between flash drivers being added, consistently use
an alphabetical sort order for the three places new drivers get added:
* Makefile.am NOR_DRIVERS (note: automake disallows a trailing backslash)
* drivers.c struct flash_driver forward declarations
* drivers.c flash_drivers array
Change-Id: Idcd6a8e12821ef10958a6b3ad7bac0dc63cadd08
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3417
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Taken from git://git.ac6.fr/openocd commit e8ed67c42227b7072
STM32F446 (0x434) now is's own case.
Change-Id: I5061db7102b4c923c9f39d3d2f0cc69d29fca0a4
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3375
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Old code waited only for 7 bytes and didn't handle buffer wrap-around, but
was functional despite.
Change-Id: Iceaf7be1e51368b2ec0a8722cc9ac16d12f9aa63
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3140
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add new structure for for working with FPU thread in thread view.
This modification support both stacking.
When FPU is activated, LR must be validated to check if the FPU
register are push on the stack. This is mandatory to find the correct
stack pointer position.
the modified code was inspired and adapted from
88d2003bb8
Change-Id: I6641926aa14e7216cacb399cbc8bb0db324cc9fc
Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-on: http://openocd.zylin.com/3397
Tested-by: jenkins
Reviewed-by: Sergey A. Borshch <sb-sf@users.sourceforge.net>
Reviewed-by: Harry Zhurov <harry.zhurov@gmail.com>
Reviewed-by: Anton Gusev
Reviewed-by: Михаил Цивинский <mtsivinsky@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested with MKE04Z8VTG4, MKE02Z64VLC4 and MKE02Z64VLD2.
Change-Id: I606e32a2746a3b96d3e50f3656ba78d40c41c1ea
Signed-off-by: Ivan Meleca <ivan@artekit.eu>
Reviewed-on: http://openocd.zylin.com/3380
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
There is no reason why not probe running target.
Initial gdb connect to running target is now possible without
halt in gdb-attach event.
Change-Id: Iacc4a231587d378168b18db871582f1086504831
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3382
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This feature is required for boards that use a programmatical way
to reset the cpu, like the TI Pandaboard with OMAP4. The board only
has a 14 pin JTAG header that doesn't feature SRST and is reset by
direct write to the PRM_RSTCTL register.
iMX6 can be reset through triggering the on-chip watchdog, but for these
methods to work reliably, access through the AHB-AP without interaction
with the CPU core is necessary.
Change-Id: I9a07a536adda83cc2f93e504384c8c7f0306220b
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3359
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch adds a 'ftdi_location' command to select an adapter by usb
bus number and port path.
This is helpful if you have a rack full of adapters in a testing or
manufacturing setup where the only constant is the physical usb bus
location of the adapter you want to address. Vid:Pid are not unique,
serial number _may_ be unique (and maybe not with embedded adapters) but
will change when a new target is plugged.
Specifying a location allows to understand instantly which board failed
bringup or testing.
Change-Id: I403c7c6c8e34fe42041b3f967db80f3160a4f1a3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3351
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add support for S6E2DH MainFlash. VFlash is not implemented.
Briefly tested with SK-FM4-176L-S6E2DH V110 board.
Change-Id: If7c523d8c75307bc1494bbf4cca3eed0272e8e01
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3158
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
These appear to be just additional flash size configurations.
Entirely based on manual, untested.
Change-Id: I4460dc1a588335df8fc0a385d24513a4e35b6951
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3157
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On the ARM PB1176JZF-S the system comes up in secure monitor
mode after reset. However the modebits in CPSR form the value
28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED.
Define this mode to be synonymous to mode 22 (MON) and things
start to work like a charm.
Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-on: http://openocd.zylin.com/3196
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This adds necessary code to obtain data from the Info region which is
not memory-mapped so can't be read the usual way.
With this "flash read_bank" and "flash verify_bank" commands should
start to work as expected for the Info memory block.
Change-Id: I57e4b80fff577500cfa85954b625fe9c9ff92aa5
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3227
Tested-by: jenkins
Reviewed-by: Eldar Khayrullin <eldar.khayrullin@mail.ru>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Instead of documenting the file path as a comment and inline-commenting
the THUMB bytecode, include the hex array via preprocessor.
This assures the path is actually up-to-date and facilitates updating
the code.
Change-Id: Ieb0a7cd0bc14882ac96750f524616d9768a0c6f5
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3134
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Instead of pointing to the assembler sources in a comment and
inline-commenting the THUMB bytecode, place the hex array alongside the
assembler sources and include it via preprocessor.
Originally inspired by a typo in the file path during driver development,
but it also facilitates making changes to the assembler sources.
A Makefile is provided to help automate updating the bytecode. It is not
integrated with the automake system to avoid forcing an ARM cross-compiler
onto every user, i.e. after modifying the sources they need to be rebuilt
in that directory before building the usual way. ARM_CROSS_COMPILE= can
be passed on the make command line to deal with native ARM toolchains
or with varying prefixes of cross-toolchains.
Change-Id: I00ceb980a68c8554a180dd13719ac77b677a8bcd
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3133
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Flash driver for at91sam4 cpu's has been enhanced to recognise and support the SAM4N family.
Change-Id: I50c471a6053b52edffd8efdd8abfe516cc5c55ee
Signed-off-by: Colin Helliwell <colin.helliwell@ln-systems.com>
Reviewed-on: http://openocd.zylin.com/3242
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Error found by static code analysis using the semantic pattern
null_ref2/mini_null_ref2.cocci, see coccinellery.org
Change-Id: Ic817c29f0ccf2b41fc8f7d9a480ad30d6e5b7ab8
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3364
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A copy-and-paste error in the arm_disassembler opcode evaluation
disabled the recognition of MRRC instructions.
According to the arm architecture ref. manual issue E or later, MRRC and MCRR
instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5.
Error found by static code analysis using a semantic pattern to
detect duplicated tests xand.cocci, see coccinellery.org
Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3363
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The flash info command on stellaris platformes
"TI/LMI Stellaris information ... rcc is ..., rcc2 is ..."
presented the actual RCC2 register as rcc and an uninitialized variable
as rcc2 due to a copy and paste error.
Found using the semantic pattern da/da.cocci, see coccinellery.org
Change-Id: I6f920fc3e07fdc085ea8e2248fbc9453eb8393dc
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3368
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A struct member has been initialized twice. Found using the semantic
pattern da/da.cocci, see coccinellery.org
Change-Id: I0320afd60f1ba505758cc5bc0adcf27f572492fb
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3369
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Obsolete C source code semicolons were removed using the semantic patch
semicolon/semicolon.cocci, see coccinellery.org
Change-Id: I153b4995a9e028ebaf5f58c947821dc78345a777
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3367
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Writing to Intel CFI flash with unaligned tail bytes raised a false
error message although all data was programmed successfully. e.g.:
> flash write_image image 0x602e0000 bin
> Programming at 0x602e0000, count 0x00000002 bytes remaining
> couldn't write word at base 0x60000000, address 0x602e0000
> error writing to flash at address 0x60000000 at offset 0x002e0000
Root cause for this false error was a mixup of two result variables
introduced with ecc8041c.
Change-Id: Ib6b85293dbed946a36a307e5b198c47b901145bf
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3233
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is a nRF51822 variant, not a nRF51422 variant.
Change-Id: Ia199e0afa39408d7391a9655bad47eba2fd85f14
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3105
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Simplify by printing one component per call, instead of one complete ROM
Table per call. Print common information the same way for all components,
including ROM tables, because ROM tables (at least the top level) contain
useful information in their identification registers, such as the
manufacturer of the SoC.
Print component designer name using the JEP106 helper when available.
Change-Id: Ic51bccd98acfae6886243500153fbdd567be2fae
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3182
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: James Mastros <james@mastros.biz>
Tested with EES-AA revision chips on Relax Kit for 5V Shields and
Relax Lite Kit.
Change-Id: I17d4479657bad0516d4c10c2ad7e745d59e678b7
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3136
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The cache is forced to zero to match the value expected by the DPIDR read
so the connect sequence is not destroyed by a SELECT update.
However, DPIDR and in fact all registers except address 4 are independent
of the current DPBANKSEL value. Change swd_queue_dp_bankselect() to use
this fact and avoid touching SELECT for those registers.
Change-Id: I0cd11925fb6adef481bbf45cc24ea2c6dab4b6fb
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3231
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Investigation:
- mem_ap_read_buf_u32() no longer exists.
- JTAG_DP_DPACC & JTAG_DP_APACC are defined in adi_v5_jtag.c now.
Change-Id: I136fc3f389a5a4eb9b68bc759ce653b6da7fa75e
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/3243
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
FTFx flash controller requires MCU in normal RUN mode.
Flash cannot be erased, programmed or blank checked in VLPR or HSRUN
modes.
VLPR mode is switched to RUN mode as it does not require any changes
in clock generator setting. VLPR can be active from reset on some
KLx devices (with some FOPT setting) so 'reset init' might not be
sufficient to get device to normal RUN.
Any other mode than RUN or VLPR is reported as an error.
Change-Id: I60f494ce0d534b04870c6219d9b05f66f7244433
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3012
Tested-by: jenkins
Command for partitioning FlexNVM to data flash and EEPROM blocks
Change-Id: Ia0ea65d72b0e5f23da330520284b0bd26435e444
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2991
Tested-by: jenkins
FlexRAM should be requested before any section programming.
Test FCNFG RAMRDY bit before issuing FTFx_CMD_SETFLEXRAM
to speed up operation and to cover pflash only devices.
Change-Id: Ib0f2d8e8ab8b1507cbf2b7f8565178ab79941f5d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2990
Tested-by: jenkins
kinetis_ftfx_command() did not use other struct flash_bank* members
than base->target. Switching first parameter to struct target*
enables use of kinetis_ftfx_command() without unnecessary bank
getting and probing.
Removed kinetis_securing_test: kind of dead code, same function
as command flash erase_address pad 0x400 0x10
Removed "NAND" word from help as flash is obviously NOR
Change-Id: I3f5fc295ef2bf42f3e913549949f2a36377f6367
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2988
Tested-by: jenkins
FlexNVM (data flash) is memory mapped at 0x10000000.
Driver used to send the same address to FTFx controller for erase/write ops.
This was wrong as FTFx accepts only low 24 bits of address.
To fix addressing for flash controller kinfo->prog_base was introduced.
Added FlexNVM protection check, blank check and data flash size calculation.
Blank check cannot use block operation on FlexNVM when EEPROM backup is enabled.
Removed non functional reassign logic and bank_ordinal stuff.
Now one can re-probe FlexNVM banks after nvm_partition change.
Change-Id: Ia60b938266963e5d056701278cdf7bf2f62a429a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2987
Tested-by: jenkins
This patch also addresses a problem with devices where no serial
number is available. For further details, see:
http://repo.or.cz/libjaylink.git/commit/7e0508d8487f65f71411117dff2e0b093e00bc80
Such devices are now ignored if device selection via serial number is
used.
Nevertheless, these devices are still usable by using the USB address
for device selection or just by omitting device selection. The latter
one is only possible if only one device is connected.
Change-Id: I5763db25e97ba3d924cb642da7e64e951e09ecb7
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3225
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Check CMSIS-DAP adapter has serialnumber before pass it to wcscmp.
Keep looking for onother adapter if choosed one doesn't have correct
serialnumber.
Change-Id: I7d386a03cb49b9baf22073ae1c6b14269ed3b618
Signed-off-by: Andrii Anpilogov <anpilog@gmail.com>
Reviewed-on: http://openocd.zylin.com/3226
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is for targets where flash controller has reverse endianness
compared to target. For these, the 'bus_swap' parameter can be given to the
CFI driver, which will cause command CFI commands to be written with
bytes swapped. This is only for x16 CFI flash.
Change-Id: I698b768e92e65d160232e90b0e81a824e3c81a46
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3041
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Due to signal propagation delays, sampling TDO on rising TCK can become
quite peculiar at fast TCK rates. However, FTDI chips offer a possiblity
to sample TDO on falling edge. With this change, stable operation can be
achieved at 30MHz clock even over 10cm ribbon cable.
Change-Id: Icaf240535dae15512e3c60a944e22a5fbc1b0b06
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3180
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Add support for the Intel Quark mcu D2000 using the new quark_d2xx
target.
Changes to the lakemont part are needed for the D2000 core and
backwards compatible with the X1000 one.
Change-Id: I6e1ef5a5d116344942f08e413965abd3945235fa
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3199
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
duration_elapsed and duration_kbps will not modify the struct duration
passed as function argument, hence it should be declared const.
Change-Id: I459c396952c78e907257e2c2f2c630abde92aaa8
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3232
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Commit 830d0c55c0 introduced
a regression in error recovery after reconnect:
If first SWD queue run in dap_dp_init() fails, DP_SELECT
does not get reset.
Change-Id: I947e2afe9933e4645a6141ece7816af8e6082cf2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3194
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Commit fd43be0726 introduced a
regression: since the register names were changed from those
traditional for MIPS to common GDB scheme the code that makes use of
them needs to be changed accordingly.
This commit restores pic32mx flash driver functionality.
Change-Id: Id18c739390fae36737a02dc30c363d0444f53b96
Reported-by: Louis Rannou <louson@users.sf.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3206
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
niietcm4_write() buffer padding:
add correct buffer padding for 16 bytes.
Args check in FLASH_BANK_COMMAND_HANDLER():
first version of the driver had 7 args, current - 6. This patch will fix
error when flash is rejected (current k1921vk01t.cfg has flash bank init
with 6 args).
Timeouts in flash flag checking procedure:
increase timeouts in niietcm4_opstatus_check() and niietcm4_uopstatus_check()
cause there were problems in some hardware configurations.
JTAG ID:
wrong id in k1921vk01t.cfg replaced with right one.
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Change-Id: I84296ba3eb4eeda4d4a68b18c94666f1269a500f
Reviewed-on: http://openocd.zylin.com/3171
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use it to print the manufacturer of detected TAPs
Change-Id: Ic4384c61c7f6f7ae2a9b860a805a5997542f72cc
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3177
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
dap_sync() executes all commands in the JTAG queue and then checks
if a WAIT condition happened inside the last batch. If yes, a recovery
is invoked. If not, processing continues without checking for
errors. This function should be called in long AP read or writes, e.g.
while uploading a new application binary, at intermediate points within
the transfer where the cost of flushing the JTAG queue and checking the
journal doesn't affect performance too much.
Change-Id: I99eeaf47cdf951e15e589a04e74b90b5ce911386
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3181
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
ADIv5 specifies that DP and AP accesses may generate a WAIT
response when the hardware is not able to complete a request for various
reasons in time before the next request is sent. Currently, the software
treats a WAIT response as a fatal error and aborts operation on the DAP.
This patch implements WAIT handling by keeping a journal of all
outstanding and completed accesses, including their response status.
At certain times (when dap_run() is called), the journal is inspected
for WAIT responses and all discarded accesses are replayed to complete
them. Special care is taken to not re-execute already successfully
completed operations.
Change-Id: I2790070388cf1ab2e8c9a042d74eb3ef776aa583
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3166
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Make the J-Link driver handle everything needed for FPGA programming,
this includes arbitrary long scans and STABLECLOCKS command.
Also, bump to the latest upstream libjaylink to properly support this.
This code is heavily inspired by Andreas Fritiofson's ftdi.c.
Change-Id: Ic5fd87aa88b58ff1138dc2e0a197bb52321b1541
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2946
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
BeagleBone debian 7 builds produce:
jlink.c: In function 'jlink_speed':
jlink.c:218:11: error: declaration of 'div' shadows a global declaration [-Werror=shadow]
jlink.c: In function 'check_trace_freq':
jlink.c:1065:54: error: declaration of 'div' shadows a global declaration [-Werror=shadow]
jlink.c: In function 'config_trace':
jlink.c:1101:11: error: declaration of 'div' shadows a global declaration [-Werror=shadow]
Fix this by changing the local variable to 'divider'.
Change-Id: I96a0cc0f7d4d4af5a56aa1e918e5416d3c61cbfe
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3185
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
BeagleBone debian 7 builds produce:
adi_v5_jtag.c: In function 'jtag_ap_q_bankselect':
adi_v5_jtag.c:336:11: error: declaration of 'select' shadows a global declaration [-Werror=shadow]
Fix this by changing the local variable to 'sel'.
Change-Id: I8e29662ac12bc77d38d5064046d59b7364853cd9
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Reviewed-on: http://openocd.zylin.com/3184
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The existing arm_adi_v5.c code decodes CoreSight peripherals based
on the part number field. However, these are specific to a
particular manufacturer (often ARM). The same part number from
two different manufacturers (distinct designer ids) should not
decode as the same CoreSight peripheral.
The Analog Devices ADSP-SC58x and ADSP-BF70x have peripherals that
overlap with existing OpenOCD decoding. The part number is the
same as existing OpenOCD decoding, but have a different JEP106 code.
Most, if not all, of the existing part number entries in
arm_adi_v5.c are probably specific to ARM. Change all entries
suspected to be designed by ARM to match only ARM's designer ID.
However, to preserve legacy behavior, existing non-ARM entries are
encoded with a wildcard so that they will behave in the same way as
the existing legacy code. It is desirable, however, to start
encoding the data with designer codes to avoid such ambiguity.
Revising the code to check both the part number and designer id
seemed to a warrant a const array lookup table instead of a
multi-tiered switch statement.
Also try to sync part identification IDs with relevant ARM docs.
Change-Id: Iac1374e4cfc6f04cebb479c0e3fa9bde527cc4a3
Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
[andreas.fritiofson@gmail.com: change JEP106 to designer ID, cleanup]
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3128
Tested-by: jenkins
The HLA target shares an examine handler with cortex_m but since it
lacks direct access to DAP, some operations need to be omitted.
Change-Id: Ifdd9d3da4a3a3c2e1c9721284b21d041b3ccaa7a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3183
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
work around issues with software breakpoints when the text segment
is mapped read-only by the OS. Set DACR to "all-manager" to bypass
TLB permission checks on memory access.
Change-Id: I79fd9b32b04a4d538d489896470ee30b26b72b30
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3107
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change tests when reading from 'value' in sysfs from =='0' to !='1'.
This guards against broken sysfs GPIO implementations that return
non-zero for high rather than just '1' while still being clean and
correct code. Note that sysfs will never output a leading zero even
in a very broken implementation as that is covered in gpiolib.c, not
the offending driver.
Tested against broken Freescale kernel 3.14.38 on i.MX6SL.
Change-Id: Id05567bb8504b1babef33d6ee5172bceefeca8b8
Signed-off-by: Matthew Campbell <mcampbell@izotope.com>
Reviewed-on: http://openocd.zylin.com/3121
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On JTAG, all reads are pipelined. If you read a register, the result is not
delivered inside the request that issued the read, it is delivered in the
following request. The current code therefore issues a scan of the RDBUFF
register after each read. This adds a superfluous transaction after each
read.
This patch follows a strategy similar to what SWD already implements.
It also leverages that all JTAG reads are pipelined, i.e. the result
will be clocked out in the next JTAG data phase, no matter if it's
READ or WRITE. Therefore it's never necessary to explicitly read RDBUFF
other than for the very last READ before a dap_run().
Change-Id: Ie40b1fef3203f0cdcb503f40dcbd2a68b0f9776c
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3167
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Debug initialization blindly selects AP#0 as default, which is the AHB-AP
in many cases. This sets the default for target_read/write functions.
However, AHB-AP is the wrong choice, because it bypasses caches on read
and write and also makes some peripherals inaccessible (e.g. l2 outer
caches). This patch explicitely selects the APB-AP (debug_ap) as the
default.
Change-Id: I13f9e0750186d35dcfc135c8d67d437c5884d9c4
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3113
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Remove entirely the concept of a "selected" AP that has to be maintained
between calls. All the information the DAP ops need are now provided to
each call through the AP/DAP pointer.
Consolidate the cache of the SELECT fields into one single field caching
the entire register.
Change-Id: I2e1c93ac5ee8ac38a7d680ca2c660c30093a6b87
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3165
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Move the mandatory dap_ap_select() call into the dap_queue_ap_read/write
wrapper.
This avoids the need for dap_ap_select() and the notion of a "current" AP
within target code.
Change-Id: I5cde8f3eef2c662f7458be6f3b3dd44ea693bd74
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3164
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Make dap apsel without arguments show current state instead of changing
to AP 0.
Change-Id: I75ea10e3e1b8a067f2dc417ec6691dc7ceec1af6
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3163
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
All AP operations should select the AP to use before calling it so
there's no point in restoring the previous value afterwards.
The explicit call to dap_ap_select() before all AP operations should be
moved into dap_queue_ap_read/write() which then would have to take the
AP as an argument instead of the DAP.
Change-Id: Icacb0c76ef2a5ac36b4d2f26b52ec01a8850286e
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3156
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
It's currently set during target creation but the AP that will be used
for the target is not even known.
Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3155
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The AP for which the TAR/CSW is printed may not be the one that caused
the failure. Remove the flawed output entirely. The correct info is
printed in mem_ap_read/write anyway.
Change-Id: I97580a0662dcf02e80646e45445cdbfc251122d8
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3154
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
All mem_ap_* functions now make sure the SELECT register is updated with
the AP number that it's operating on. This shouldn't have to be handled
explicitly.
Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This function does two separate things, powering up the DP and setting
up a MEM-AP. But the DP needs to be powered before even searching for a
MEM-AP to initialize and targets may have multiple MEM-APs that need
initializing.
Split the function into dap_dp_init() and mem_ap_init() and change all
call sites to use the appropriate one.
Change-Id: I92f55e09754a93f3f01dd8e5aa1ffdf60c856126
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3151
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reduce use of magic numbers and add AXI type MEM-AP detection. Don't try
to call dap_rom_display on a non-existent AP.
AP identification is unique per designer, so make sure the JEDEC code
matches ARM when interpreting the AP type.
Change-Id: I8e86b7de61811382afe99bf15094ab71b43f5fdf
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3150
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Change the debug_ap and memory_ap fields of the cortex_a target and
the debug_ap field of the cortex_m target to be pointers to the
struct adiv5_ap instead of AP numbers in some known DAP.
This reduces the dependency on the DAP struct in the targets and
enables MEM-AP accesses to take the relevant AP as parameter.
Change-Id: I39d7b134d78000564b7eec5bff464adf0ef89147
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3147
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This required fixing the AP ID parsing in dap_find_ap() to
match IHI0031C. The AXI type was added too.
Change-Id: I44577a7848df37586e650dce0fb57ac26f5f858c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3146
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This will make it possible to reference directly the AP used for debug
in the target instance and remove the DAP reference. This will in turn
enable getting rid of the need to select an "active" AP in the DAP (using
dap apsel).
Change-Id: I265846a427c714204f4fd3df3cdb75843686c2d0
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3144
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Not clear what it was supposed to be used for. It probably shouldn't.
Change-Id: Ife1d833e59ba80f93876447d752a0ca7e7b57b0f
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3143
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be
able to pass a pointer to it to one common JTAG function which anyway
only uses the TAP field.
Refactor the function to take a TAP directly, remove the legacy struct
from cortex instances and store the TAP pointer only in the DAP.
Cortex-M makes a call to arm_jtag_setup_connection() with the struct
but the function does nothing useful for a Cortex-M target so remove
the call.
Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3142
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Making the SWD driver aware of the DAP that controls it is a layering
violation.
The only usage for the DAP pointer is to store the number of idle cycles
the AP may need to avoid WAITs. Replace the DAP pointer with a cycle
count hint instead to avoid future misuse.
Change-Id: I3e64e11a43ba2396bd646a4cf8f9bc331805d802
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3141
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Separate out the values from adiv5_dap that are associated with a specific AP into a new struct, so we can properly support multiple APs. Remove the DAP struct from the armv7* structs, because we can have multiple CPUs per DAP, and we shouldn't have multiple DAP structs. Tidy up a few places where ap_current is used incorrectly.
Change-Id: I0c6ef4b49cc86b140366347aaf9b76c07cbab0a8
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2984
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_*
functions and removes mem_ap_* functions. Adds a new debug_ap
parameter to the cortex_m (currently set to zero as in existing code).
Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2983
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
ERROR_WAIT is better than ERROR_FAIL in timeout condition.
Change-Id: Iefe837f276a9091ce6c18db5947212c449f49d89
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2934
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is a TODO in the src/target/arm_adi_v5.h for MEM-AP registers.
Some new registers are introduced in ADIv5.2 specification.
MEM_AP_REG_MGT (0x20) // Memory Barrier Transfer register
MEM_AP_REG_TAR64 (0x08) // Bits[63:32] of Transfer Address
MEM_AP_REG_BASE64 (0xF0) // Bits[63:32] of Debug Base Address
Refer to
7.5 MEM-AP register summary in
IHI0031C: ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
Change-Id: I3bc4296a04c35f5c64f851e5865d3099922613fa
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2904
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Problem
No matter what target->coreid is, it always shows
Detected core 0 dbgbase: ...
In dap_lookup_cs_component(), it decreases the core index value to zero
in order to find the desired core.
The reference to coreidx is necessary considering "a device which has nested
ROM tables, with each core described in its own table." (by Paul Fertser).
Change-Id: I9b56d45d6edf6639e748a625ab27787f8e5a5776
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2902
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
They are only used to initialize the flash bank sectors and never modified.
Explicitly specify the array length while at it.
Cleanup before adding XMC4800 support.
Change-Id: I2985b9a9946b67798dbfd47d8b219d93a7ffc3da
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3131
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
cortex_a_read_apb_ab_memory_fast() uses the wrong order of ITR and DSCR
writes when setting up the transfer. ARM DDI0406C says in C8.2 regarding
"Fast mode" operation to first switch to fast mode and then latch the
instruction in ITR. Current implementation first wrote ITR, causing
the instruction to be executed immediately, then switched to fast mode
without an instruction latched. Repeated reading of DTRTX didn't
execute LDC and thus replicated its current content into the whole buffer.
This patch uses the following, revised algorithm:
1) switch to non-blocking mode and issue the LDC for the first word
2) if more than one word is to be read:
- switch to fast mode
- latch the LDC instruction into ITR (it is _not_ executed)
- issue (count-1) reads of DTRTX register, each read returns the current
content of DTRTX and re-issues the latched instruction
-> now the second-to-last word is in the buffer and the LDC for the last
word has been issued.
3) wait for the last instruction to complete
4) switch back to non-blocking mode
5) Read DTRTX for the last (or: only) word and put it into the buffer
Change-Id: I44f5c585962ffa5af257c3d5a2a802c122b6b1e4
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3122
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
When accessing memory through the ARM core, privilege levels and mmu
access permissions observed. Thus it depends on the current mode of the
ARM core whether an access is possible or not. the ARM in USR mode can
not access memory mapped to a higher privilege level. This means, if the
ARM core is halted while executing at PL0, the debugger would be
prevented from setting a breakpoint at an address with a higher privilege
level, e.g. in the OS kernel. This is not desirable.
cortex_a_check_address() tried to work around this by predicting if an
access would fail and switched the ARM core to SVC mode. However, the
prediction was based on hardcoded address ranges and only worked for
Linux and a 3G/1G user/kernel space split.
This patch changes the policy to always switch to SVC mode for memory
accesses. It introduces two functions cortex_a_prep_memaccess() and
cortex_a_post_memaccess() which bracket memory reads and writes. These
function encapsulate all actions necessary for preparation and cleanup.
Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3119
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
when disabling the mmu to access physical addresses, normally the d-cache
must be disabled as well. Disabling the d-cache also requires a full
clean&invalidate. However, since all memory writes are treated as write-
through no-allocate and memory reads do not allocate cache lines,
effectively the d-cache state does not change at all. We can therefore
save the the d-cache disabling and flushing.
This patch also simplifies the function a bit.
Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3114
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
for minimal impact on the hardware state, force all memory accesses to
bypass the caches and tlbs. This may actually be the default, but ARM
recommends in DDI0406C to set proper default values on debug init.
Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3079
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Other cache functions use an updated pattern for the address range loop.
Bring dcache clean and flush functions in line.
Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3035
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint,
to make sure the d-cache is clean and invalid at the breakpoint
location down to PoC.
Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint
again, so that d-cache will pick up the modified code.
Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint
to memory to make the change visible to the CPU.
Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3033
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
D-Cache invalidate is a dangerous operation. It will only work correctly
if full cache lines are invalidated. When partial cache lines are
invalidated, i.e. the target address range does not start and end
at a cache line boundary, cpu data writes outside of the target range
will be dropped. This patch adds special treatment for partial cache
lines by doing a clean & invalidate on the partial lines before
invalidating the rest of the range.
Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The following changes are implemented:
- Clean&Invalidate the VA range to PoC *before* the write takes place
- Remove SMP handling since DCCIMVA instruction already maintains SMP
coherence.
- Remove separate Invalidate step
Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3027
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This patch adds a function for cleaning & invalidating a virtual
address range from the architecture caches down to the point of
coherence.
Change-Id: I4061ab023a3797fabc967f3a34498034841d52c6
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3026
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
There's only one function left that handles cache info display,
no need any more for a function pointer and runtime initialization.
Change-Id: I90b09577f81607917b11f0ab5600a0e2dce223e2
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3025
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
ARMv7 architecture allows up to 7 cache levels that are architecturally
visible, as opposed to "system caches", which are outside of the domain
defined by ARMv7 and require separate management. This patch enables
detection and identification of caches at all levels. It also implements
a new "flush-all" function that cleans & invalidates all cache levels to
the "Point of Coherence".
Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3024
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This patch is on the path to unified handlers for both inner and
outer caches. It removes the special overrides installed when
an outer cache is configured.
Change-Id: I747f2762c6c8c76c700341cbf6cf500ff2a51476
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3022
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The outer cache is not necessarily at L2 in a system. Rename functions
to make that clear.
Change-Id: Ia636a4844f50634f2bdf5cdce285febc1a47c11f
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3020
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch introduces, new command set and handlers for l1 and l2x caches.
Patch set 10 folded the following changes into this one:
Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415
If8d87a03281d0f4ad402909998e7834eb4837e79
I0749f129fa74e04f4e9c20d143a744f09ef750d8
Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/2800
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This was needed for ahb access
Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2796
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Problem
dap->ap_current is register value, not field value.
it restores invalid ap when it calls dap_ap_select(dap, ap_old) later.
* assume the current ap is 1, dap->ap_current value would be (1 << 24).
ap_old = dap->ap_current; <-- ap_old = 1<<24 = 0x1000000.
...
dap_ap_select(dap, ap_old); <-- select 0x1000000, not 1.
* All AP registers accessing fail afterwards.
One of the reproducible case(s): CORE residents in AP >= 1
dap_lookup_cs_component() being used to find PE(*).
In most cases, PE would be found in AP==0, hence the problem is hidden.
When AP number is 1, dap->ap_current would have the value of 1<<24.
Anyone get the AP value with dap->ap_current and resotre it later would
select the wrong AP and all accessing later would fail.
The ARM Versatile and/or FPGA would have better chance to provide this
kind of environment that PE residents in AP>=1. As they have an 'umbrella'
system at AP0, and main system at AP>=1.
* PE: Processing Element. AKA Core. See ARM Glossary at
http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014g/ABCDEFGH.html
Fix
Use dap_ap_get_select() to get ap value.
a. Retrieve current ap value by calling dap_ap_get_select();
src/flash/nor/kinetis.c
src/target/arm_adi_v5.c
b. The code is correct (dap->ap_current >> 24), but it's better to use
dap_ap_get_select() so everything could be synchronized.
src/flash/nor/sim3x.c
Change-Id: I97b5a13a3fc5506cf287e299c6c35699374de74f
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2935
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
If supported, the maximum transport speed is now retrieved from the
device.
Change-Id: I614f405ec91cf199c851781785fd26cbd10c37a6
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2955
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch uses libjaylink which is a library to access J-Link
devices. As other tools which are not in the scope of OpenOCD also
need to access J-Link devices a library is used. A firmware upgrade
tool and an advanced configuration tool for J-Link devices are under
development.
Further versions of libjaylink will support additional features
OpenOCD could benefit from. This includes TCP/IP as additional
possibility to connect to J-Link devices as well as power tracing and
device internal communication. The latter is used to access
peripherals on some development boards (e.g EFM32 STK and DVK).
Integration of libjaylink is realized with a git submodule like
jimtcl. As libjaylink depends on libusb-1.0 only, no additional
dependency is introduced for OpenOCD.
All low-level JTAG and SWD implementations of the current driver are
left untouched and therefore no incompabilities are to be expected.
Improvements of this patch:
* Support for more USB Product IDs, including those with the new
scheme (0x10xx). The corresponding udev rules are also updated.
* Device selection with serial number and USB address.
* Adaptive clocking is now correctly implemented and only usable for
devices with the corresponding capability.
* The target power supply can now be switched without the need for
changing configuration and power cycling the device.
* Device configuration is more restrictive and only allowed if the
required capabilities are available.
* Device configuration now shows the changes between the current
configuration of the device and the values that will be applied.
* Device configuration is verified after it is written to the device
exactly as the vendor software does.
* Connection registration is now handled properly and checks if the
maximum number of connections on a device is reached. This is also
necessary for devices which are attached via USB to OpenOCD as
some device models also support connections on TCP/IP.
* Serial Wire Output (SWO) can now be captured. This feature is not
documented by SEGGER however it is completely supported by
libjaylink.
This patch and libjaylink were tested on Ubuntu 14.04 (i386),
Debian 7 (amd64), FreeBSD 10.0 (amd64) and Windows XP SP3 (32-bit)
with the following device and target configurations:
* JTAG: J-Link v8.0, v9.0 and v9.3 with AT91SAM7S256
* SWD: SiLabs EFM32 STK 3700 (EFM32GG990F1024)
* SWD: J-Link v8.0, v9.0 and v9.3 with EFM32GG990F1024
* SWD: XMC 2Go (XMC1100)
* SWD: XMC1100 Boot Kit (XMC1100)
* SWD: IAR Systems / Olimex Eval Board (LPC1343F)
* SWD: Nordic Semiconductor nRF51 Dongle (nRF51422)
* SWD: SiLabs EZR32 WSTK 6220A (EZR32WG330FG60G)
Except for Windows XP all builds are tested with Clang in addition to
GCC. This patch and libjaylink are not tested on OSX yet.
Change-Id: I8476c57d37c6091c4b892b183da682c548ca1786
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2598
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
http://support.code-red-tech.com/CodeRedWiki/DebugAccessChip
> Note that once you have recovered debug access to your MCU, then in most cases you should then modify your Debug Configuration to turn vector catch off again. If this is not done, then this can cause problems in some circumstances with some versions of the Code Red IDE. For example with NXP LPC13xx parts, connecting more than once to the MCU with vector catch enabled can lead to the part ID being incorrectly read - which can again cause debug connections to fail
This patch adds an alternative part ID for LPC1343. With this patch "program" command works fine for flashing.
Change-Id: I8632e898a4c33102455925d25715b4f4edfa1d97
Signed-off-by: Jakub Kubiak <jakub@kubiak.es>
Reviewed-on: http://openocd.zylin.com/2782
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This adds docs, example config, flash driver.
Driver is only supports K1921VK01T model for now.
Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f
Signed-off-by: Bogdan Kolbov <kolbov@niiet.ru>
Reviewed-on: http://openocd.zylin.com/3011
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The probe and info methods had duplicate sections decoding family names
to generate a human friendly part name. Extract this to a common
helper.
Change-Id: I4c6309d83c601e154b7c14ad9c15c53854ee1e98
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2932
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Basic basic support to get running, magic numbers taken from revision
0.90 of the reference manual.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Change-Id: Iff6ab94d30698f056ef09f7a856b7285fed8f441
Reviewed-on: http://openocd.zylin.com/2931
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
By saving a pointer to the tail of the list,
we don't need to traverse the entire command
queue before we're able to append an item to
it.
With this patch, I see a 10% improvement when
using the embedded XDS100v2 on AM437x IDK board
to load a 4MiB binary (linux zImage) to DDR
with load_image.
IOW, we went from ~305kB/sec to ~336kb/sec.
Change-Id: Idb55d49f0d0106043374ab520b2f3b6b32f2c50f
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2709
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Daniele Emancipato <daniele12457@hotmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The svf_progress_enabled variable is global, hence its lifetime is not
limited and it retains the value from the previous run. Fix this by
explicit assignment.
Change-Id: Id6f4fa88f39521606342a37f6876a0948ac5406e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3111
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This makes SVF error output match actual line numbers in the file
processed.
Change-Id: I1fa4b9d0891e4358b7beada516945d5331ebe182
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2945
Tested-by: jenkins
Kinetis driver checks MDM STAT register to detect secured state of MCU.
An unsecured clean device typically triggered a huge fat alarm message.
Now when driver detects secured state it tries to halt MCU and then
re-reads status register.
Command "mdm mass_erase" used to deassert reset when finished
and MCU started looping in hard fault - WDOG reset cycle.
Now "reset halt" is issued. Clean flash is not run after mass_erase.
Change-Id: I23f393509fbd8751d44ffc744ff2d67f1074f74e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3010
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
SAMD driver suffered from following problems:
1) Flash was erased as an integral part of flash write.
It was not documented so with usual workflow it resulted
in erasing flash twice (and reducing flash lifespan)
and in almost double flashing time.
2) Sector erase was silently skipped if "is_erased" flag was set.
"is_erased" logic was not reliable, e.g. when a row write
was aborted after successful write of some pages, sector was
still considered as erased. "is_erased" flag could not
cope with flash writes from a user program.
3) Writing of a block with start address unaligned to a flash page
resulted in failed assert and OpenOCD abort.
4) Disabling cache in bit 18 of 16-bit halfword never worked.
MCU implements cache invalidate in hardware so there is no need
to take care about. This bug was reported by Tony DiCola.
New code does not erase flash in write operation.
Instead it traditionally relies on erasing flash beforehand.
"is_erased" logic and cache disabling is completely removed.
It simplifies write procedure a lot and flash write is now faster.
The change partly solves ticket #109 SAMD/SAM4L driver doubles flash erase.
Change-Id: I582b497d01a351575533a1f8c9810a4413be0216
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3045
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds support for the Atmel SAML21 variant B parts.
There is minimal change between the two variants, but in
variant B the automatic page write which the at91samd flash
driver relies on to be enabled is disabled by default.
With this patch the write row function will now issue a page write
command after each of the four pages in the row if the MANW (manual
write) bit is set. This also fixes flash write for the SAMC20/SAMC21
devices which have the MANW bit set by default as well.
I have also moved the device ID (DID) register bitfield extraction
from the find_part into helper macros. These can be used in the future
if there are more workarounds for specific devices.
Tested (programming) on:
ATSAML21-XPRO
ATSAML21-XPRO-B
SAMC21 Xplained Pro
SAMD21 Xplained Pro
SAMD20 Xplained Pro
Change-Id: I401a8aa1efd64730840c0d62cf49a1e880ea5900
Signed-off-by: Andreas Loehre <alohre@gmail.com>
Reviewed-on: http://openocd.zylin.com/2903
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cmsis-dap protocol has both DAP_Connect and DAP_Disconnect commands.
Logically if cmsis_dap_swd_switch_seq() calls DAP_Connect in connected
state it should call DAP_Disconnect first.
Doing so surprisingly solves problems on Atmel EDBG with target SAMD/R/L/C.
Without this change SWD communication breaks after reset run/halt
in config "reset_config srst_only" and reconnect trials repeatedly
fail with "SWD ack not OK: 0 JUNK"
Change-Id: Ie951098d5e0c83f388e2df414608aaabec2135c9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3098
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Atmel introduced a "Device Service Unit" (DSU) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604
Atmel's EDBG adapter handles DSU reset correctly without this change.
An ordinary SWD adapter leaves TCK in its default state, low.
So without this change any use of sysresetreq or srst
locks the chip in reset state until power is cycled.
A new function dsu_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and DSU reset is released then.
Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is
lowered a bit to ensure a margin for RC oscillator frequency deviation.
adapter_nsrst_delay 100 is commented out because is no more necessary after
http://openocd.zylin.com/2601
Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2778
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
According to Infineon, XMC4500 EES AA13 with date codes before GE212 -
as seen on an XMC4500 General App Kit - had a zero SCU_IDCHIP register.
Handle this by extending our checks to not error out on zero SCU_IDCHIP
and by printing a useful info string in that case.
Change-Id: Ic2d641a314627dd5a1ff775a0113999191b95e3d
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2751
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
This is a complete flash driver for the Infineon XMC4xxx family of
microcontrollers, based on the TMS570 driver by Andrey Yurovsky.
The driver attempts to discover the particular variant of MCU via a
combination of the SCU register (to determine if this is indeed an
XMC4xxx part) and the FLASH0_ID register (to determine the variant).
If this fails, the driver will not load.
The driver has been added to the README and documentation.
Tests:
* Hardware: XMC4500 (XMC4500_relax), XMC4200 (XMC4200 enterprise)
* SWD + JTAG
* Binary: 144k, 1M
Note:
* Flash protect only partly tested. These parts only allow the flash
protection registers (UCB) to be written 4 times total, and my devkits
have run out of uses (more on the way)
Future Work:
* User 1/2(permalock) locking support via custom command
* In-memory flash loader bootstrap (flashing is rather slow...)
Change-Id: I1d3345d5255d8de8dc4175cf987eb4a037a8cf7f
Signed-off-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2488
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a driver for the Atmel Cortex-M7 SAMV, SAMS, and SAME.
I started with the at91sam4.c driver and then restructured it
significantly to try to simplify it and limit the functionality
to just a flash driver, as well as to comply with the style guide.
Change-Id: I5340bf61f067265b8ebabd3adad45be45324b707
Signed-off-by: Morgan Quigley <morgan@osrfoundation.org>
Reviewed-on: http://openocd.zylin.com/2952
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 68101e67ac introduced a
regression which resulted for ever-growing registers list (as output
by "reg" command), its contents were doubled every reset (actually,
every examination).
Change-Id: Ie3409c795160a2fc840a5e8a892928df0bcc0c57
Reported-by: Daniele Emancipato <daniele12457@hotmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3100
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This patch brings the calculation of the address ranges handled by
ttbr0 and ttbr1 registers in line with ARM DDI 0406C, Table B3-1
Change-Id: Ib807c4b1cb328a6f661e1a0898e744e60d3eccac
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3006
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
If ttbcr is changed after the debugger has examined a target for the
first time, address translations may fail. This problem does not show up
with Linux because it doesn't use ttbr1, but it shows with other OS that
use this feature. If the debugger connects to the target while it's in
u-boot, all address translations will fail after the OS has booted and
the target can not be debugged.
This patch reads the ttbcr in armv7a_mmu_translate_va() and compares it
a cached value. If a difference is detected, armv7a_read_ttbcr() is called
to re-parse the ttb configuration and update the cache.
Change-Id: I1c3adf53ea9d748a0e1e3091d9581e5c43ed64e8
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3005
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
kinetis_write() with byte count not divisible by prog_section_chunk_bytes
computed wrong wc and therefore paded section chunk by some
random data instead of 0xff
Change-Id: Ic7c66d8a3ceacda9e611e98b9fbf943b8001774b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2994
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Kx devices with FTFA flash need the watchdog disabled when programming.
I tried to keep overhead as small as possible and re-use registers that
were already inquired (e.g. sim_sdid).
Change-Id: Ibc29a26ec34102d78a6c3920dd16f63e134a8f6f
Signed-off-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-on: http://openocd.zylin.com/2986
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This makes it easier to relocate the install tree of OpenOCD from where
it was originally built (for example, if put onto a different machine),
without having to change scripts or add something to the command line
every time.
Change-Id: Ia5edf0eba166f7a999f267bd6a92402dab9b399e
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3004
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The memory leak occurs when opening a file fails. It can be
reproduced by using the "flash verify_bank" command with a filename
that does not exist.
Change-Id: I60b7b545c18793d750ff75d08124fde3f0aa6f64
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2998
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If we work on smp system, the output of step command will depend
on Id of default target.
This patch adds additional information to help find what on which
core is happening.
Example of LOG after this patch.
imx6.cpu.1: target state: halted
^^^^^^^^^^
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x60000093 pc: 0x80076c0c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
imx6.cpu.0: target state: halted
^^^^^^^^^^
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x20000193 pc: 0x802ccb6c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
Change-Id: I536a2cce33b5ab10af9de2a43b9960320c17729f
Signed-off-by: Oleksij Rempel <external.Oleksij.Rempel@de.bosch.com>
Reviewed-on: http://openocd.zylin.com/2691
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A segmentation fault in cortex_m_endreset_event() is sometimes raised
with very broken target like Kinetis Kx with erased flash and active WDOG.
Debugging revealed that cortex_m->dwt_num_comp is 4 and
dwt_list is NULL at cortex_m:290
Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2989
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Memory for the symbol table was allocated by malloc but not initialized other
than with the symbol name. Therefore `address` and `optional` members were
having arbitrary values leading to every symbol being optional most of the
time which messes up RTOS auto-detection. Memory will now be zero-initialized
as in other RTOS implementations.
Change-Id: I6c6e31ec1ef7e043061adf8c695b2139620e005d
Signed-off-by: Daniel Krebs <github@daniel-krebs.net>
Reviewed-on: http://openocd.zylin.com/3017
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
According to "man 2 poll" the correct header to include is poll.h, not
sys/poll.h. Reported by a build against musl.
Change-Id: I5298b49dc947d1a368e423104c0c0c7b9bdd1a10
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2947
Tested-by: jenkins
In the case that the STKALIGN bit is set on Cortex M processors, on
entry to an exception - the processor can store an additional 4 bytes
of padding before regular stacking to achieve 8-byte alignment on
exception entry. In the case that this padding is present, the
processor will set bit (1 << 9) in the stacked xPSR register. Use the
new calculate_process_stack callback to take into account the xPSR
register and use it on the standard Cortex_M3 stacking.
Note: Change #2301 had some misinformation regarding the padding. On
Cortex-M the padding is stored BEFORE stacking so xPSR is always
available at a fixed offset.
Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed
to a '1' such that this alignment always occurs on non-aligned stacks.
Behavior of xPSR verified via the (bad-sorry) assembly program below by
setting a breakpoint on the SVC_Handler symbol. The first time
SVC_Handler is triggered the stack was 0x20000ff8, the second time
SVC_Handler is triggered the stack was 0x20000ffc. Note that in both
cases the interrupt handler gets 0x20000fd8 for a stack pointer.
GDB exerpt:
Breakpoint 1, 0x000040b6 in Reset_Handler ()
(gdb) hbreak SVC_Handler
Hardware assisted breakpoint 2 at 0x40f8
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$3 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40ce 0x21000000
0x20000ff8: 0x0
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$4 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40e8 0x21000200
0x20000ff8: 0x0
Assembly program:
.cpu cortex-m0plus
.fpu softvfp
.thumb
.syntax unified
.section .vectors
@ pvStack:
.word 0x20001000
@ pfnReset_Handler:
.word Reset_Handler + 1
@ pfnNMI_Handler:
.word 0
@ pfnHardFault_Handler:
.word 0
@ pfnReservedM12:
.word 0
@ pfnReservedM11:
.word 0
@ pfnReservedM10:
.word 0
@ pfnReservedM9:
.word 0
@ pfnReservedM8:
.word 0
@ pfnReservedM7:
.word 0
@ pfnReservedM6:
.word 0
@ pfnSVC_Handler:
.word SVC_Handler + 1
.section .text
.global Reset_Handler
Reset_Handler:
cpsie i
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear
subs r2, r2, #4
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear2:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear2
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
.loop:
b .loop
.align 4
.stack_start:
.word 0x20000f00
.stack_last:
.word 0x20000ffc
@ first call - 0x2000fff8 -- should already be aligned
@ second call - 0x2000fffc -- should hit the alignment code
.global SVC_Handler
SVC_Handler:
bx lr
Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3003
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Some targets (Cortex M) require more complicated calculations for
turning the stored stack pointer back into a process stack pointer.
For example, the Cortex M stores a bit in the auto-stacked xPSR
indicating that alignment had to be performed and an additional 4
byte padding is present before the exception stacking. This change
only sets up the framework for Cortex-M unstacking and does not
add Cortex-M support.
Note: this also fixes the alignment calculation nearly addressed by
change #2301 entitled rtos/rtos.c: fix stack alignment calculation.
Updated calculation is in rtos_generic_stack_align.
Change-Id: I0f662cad0df81cbe5866219ad0fef980dcb3e44f
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3002
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Intel is relicensing our contributions to OpenOCD under GPL
version 2 or any later version. We previously contributed code
under GPL version 2 only. It was not our intention to differ
from the standard OpenOCD license. We're correcting that here.
This also applies retroactively to previous versions of our
contributions to OpenOCD.
Change-Id: I5e831ed95d03d2044d8e5a8375b21c6e52c933d7
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3044
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
K22FN1M0 and K22FX512 has FTFE flash and old style SDID.
K22FN128, 256 and 512 has FTFA flash and new style SDID
K63 and K64 detects as K61 and K62, see Errata 1N83J e7534
Change-Id: I2aca6f1f18819bb2b2ec4982036510de444ad2ac
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2867
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Patrick Stewart <patstew@gmail.com>
max_flash_prog_size euals to pflash_sector_size_bytes for most of devices.
There is no point setting max_flash_prog_size for devices without
FS_PROGRAM_SECTOR capability.
Check for zero sector_size to avoid div by zero exception in case of
device has FlexNVM but the driver does not define nvm_sector_size_bytes
Change-Id: Iaf4e007fb1ec3d24c373350410e4bebe504a4c3e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2958
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Patrick Stewart <patstew@gmail.com>
The K24 uses the KL-style SDID register and has some flashing quirks, so the kinetis driver does not support it properly.
Extend the chip detection routine to support the new SDID format. Add a parameter for the maximum flash size, as the K24 only supports 1k flashing blocks but has 4k sector size. Remove global 'granularity' array, as it's only really needed in one function. Replace 'klxx' with an enum showing which flash commands are actually supported on a given chip.
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Change-Id: Ie244fab564d58c5cfe4fa36a025f0b2674ffad69
Reviewed-on: http://openocd.zylin.com/2864
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I3cf5ced568319878b8bf40743e4c07718f630c68
Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2953
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Flash driver "mini51.c" and "nuc1x.c" are same target MCU.
This patch integrates each driver and functions,
and makes into new "NuMicro" flash driver.
Change-Id: Ifff5c1cfdd265acca0f489631695be9194fa144c
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2794
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A target config and a simple flash driver for the ADuCM360 microcontroller.
The EEPROM of the chip may be erased and programmed.
Change-Id: Ic2bc2f91ec5b6f72e3976dbe18071f461fe503b8
Signed-off-by: Ivan Buliev <i.buliev@mikrosistemi.com>
Reviewed-on: http://openocd.zylin.com/2787
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
The problem was reported by jstefanop on IRC, the SVF was generated with
Xilinx ISE 14.7.
Found and investigated with Valgrind's vgdb service.
Change-Id: I32b0e77e0380ce4a391661f97449f9c2a5f83625
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2933
Tested-by: jenkins
Currently, the maximum size of a command sent to the TCL server is
4k. This patch increases this limit up to 4M.
Reasoning:
To get high-speed JTAG data transfers, I'm using a very long shift
register. This reduces the overhead of the state changes, as well as the
latency due to the common USB adapter transfers considerably. In order
to submit those long DRSCAN commands to OpenOCD over the TCL/TCL
interface, long TCL command lines are required. This is enabled by this
patch.
v3:
Address review comments. Drop line instead of connection when realloc()
fails.
Changes in v2 of this patch:
The line buffer is allocated dynamically to avoid an OpenOCD memory
overhead if the large buffers are not used. The buffer starts at 4K and
increases exponentially up to 1M, and then linearly in 1M increments up
to 4M.
Change-Id: Iecaef6a56ed5e18e9de4d912a514031ea78fa3bd
Signed-off-by: Philipp Wagner <philipp.wagner@tum.de>
Reviewed-on: http://openocd.zylin.com/2837
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add constant CONNECTION_LIMIT_UNLIMITED which indicates a service
has no connection limit
Change-Id: I008d31264010c25fa44ca74eb6d5740eca38bee1
Signed-off-by: Austin Morton <austinpmorton@gmail.com>
Reviewed-on: http://openocd.zylin.com/2937
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Problem
As my compiler has "warnings being treated as errors" on, it shows the
error message:
error: 'retval' may be used uninitialized in this function
Investigation
Nothing wrong with the logic, 'retval' would have a value before returning.
Just wanna get rid of the compiling "warning as error" message.
Solution
Provide a reasonable default value
Change-Id: I712c15f82819c6c48bee9dceca8de4b18aeb29b0
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/2905
Tested-by: jenkins
Reviewed-by: Robert Jordens <jordens@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
During reallocation a new memory region might be allocated and the old
one freed. If jtag queue is holding a pointer to the old memory, it will
segfault during the execution. Avoid this by flushing the queue before a
reallocation attempt is made.
This should fix ticket #102.
Change-Id: I737fc3f1ebf6d76413a475beb8bf20184fe0233f
Reported-by: Alex Forencich <aforencich@users.sf.net>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2899
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Added support for SWD transport similar to sysfsgpio driver.
Added configurable peripheral base address to support Raspberry Pi 2.
Change-Id: If76d45fbe74ce49f1f22af72e5f246e973237e04
Signed-off-by: Christoph Pittracher <pitt@segfault.info>
Reviewed-on: http://openocd.zylin.com/2802
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the chip IDs corresponding to the new 5V "SAMC" parts which are
otherwise identical to the SAMD and should work with this driver. Also
add the configurations for their Xplained Pro boards.
Change-Id: Ic268d4ac384a3a77d4211a94da9f9faf4d8c0f7b
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2809
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This fixes a warning as reported by the current clang version:
../../../../src/flash/nor/sim3x.c:867:20: error: address of array
'sim3x_info->device_package' will always evaluate to 'true' .
Change-Id: Ie160cbe6df8f491e9beff38d47e2f13575529bf9
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2838
Tested-by: jenkins
Reviewed-by: Oleksij Rempel
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Many FPGA board speak JTAG and have a SPI flash for their bitstream
attached to them. The SPI flash is programmed by first uploading a
proxy bitstream to the FPGA that connects the JTAG interface to the
SPI interface if the IR contains a certain USER instruction. Then the
SPI flash can be erase, written, read directly through the JTAG DR.
The JTAG and SPI signaling is compatible. Such a proxy bitstream only
needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
chip select when the IR contains the special instruction and the JTAG
state machine is in the DR-SHIFT state.
Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2844
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The only read access to flash chips so is through the target's
memory. Flashes like jtagspi do not expose a memory mapped interface
to the flash. These commands use the flash_driver_read() driver API
directly.
Change-Id: I40b910de650114a3f676507f9f059a234377d862
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2842
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds an option to disable the use of the JSTART instruction
when loading bitstreams to xilinx fpgas. JSTART apparently prevents
configuration if the startup clock is not set to the jtag clock in
the bitstream.
xc3sprog is omitting JSTART for all devices. Problems with loading a bitstream
that does not have StartupClk:JTAGClk are described here:
http://www.xilinx.com/support/answers/56151.html
Change-Id: I8137c0bae05a8c3c6f8e2611869f70a770d1651d
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2860
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The testee target is usefull for certain non-cpu pass-through
situations, for example in the case of a spi flash mapped to the DR of
a JTAG tap, as is the case for most FPGAs with SPI flashs behind them.
We just manage the RUNNING/RESET/HALTED state in the testee driver to
support it being halted which is a requirement for flash banks.
Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2840
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
* Add USB VID and PID for the J-Link interface running on the Nordic
Semiconductor nRF51-DK. Also tested with debug out port to debug
external boards.
* Elimiantes need for `-c "jlink pid 0x1015"` on the openocd cmd line.
Change-Id: Ib23acb72b9f5183b76fc7dc22b556982869ae830
Signed-off-by: Kyle Manna <kyle@kylemanna.com>
Reviewed-on: http://openocd.zylin.com/2775
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
ThreadX uses two stacking schemas on ARM926E-JS, extend API to use more then
one stecking at time.
Change-Id: I92d445ad0981b6409ea4c4e7e438d3a7ae39cbe7
Signed-off-by: Alexander Drozdov <adrozdoff@gmail.com>
Reviewed-on: http://openocd.zylin.com/2848
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
MMU types were checking and installing fakes at init, but this wasn't catching
all devices. Fixes segfaults when attempting mdw and friends on avr.
Change-Id: I5b11f9913157a21f1aeb11ec852f593b529d9be8
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/2791
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Even though the latest firmware version for stlink-v1 supports "v2"
JTAG API, the hardware SRST handling is still broken; amend the check
accordingly.
Change-Id: I62c662cd7aa209d2d6e9fe260f5c0be81d0ce672
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2761
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add the identifiers to support the flash on the Cypress Type-C Port Controller
chips of the CCG1 family : http://www.cypress.com/ccg1/.
Tested successfully on CYPD1132-16SXI.
Change-Id: I3fe6283379e5bcab964afac31b547ef95535aa2c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://openocd.zylin.com/2757
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
